JPH0214363A - Fast fourier transform method and arithmetic apparatus therefor - Google Patents

Abstract

PURPOSE: To execute the FFT of digital data without using a switch by preventing an input memory and an output memory data word from being transmitted to the other side of a channel except performing the transmission within a Fourier transformation operator. CONSTITUTION: Digital data is received by the window composed of N complex number data words and the data is stored within R independent parallel channels. Next, these data is sequenced within a LogR N serially arrayed stages. Each stage has a Fourier transformation operator 10 having an arithmetic element to be a data address operator FFT or DFT, the RAM for each channel, a rotation factor operator deforming data to be transformed without performing cross channel communication and a new phase system operator. First and third substitution operators are transformed into phase shift operators. By making the complex number data word perform a phase rotation in each channel by these operators, the action which is equivalent to the switching of the data word is made.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF INDUSTRIAL APPLICATION The present invention relates to a method and apparatus for performing a Fourier transform of a set of digital data. In particular, it relates to a processor that performs fast Fourier transform (FFT) on individual signals sampled from continuously received electrical signals.

[Conventional technology]

Such FFT (fast Fourier transform) techniques include the high speed operation of multiple discrete Fourier transforms (DFTs). This DFT is calculated using these individual (
It is used as a tool to explain the relationship between the time domain and frequency domain of discrete (discrete) signals. The number of data words to be transformed by this fast Fourier transform apparatus and method and the DFT (N
From the relationship with the number of operations required to calculate 2),
The efficiency of this is determined.

If multiple small-scale DFTs (eg, with a base R of 2 or 4) can be substituted for large-scale FTs, the number of required operations can be reduced considerably.

Furthermore, the operation of this multiple small-scale DFTs consists of a multi-stage process where each step is similar.

This allows the processor to compute an FFT with fewer unique components. The numbers of these stages B are related based on the sample size and cardinality by B=LogFLN.

However, as the number of calculation stages increases, the calculations become more complex due to rounding errors, and the accuracy of the calculation results decreases. Therefore the sample size is 11
In order to improve the processing efficiency when N I+ increases, the FFT calculation method is obtained by a compromise between the DFT radix number and the number of calculation stages B, and the radix is generally a combination of the switching cost and the number of processing stages in the data bus. Limited to 4 or 8 depending on complexity.

In the past, several unique methods for calculating FFT have been proposed, and when these calculations are performed in hardware, they are realized using different architectural chairs. First of all,
The first conventional example is by Cooley and 7ukey et al., "Math Computer'" 196
April 5th vol 19. “An” on pages 297-301
Algorithm for the Machine
Calculation of Complex Fo
This type includes a "variable geometry," meaning that the data addressing behavior varies from stage to stage.

The second type is the ``constant geometry'' type introduced by Mr. Pease, and the ``Jour''
nal of the As5ocation fo
rCoa+putting Machinery”19
April 1968 vol 15. “Ad” on pages 252-264
aptation of the Fast Four
ier Transform for Paralle
There are 3 articles listed in ``rocessing''. Here, the data address operation remains the same from stage to stage. The realization of this hardware simplification is due to the "rotating element" R for variable geometry types.
A change in the order of OM. In both of these types, the order of the ROM elements changes from stage to stage and is generally handled by an address counter.

A recent development is the introduction of pipeline processors. By this architectural chair.

Since we divide the computational load into sequential parallel stages, R
Simultaneous processing of channels is possible. A well-known example of a pipelined processor in a variable geometry architectural chair is the one published by McClellar and Purdy et al. in “Applications of Digital.
l Signal Processing” 1978
Prentice ) ta11's Alan1/, O
ppenheimi, pp. 268-278. In order not to delay the parallel input rate of data,
The arithmetic element itself in each stage consists of two stages of 4 points l-
FFT (instead of DFTS) and each point is
- Consists of four arithmetic processors per stage.

However, when the number of radixes increases to 8 or more and further parallelization is performed, there is a problem that the number of commutators or crossbar switches increases, resulting in a considerably high cost.

A pipelined FFT processor using a constant geometry architectural chair was developed by Corinthios and published in IEEE Transactions on
Computers.

June 1971 vol, c-20, “The Des
ign of a C1ass.

f Fast Fourier Trans form
Computers", pages 617-623. This architectural chair also requires switching and gating for purposes of cross-channel communication.

Such processors also have complex and large memory requirements, which, as the radix increases,
Furthermore, it becomes unwieldy (i.e., the desired number of memory units is R2 since the memory length is a function of "N/R"). No. 754,128, August 21, 1973, and IEE
Transaction On Computers,
January 1975 vol.1. c-24. “A Parallel Radix4 Fast F” on pages 80-92
Ourier Transform Computer
” is also stated.

Other developments relate to certain features of the apparatus and methods described above. Perry U.S. Pat. No. 4,159.
No. 528 (June 26, 1979) describes the correction of phase shifts introduced by Fourier transforms. This technique utilizes barrel switches and delay elements to perform appropriate phase corrections on the outputs from smaller scale FTs before incorporating them into the larger scale Fourier transform. Also, Mr. McGee's U.S. Patent No. 4,
No. 534,009 (August 6, 1985) implements the aforementioned McClan and Purdy architectural chair and utilizes switches and shift registers to improve the computational efficiency of arithmetic units.

All of these single-channel and multi-channel FFT processor architectural chairs described above require some type of cross-channel communication path using a switch. These channels can vary significantly with time and stage in variable geometry cases.

[Purpose of the invention]

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide an apparatus for performing FFT (Fast Fourier Transform) of digital data in a cross-channel communication path without using a switch.

Another object of the present invention is to provide an apparatus for computing an FFT of digital data by implementing a novel contractile geometry method in which the interstage structure is substantially doubled.

Yet another object of the present invention is to provide an apparatus for performing FFT operations on digital data where the radix size is not limited by the complexity and/or cost of the switching arrangement.

Another object of the present invention is to provide an apparatus that performs FFT calculations on digital data by utilizing the phase shift characteristics of Fourier transform as part of data shuffling.

It is a further object of the present invention to provide an apparatus capable of performing FFT operations on digital data without switching data steps in a cross-channel communication path.

〔Example〕

The invention will now be described in detail with reference to one drawing.

First, the present invention is an apparatus and method for performing fast Fourier transform (hereinafter referred to as FFT), which is based on the above-mentioned P
A new contractile geometry method obtained from the constant geometry method by Ease is computed. Digital data is received in windows of N complex data words and stored in R independent parallel channels.

These data are then ordered into LogRN serially arranged stages. Each stage consists of a data address operator (the NxN matrix is known as the RAM shuffle operator) and an FFT or DFT (known as the kernel).
, a RAM for each channel, a rotation factor operator that transforms the data to be transformed without cross-channel communication, and a novel phase system operator.

Conceptually, this operation is similar to this general-purpose FFT processor (the aforementioned Pease and Corin
This is achieved by factorizing the standard global shuffle operator for each stage, as used in thios (see thios), into three permutation operators.

The second of these permutation operators is forced onto one data element in each channel, thereby giving the second operator to the appropriate kernel. For example, in a radix-4 embodiment, this means four data words: That is, four data words from each of the four channels are simultaneously represented at each stage into a four-point FFT kernel.

Also, convert the first and third permutation operators into phase shift operators. This operator performs a phase rotation on the complex data word in each channel, which is equivalent to switching the data word (obtaining the appropriate data word together with the representation for the nucleus). In such a manner, by utilizing the relatively direct forward addressing of the RAM within each channel, the appropriate data words can be obtained instead of utilizing switches as disclosed in the prior art. .

This example is carried out under the conditions of N=64 and R=4 (that is, three stages occur), with the exception of those specifically described. These values are for illustrative purposes only, e.g.
It is by no means intended to be limiting. Generally, N and R are integer powers of 2, but the method of the present invention is applicable to any base R and sample size N.

The conventional constant geometry FFT operation method can be represented by the following matrix (the order of operations in the matrix is read from right to left); F, , X = F4S
,/,G I D,,F,S,/,G I D64F4S
, /, 6X stage 3 j stage 21 stage 1
where: X: the input row data vector of N=64 complex data words.

S4/, &: A shuffle operator which selects 4 data rods facing 16 data words spaced from the input vector and groups these data together as input for the Fourier transform operator.

F4: Fourier transform operator, which is an N×N square block matrix, containing 4-point D FTs along the block terms.

D641 Dts: Rotating element (twiddl) described later
e factors) F64: DFT matrix with columns in digit-reversed order.

The order of data in the row vector is changed to O, L, 2, by the above-mentioned S4/, shuffle operator. ..., N
-1 sequence is O, N/R, 2N/R, -, (R-
L) N/Rjl.

(N/R) +1, ・[(R-1)N/Rj+1.・
・ Changes to (N/R)-1,...N-1. The same effect is achieved by shifting the R parallel input channels N/[(data words) associated with adjacent channels.

For N=64 and R=4, 0, 1, 2. ..., 63 input sequences are changed as follows: 0, 1.2.・・・・・・・・・、1516.17、
18. ......, 3132.33,34.・
......, 4748.49,50.・・・・・・
..., 53 Operator F4 can be described more accurately as (Ix+, xF4). Here, × is the Kronecker product of two matrices (ronecker prod
uct). As an operator, this 71-lix is equivalent to a 4-point 1-Fourier transform on the 4 data words that are represented at its input, and the complete path is through a window of N complex data words. The process is then repeated for successive groups of four data words until one is formed. N=
The operation is repeated 16 times for 64.

The aforementioned "rotating element" is disclosed in the Pease patent and is defined as follows.

D, 4 = Diag(Its + olf t DL
s z Dxt') Here, these rotational elements are coefficients obtained from the derivation result of the constant geometry FFT using Pease described above. These values can be calculated from the equations above.

is constant for given N and R.

Vector X will be deleted from the discussion below for convenience. What is thus obtained is the matrix factor F□ of the DFT matrix.

According to the consideration of the conventional example described above, a similar shuffle operator and Fourier transform operator exist for each stage. Only the rotating elements are unique at each stage. Additionally, the shuffle operators are global, allowing them to address data from all channels and at larger time intervals than in a window of 64 data words. Due to these characteristics,
The trend is for hardware architectures to be forced into single channel operation.

When the data words enter the second stage, they are no longer in the proper sequence for the next S4/1G operator because they are in the same data channel, so they can be manipulated into the second stage. They need to appear on stage in an appropriate sequence. 1st
With reference to the figure, data words from Fourier transform operator 10 are output into four channels AD in the numerical order shown. However, the input data to the next stage is required in groups of four data words expressed in cycles. Cross-channel communication is required to align these data words to their own appropriate channels.

In the prior art, this was accomplished by using switches. For example, the aforementioned McClellan,
According to the pipeline architecture chair by Purdy, a commutator switch and an FI with different amounts of delay are used.
A combination of FO memories is utilized to perform cross-channel operations.

As a first step in achieving the contractile geometry method according to the invention, and in order to process R parallel channels without switches, we factorize the conventional shuffle operator into the following three operators:

SJ Eng, = SpfS shuffle, where: SPf: Fast circular shuffle (all data words) SPL: Random access memory (RAM) shuffle;
Since we operate on one data word from each channel, separate RAM is available for each channel.

SP = slow circular shuffle (every 4th data word).

This Sp rashal cycle is a set of 4 data words within a larger group of 16 data words. N
= 64, resulting in 4 groups of 16.

The first group of 16 data words does not change at all, and each set of 4 data words within this second group of 16 is rotated by one data word as shown below.

Each of the 4 data words in the 16 third group is rotated by 2 data words and so on.

Cycle through the fourth group by three data words.

Using the constant geometry method described above, replace the second and third stage global shuffles with three permutation operators as shown below (the first stage shuffle remains unchanged): F64:F4SpfS Sp1D
iGF4SpfSe5PID6J+5jxs this it
D ++ Rotation elements are each multiplied by (Sp-'Sp), and Sp is II D I + sp- for factor generation
It is reorganized by passing it through ol,'sρ instead of DIG and passing 5P-1DG4Sp instead of D64 (the first part indicates the reorganization).

Next, each 5p-1 is infused together with Sp from an adjacent channel, and then these are canceled to form the following equation.

FG4=FiSpfSFLI DI G' 5PF4
sPt'sR+ [)G4' 5PF4S+71GS
pf and sp pass through F4, do not transform this F4, and use the phase shift operator and Dp op'
and further form the basic contractile geometry method of the present invention.

Fs4"DPHF4SBIDxi'DPI4F*DPH
'S ID54'F+DPH5*/1g Most of the constant geometry architecture.

Hold together with the differences appearing in the rotation element and phase rotation operator. It also holds a first stage shuffle operator.

The equivalent of cross-channel switching is achieved by phase shift operators Dp and Dp+, which involve transforming the coefficients of a complex data word. These phase shift operators shift the phase of R of the complex data word in each channel by a multiple of 360/R degrees (e.g., for R=4, the phase shift is O for the first channel; π/2 for the second channel, π for the third channel and 3π/2 for the fourth channel, i.e. 1°Jy
(equivalent to multiplying by 1+J).

These operators take advantage of the "shift" property of the DFT kernel, where a cyclic ring shift in the input domain is equivalent to a multiplication by a complex index in the transform domain. These shifts allow data words to be placed in the proper sequence without utilizing data words from other channels, thereby eliminating the need for cross-channel switching.

In FIG. 2, according to the invention, the phase of the data introducing the Fourier transform operator 10 is shifted in the phase shift unit 5 as described above. The data words outputting this FFTl0 are output into four channels A-D in the numerical order shown. In contrast to the order of data words shown in FIG. displayed). The next set of inputs to the next stage, represented by squares, are similarly arranged. These selections and the next set of four inputs from these channels are realized via the RAM address unit 20.

Another phase shift operation is performed after the data is present in the FFT of each stage for the following reasons.

That is, with further reference to FIG.
7, 33 and 49) are parallel, but shifted by one from their appropriate destination RAM.

Again, instead of a switching data path, we use the shifting characteristic (this time in the opposite direction) to further
4 operation unit outputs by an appropriate multiplier (1+J+1
This same effect is achieved by multiplying term-by-term by +J (prepared for R=4). These are simple phase shifts that can be absorbed in the ROM retention coefficients OsG' and DG4', which are typically
It is realized by radix-4 conversion after .

Simplifications in such contractile geometry methods can be achieved by incorporating the phase shift operator with rotating elements. This reduces the computational load, which can be reduced by establishing a single complex multiplication of the data in each channel and replacing the two complex multiplications required for the rotating element and phase shift operators. (input) operations are handled by the ROM unit.

Such a merging (penetration) operation is called direct melting or RA.
This can be achieved by passing the phase shift operation DPH' through the M shuffle operator S, as follows.

1 Penetration Penetration 1 FG4”DPl-IF4Slt Dts”DPMF4
DPH″S艮ld＆4′FnDPH3J工.

Stage 11 Stage 2 1 Stage 3 The final result is a reduced contractile geometry method.

Fe2”DP?1F4SIL DPH2F4Se D
PHtF4D4Sj, s stage 11 stage! -ji21
Stage 3 here.

Dp) 1□"Dts' DPS and opH□=DPH"DI, 4 (DpH" is a rearrangement of DPH'.) Next, referring to FIG. 3, N=64.R= The operation of implementing the contractility method of the present invention using a 4° three-stage FFT device will be described.It is assumed that the data flow moves from left to right.

Shuffle unit 10 receives data words 90 and arranges them into four channels AD. With this shuffle unit 100, the above-mentioned S4/0.
Assuming we perform a shuffle, the data is S,/
The six-phase rotator 110, which can remove this shuffle unit already given in the order given by the shuffle, is a multiplication unit, which shifts the phase of the data word, so that the result is 2
The sequence shown is obtained after the next Fourier transform operation. For radix 4, this phase rotator 110
Simply multiply each channel by the power of j.

For example, channel A is 1 (j'), channel B is j (jl), C is -1 (j"), and D is -j (
Multiply by j3). For higher radix operations, this multiplication is even more complex (e.g., for radix 8, the phase of each of the 8 channels is 45°
(need to be shifted). A DFT operation is performed by Fourier transform operator 120 to obtain and Fourier transform a set of four data words from each channel. The rotating element 130 is provided with a memory for storing predetermined coefficients and a multiplier for multiplying these data words by these coefficients. RAM unit 140 performs RAM shuffling (SR) and acts as a data interface between stages.

For N greater than 64, repeat stage 2, but
The exception is that the second stage and the next stage are provided with a post-FFT before each pre-FFT phase rotator 110. As previously mentioned, a post-FFT phase rotator provides a second set of data to be appropriately received from the RAM. For N=64, this function was absorbed into the reorganized rotating element D1%lD□.

The previously described reduced contractile geometry method is embodied in FIG. 4, where the identification numbers correspond to those in FIG. Phase rotator 150 is a merge operator that includes a rotation coefficient merged with a phase shift multiplier.

The stage-to-stage symmetry of the device of FIG. 4 allows the third stage phase rotator 110 to be merged with a single rotation operator while addressing the first stage phase rotator 110 operator with a RAM element. is further emphasized by These changes create a device in which each stage has a RAM element, a Fourier transform operator, and an adjusted rotation factor of a programmable ROM (PItOM).

FIG. 5 illustrates an FFT processor unit that is used as a stage in a multi-stage FFT device and includes these three elements. Three FFT processor units are required for N=64 and R=4.

The FFT processor unit 200 shown in FIG. 5 can be configured with seven elements, including the I10RAM element 220. RAM address element 2401 rotation memory element 2602 rotation address element 28
0. FFT calculation element 3002 built-in test (BI
TE) element 320 and control element 1.

I10 RAM element 220 is the data interface between sequential stages. This element 220 receives human power data 225 (ie, for stage 1, from system input via an element such as a shuffle operator, not shown). These data are 2
It has two 16-bit components to form a complex data word with phase. Ilo)IAM
Element 220 can be separated into four identical boats that interface directly with the four boats of computational element 300. Each boat can be comprised of a recursive data buffer and a double buffer RAM module.

Each of these four RAM modules can be configured into multiple RAMs with multiplexed inputs and outputs.
M (for example, two 2kX for N :4096
1S RAM). As a result, new input data can be written into the RAM at the same time as the data is read from the RAM.

In such a method, 100% of the FFT processor unit can be utilized. A write address command is received on bus 227 by RAM element 220 and a write address command is received on bus 229 from RAM address element 240.
Receive read read address command within. FFT the output data in bus 235? 'iL calculation element 300.

This RAM address element 240 can be multiple PR
OM (e.g. 4 2X for N=4096
s PROM) into read/write addresses and complex/real addresses.

The complex address portion uses read or write addresses to store complex data values.

The real address adds the LSB to the complex address, and the address controls access to the in-phase and quadrature components of each complex data value. For example, the LSB of O
The values are in-phase, ie, correspond to the real component, and the LSB values of l are made orthogonal, ie, correspond to the imaginary component. by this,
FFT data can be referred to as complex data based on the inherent recognition that the real or imaginary component is determined by the LSB value using a complex number address.

All RAM write addresses are sequentially driven by counts corresponding to a particular complex Fourier transform operation for each FFT stage. Sequential complex points are first,
Write sequentially with the real component and then the imaginary component, so by the real counter I10RA
M element 220 can be addressed. Such sequential counting is performed simultaneously for each of the four boats and then remains on a single bus 227.

Read re-addressing operations involve considerably more than write-addressing operations due to the RAM shuffling (S,) of the input data to the FFT arithmetic element 300.

Since data is written to the RAM in its appropriate channel in sequence, it is necessary to select the required data word for each Fourier transform operation by read address. This read address operation is performed by FR
It is executed by instructions in OM memory, which is addressed by a sequential counter that tracks the most recent complex Fourier transform operation. Each of the four RAMs in RAM element 220 requires independent addressing in parallel within bus 229.

Rotating memory element 260 can be configured with multiple PROMs (for example, N=4096, 8
(2 kX 8FROM), these PROMs include:
Contains rotational element coefficients supplied to the FFT calculation element 300. It sends data to bus 265 via four parallel 16-bit ports.

As will be explained below, an actual stored rotational element is required for one stage of the transformation for predetermined N and R. From this stored data, a rotational addressing scheme within rotational address element 280 ensures that the correct coefficients are selected for a Fourier transform operation per particular stage and transform size.

The rotary address element 280 is a multiple PROM (
For example, 3 2 k X 8 for N=4096
FROM), which are controlled by counters that track complex Fourier transform operation numbers, such as in RAM address element 240. This element utilizes a masking scheme in which the address is incremented by an appropriate value to compensate for different throughputs and transform sizes.

Instructions are sent to rotating memory element 260 via line 275.

Control element 340 generates on-board control signals for other elements and provides clock-in signal 355 to control all I/Os.
Synchronize the 10 data words and coefficients.

By pulling up output data 305 by BITE element 320 as a source for test data using line 315, for example, by pulling up one port of output data 305.
20 to 16-1 data multiplexer and external control 325 is available to select one of the 16 bits for external monitoring via line 335.

Further, the FFT calculation element (FFTCE) 300 will be explained with reference to FIG. First, in this figure, the same identification numbers as those in FIG. 5 were used.

This FFTCE300 can be a unique single-chip design, and this functionality can be achieved by e.g.

This can be achieved by cascading existing chips such as the IBM SPE chip. This FFTCH functionality computes FFT matrix operations and provides array scaling and rounding. Receives input data via bus 235 and further receives rotation coefficients from bus 265 and control functions via line 345 as well as line 355.
Receives the clock in signal of Output data to bus 3
05 (the number adjacent to each port or bus in FIG. 5 represents the number of lines per port or bus).

Using this FFTCE300, radix 4 4-port DFT
is calculated by solving the following equation: T(to)=C
H(k)+D(k+1)+D(k+2)+D(k+3)
] x c(k)T (k+ 1)=[D(k)−
jD (k+1)-D (k+2)+jD (k+3)
] X C(k+ 1)T(k+2)=[D(k)−
D(k+1) 〇(k+2)−〇(k+3)] xc(
k+2)T (k+3)=CH(k)+jD (k+
1)-D (k+ 2)-jD (k+3)]
For C(k+3)k=o, 4.8..., N-4, here, T(i): Output vector D(i): Data input vector C(i): Rotation coefficient or phase rotation vector j square root of 1. However, since this is radix 4, a phase rotation operation is included in these equations by adding the C(i) vector. For higher order radix operations, the phase rotation operation requires a separate complex multiplication operation (not shown). Alternatively, the phase rotator can be merged with the rotating memory element coefficients and the complex multiplication step can be omitted.

Data may be received as data words via bus 235. These data can also be made into complex numbers consisting of in-phase components and orthogonal components.

Each component is 16 bits, fixed point, and two's complement. Four data words are received simultaneously and the vector D (
i) is formed in the equation described above. At the same time, four rotation coefficients are received from bus 265 synchronously with four data words to form vector C(i).

With N=64 in this example, the FFTCE receives 16 vectors D (i) and C(i) on each pass through the stage and outputs 16 vectors T (i). Each of these vectors consists of four data words. The output is routed to the next stage via bus 305.

Also, in FIG. 6, the FFTCE 300 outputs a control word 1' scale factor output" 347, which is equal to the number of right shifts required to avoid overflowing during subsequent processing. .This output is used as ``scale factor input'' in the next stage.
349.

An example of this FFTCE architecture is shown in FIG. The same reference numbers as in FIG. 5 are used here. The data words of vector D (i) are input onto bus 235 and scaled appropriately. Arithmetic logic unit (ALU) 312. Delay 314. 'j' multiplier 316 and a complex multiplier 318 utilizing the C(i) vector from bus 265 provides the vector T (i) output from bus 305.

N=64. The values for the vector C(i) stored in the rotating memory element (260 in FIG. 4) of the R=4 contractile geometry FFT processor unit are shown in FIG. The counts for the Fourier transform operation are illustrated in column A. The four values of vector C(i) at each stage are column B-
Shown in D. Each value is the term exp(j2 tc m/
N) represents "m", and N=64.

It can be seen that the stage 2 rotation coefficient values are a subset of the stage 1 rotation coefficient values. For larger N, this relationship is developed later. If the powers of the five-phase rotator are combined with the rotating elements, repeatability is destroyed. Stage 3 as shown is the result of merging the power of the j multiplier with the unit rotation element of stage 3. If the powers of the j multiplier do not merge with the rotating elements of stage 3, then all rotating element values of stage 3 will be zero.

ROM requirements can be further reduced by combining rotation factors as shown in FIG. A hardwired addressing scheme in the rotation coefficient element (280 in FIG. 4) selects the appropriate C(i) value using the number of Fourier transform operations and the number of stages. At the last stage.

Only values marked with a circle are accessed. For higher N, the pattern is similar, except that the fluctuations of the circled groups are repeated.

For example, if N=256, each column has (0, 64, 128,
192) are included.

Software simulation of the method described above shows that it can be used with pipelined FFTs of radix 2.4.8 or higher. As the radix increases, the throughput rate also increases. This forces the FFT arithmetic processor (at each stage) to have a sufficient amount of parallelism within its own internal architecture such that high throughput occurs.
If it can be composed of , it will increase due to a considerable degree of parallelism. Depending on the desired processing speed, a high-order radix architectural chair may require a pipeline processor within the FFT calculation element (eg, 8-point FFT, etc.).

The method described above was of the type that takes 1/10 of the frequency (DIF), but it takes 1/10 of the time (DIT).
) type version can be generated from the DIF method, in this case by performing a matrix arrangement F G 4 of the DFT matrix when the OFT matrix is symmetric. This F 64 can be made symmetric by multiplication by a shuffle matrix S4/1g, which transforms the rows of F@4 back to their natural order (increasing frequency). This DIT version is given below (after multiplying the DIF version by SJ, , and converting the result), F, , T=S/*Dp F4DP
ts TF4DρzS TF4Up Sts8 Here, To S□6=SJ Engineering, T Sζ is the arrangement matrix of Sbi, and Fs4T is the DIT DFT matrix.

This matrix F4 is a block square matrix containing a 4-point kernel T along the diagonal and assumes that each DFT is in natural order, thus being a symmetric 4X4 matrix.

is symmetrical and does not change depending on the placement matrix. II p including phase rotation and rotating elements
All of the I+ matrices are already square, which gives them symmetry. Shuffle matrix S4/
IG and SFL vary with placement matrix operations. However, the rotating element matrix is currently the predecessor to the F4 matrix, which is a feature and method of the processor that takes 1/10th of the time.

According to a variant, the function of the phase shift operator can also be implemented with a circular commutator switch. Introducing cross-channel communication is done outside the FFr computational element. Such an embodiment is advantageous for slow, low-order radix operations.

The technique described above can also be applied to a recursive FFT processor. Recursive processor applications, where the same hardware can be used repeatedly, are suitable if low processing speeds are acceptable.

Although various embodiments of the invention have been described in detail, modifications and changes will readily occur to those skilled in the art.

Accordingly, the embodiments described above are illustrative only and are not intended to limit the spirit of the invention, which is to be defined by the accompanying claims and their equivalents.

[Brief explanation of the drawing]

FIG. 1 is an illustration of the data words in a conventional FFT processor; FIG. 2 is an illustration of the phase-shifted order of data words in the FFT processor of the present invention; FIG. A three-stage FFT encompassing a phase shift scheme of
A block diagram of a processor; FIG. 4 is a block diagram of a reduced contractile geometry version of the device of FIG. 3; FIG. 5 is a block diagram of a single stage of the processor of FIG. 4; A block diagram of the FFT calculation element shown in FIG. 5; FIG. 7 shows the calculation architecture of the element shown in FIG. 6; FIG. The figure shows the RO version with a small rotation coefficient shown in FIG. 5... Phase shift unit 10... Fourier transform operator 20... Address unit 100... Shuffle unit 110... Phase rotator 200... FFT processor unit 280...
Rotation address element 347...Scale factor output 349...Scale factor input

Claims (1)

[Scope of Claims] 1. In performing a fast Fourier transform operation on complex data words, the data words are received, arranged in R channels, and R channels corresponding to the R channels are arranged. an input memory means having an output; a plurality of series connected stages for converting the data words, wherein a first of these stages converts the data words in R channels into the input memory means; output memory means connected at the end of the series connected stages for outputting said data words, each of said stages having said R channels for connecting said stages; R input means and output means corresponding to R of the data words; and R shuffling means for temporally aligning R of said data words into vectors, each of said vectors wherein said R of said data words from each of said channels; a Fourier transform operator for Fourier transforming each of these vectors; R vectors for shifting the phase of these data words before they are input to said Fourier transform operator; first multiplier means and R for shifting the phase of the data words after outputting them to the Fourier transform operator;
R second multiplier means, where said second multiplier means is not the first stage of said series arranged stages, and R third multiplier means for providing a predetermined coefficient to each of said data words. multiplier means for not transmitting said input memory and output memory data words of one of said channels to the other of said channels except within said Fourier transform operator. Fourier transform calculation device. 2 one of the R third multiplier means
2. An arithmetic device according to claim 1, wherein said first multiplier means is integrated into one of said first multiplier means. 3. The arithmetic device according to claim 1, wherein one of the third multiplier means is merged with one of the second multiplier means. 4. The Fourier transform operator is provided with a block square matrix, and R point Fourier transforms are provided along the diagonal of the block.
Arithmetic device as described in section. 5. The arithmetic device according to claim 1, wherein the first multiplier means includes multiplier means for shifting the phase of the data word by an integral multiple of 360/R degrees. 6. Each of said third multiplier means includes: one or more programmable ROM means containing said predetermined coefficients; and tracking means for counting the number of operations performed by said Fourier transform operator. , and an address element for selecting the coefficient from the programmable ROM means using the tracking means. 7 receiving means for receiving the input stream of N digital data words in R channels for Fourier transformation into an input stream of N digital data words, each having a phase; Log_RN serially connected stages for said data loads; processing means for processing within the vectors, each of these stages comprising: shuffling means having an N×N matrix for temporally aligning said data words R in vectors; one of said data words from each of said R channels subtracted at intervals of N/R from said stream of digital data words; shifting means for shifting the phase of the R data words in each of said channels by an integer multiple of 360/R degrees, further Fourier transforming each of said vectors and having a plurality of matrix operators of radix R; A Fourier transform device comprising: a Fourier transform means. 8. In performing a fast Fourier transform on a digital data word having a phase, a plurality of serially connected Fourier transform means having a plurality of channels and performing a Fourier transform on a group of these data words; a plurality of phase shifting means for transforming said data words by means of each of said phase shifting means, placing said data words in a suitable order for the next stage of said Fourier transformation means;
A processor characterized in that the data words are not transmitted between the channels. 9. The device comprises a plurality of data channels and a plurality of shuffle operators for rearranging digital data, and each of these shuffle operators rearranges data from only one of the data channels. A high-speed Fourier transform calculation device for digital data. 10 for fast Fourier transforming digital data words, each having a phase; a plurality of data channels; a plurality of serially connected Fourier transform means for computing the Fourier transform of groups of these data words; a plurality of phase shifting means provided with one of the data words from each of said channels and for modifying the phase of one data word in said channel prior to said Fourier means; further prior to said Fourier transforming means; 1 of the said channels
a plurality of shuffling means for arranging data words in one of the channels so that said data words in one of said channels are not transmitted to another channel. 11. The transform device according to claim 10, wherein the Fourier transform means is provided with a block square matrix, and the Fourier transform is provided along the diagonal of the block. 12 R said data channels are provided, and each said phase shift means is configured to adjust the phase of said data word by 360/
12. The conversion device according to claim 11, further comprising multiplier means for shifting by an integral multiple of the R degree. 13 comprising a plurality of data channels and means for computing a Fourier transform of a plurality of groups of digital data, each of said groups being provided with one of said data words from each of said channels, said data words being transferred to said channels; A fast Fourier transform device characterized in that no data is transmitted between the two. 14. A digital device comprising a processor having a plurality of stages and a plurality of channels for digital data, the path for the digital data in each of these channels being fixed and without a switch. Fourier transform device for data. 15. comprising a plurality of channels and a plurality of connected stages for computing the Fourier transform of complex data words, further comprising phase shifting means for transforming the data words;
Data words, characterized in that the arrangement of the data words in one of the stages results in a predetermined order of the words for the next stage, such that no data is transmitted between these channels. Transformation device. 16 providing four said channels, and providing said phase shifting means with multiplier means for multiplying the data word in each of said channels by a power of j, such that the powers of j for each of these channels are consecutive; 16. The transforming device according to claim 15, wherein the integer powers of start from zero. 17. Providing R channels, the shifting means further comprising multiplier means for shifting the phase of the data word present in each of the R channels by a multiple of 360/R degrees; 16. The apparatus of claim 15, wherein the multiples of 360/R are consecutive integers starting with zero. 18 Perform a fast Fourier transform operation on the complex data word,
a plurality of serially connected stages for converting these data words; each of these stages has R input and output means connecting the stages and corresponding to the R channels; R shuffling means for aligning R in time within the vectors, each of these vectors being provided with one of the data words from each of these channels, and Fourier means for performing a Fourier transform on one of these vectors. a transform operator; R first multiplier means for shifting the phase of said data words before they are input to said Fourier transform operator; applying a predetermined coefficient to each of said data words; R second multiplier means for providing one of said channels between said input means and output means;
A fast Fourier transform computing device characterized in that data words in one channel are not transmitted to other channels. 19. Apparatus according to claim 18, characterized in that one of said R second multiplier means is merged with one of said R first multiplier means. 20. The apparatus of claim 18, wherein the Fourier transform operator is provided with a block square matrix having R-point Fourier transforms along the diagonal of the block. 21. each of said second multiplier means includes one or more programmable ROM means containing predetermined coefficients; and tracking means for counting the number of operations performed by said Fourier transform operator; 19. The apparatus of claim 18, further comprising an address element for selecting said coefficients from said programmable ROM means using said tracking means. 22 has R channels and Log_RN serially connected stages, and in performing a Fourier transform operation on an input stream of N digital data words, each of these stages has R channels of these digital words in a vector. an N×N matrix aligned in time, where each of said vectors is provided with one data word from each of said R channels subtracted from said data word stream at intervals of N/R. A Fourier transform device comprising: phase shifting means for transforming the data word without transmitting the data word between the channels; and Fourier transform means for Fourier transforming each of the vectors. 23. The Fourier transform device according to claim 22, wherein the Fourier transform means is provided with a block square matrix, and R-point Fourier transform is provided on this block square matrix along the diagonal of the block. 24 Having a plurality of Fourier transform means arranged in series, in performing Fourier transform of a digital data word, a plurality of phase shift means for transforming the data word are provided before the Fourier transform means, and these Fast Fourier transform processor, characterized in that each of the phase shifting means places said data words in an appropriate sequence for the next stage of said Fourier transform means. 25. in computing a fast Fourier transform of a digital data word in a plurality of data channels, computing a Fourier transform of said group of digital data words;
a plurality of series-arranged Fourier transform means, each group being provided with one of said data words from each of said channels, further comprising: a plurality of serially arranged Fourier transform means; A fast Fourier transform device, characterized in that it comprises a plurality of phase shift means for transforming the digital data word, the path followed by the digital data word being fixed and without switches. 26 Fast Fourier transforming an input stream of N digital data words, each with phase: (a) partitioning these data words into R channels; (b) steps (c) to (f) (c) aligning R of these data words in time into N/R vectors, where the data words in each of these vectors are applied to the input at N/R intervals; (d) shifting the phase of the data word, wherein the phase of the data word in each channel is , for each channel by a multiple of 360/R degrees; (e) computing the Fourier transform of each of said vectors; and (f) multiplying by a predetermined coefficient. A fast Fourier transform method characterized by: 27 In performing a fast Fourier transform operation on an input stream of N digital data words in a plurality of serially arranged stages, each of these stages: (a) transforms R of said data words into N/R vectors; (b) shifting the phase of the data words, wherein the phase of the data words in these channels is adjusted to A fast Fourier transform method, comprising: shifting each of the channels by a multiple of 360/R degrees; and further comprising: (c) calculating a Fourier transform of each of the vectors.