JPH05199555A - Time division switch - Google Patents

Abstract

PURPOSE:To provide a bit switching time division switch which can reduce the capacity of a control memory without increasing the operating speeds of a call channel, the control memory, etc. CONSTITUTION:When the input parallel data 2 are converted into the serial data 10, the bit identification information 5 given from a control memory 5 is stored in a call channel memory 1a as long as the information 5 is identical with a specific pattern. At the same time, the bit corresponding to a shown bit position is selected out of the data 2. Meanwhile the parallel data 8 read out of the memory 1a are converted into the data 10 with a pattern except the specific one and then outputted. When the serial data 11 are converted into the parallel data 14, a selector 12 puts the data 11 into the corresponding bit position based on the information 5 given from the memory 3 and converts the data 11 and the converted data 14 read based on an address information 4 given from a memory 3 into the parallel data 13. The data 13 are stored in a call channel memory 1b based on the information 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a time division switch for exchanging bit units used in a time division multiplexer or the like.

[0002]

2. Description of the Related Art FIG. 5, for example, is published by The Telecommunications Association of Japan, edited by Shinichi Aizawa, "Easy Digital Exchange" (Showa era).
It is the conventional time-division switch shown on January 42, 1983, p42-p45). In the figure, 41 is a speech path memory, 42 is a selector, 43 is a control memory, and 44 is an address counter. Sequential light random read
According to the read method, the reading control and the writing control of the communication path memory 41 are performed, and the time slots are exchanged.

FIG. 6 is a diagram for explaining the operation thereof, showing a case where the input and output highways are multiplexed in 8 bits and 32 bits.
Is a frame, TS is a time slot, R is a lead period,
W indicates a write period. The address counter 44 sets the addresses of addresses 0 to 31 of the speech path memory 41 to 1 frame F.
It is configured to output within the period. In this case, the communication path memory 41 has a structure of 8 bits.times.32 words, and the control memory 43 has a structure of at least 5 bits.times.32 words. Input highway 8 bits 0
Information of 00 to 007 is regarded as one word
In addition, in the first half read period R of the time slot TS, the address read from the control memory 43 is selected by the selector 42 and the 8-bit information read from the speech path memory 41 is output highway. Sent to
In the latter half write period W, the output of the address counter 44 is selected by the selector 42 and added as a write address of the communication path memory 41, and 8-bit information 000 to 007 of the incoming highway is written to, for example, address 0. In the next time slot, the data is read from the control memory 43 during the read period R, and is read out of the input highway 8
Channel memory 4 as address of bits 010 to 017
It is written in, for example, address 1.

[0004]

When bit-by-bit exchange is realized by the conventional time division switch, the communication path memory 41 has a 1 × 256 word structure and the control memory 4
It is necessary to make the configuration of 3 to 8 × 256 words to increase the memory amount and to operate at 8 times speed. In addition, by limiting the exchange capacity in bit units, for example, 1/8
If the exchange capacity is set as the exchange capacity, it is not necessary to increase the speed, but the channel memory 41 and the control memory 43 also need to have the 1 × 256 word and 8 × 256 word configurations as in the above. There was a problem such as the increase.

The present invention has been made to solve the above-mentioned problems, and it is possible to increase the operating speed without increasing the operating speed.
The purpose of the present invention is to obtain a time-division switch for exchanging bits, which can suppress the increase in the amount of memory to a small extent and can also reduce the circuit scale.

[0006]

SUMMARY OF THE INVENTION A time division switch according to the present invention comprises a first speech path memory for storing input parallel data, and read from this input parallel data and the first speech path memory. The first conversion means for converting the converted parallel data into serial data and outputting the converted parallel data, the second conversion means for converting the input serial data and the converted parallel data into new parallel data, and the converted new data. A second channel memory that stores parallel data and outputs it as output parallel data,
A control memory is provided which stores address information for reading and writing the first speech path memory and the second speech path memory and bit identification information for controlling the first converting means and the second converting means. Further, when the bit identification information is a specific pattern, a unit for selecting a bit corresponding to the bit position indicated by the bit identification information of the input parallel data and outputting it as output serial data is provided. Further, when the bit identification information is a specific pattern, there is provided means for writing in the first speech path memory based on the address information from the control memory. Also,
Based on the address information from the control memory, the parallel data read from the second speech path memory in the first half cycle of the clock cycle T is input to the second conversion means, and in the latter half cycle of the clock T, the bit identification information There is provided means for inserting the input serial data at the indicated bit position and writing the parallel data from the second converting means to the address indicated by the address information in the second speech path memory.

[0007]

In the present invention, the input parallel data is serial data.
In the case of converting to parallel data and outputting it, the input parallel data is written into and read from the first communication path memory based on the address information and bit identification information from the control memory and is input by the first conversion unit. The parallel data and the parallel data read from the first channel memory are converted into serial data and output. When converting the input serial data to parallel data, input serial data to the bit position indicated by the bit identification information of the converted parallel data read from the second communication path memory based on the address information from the control memory. It is inserted, converted into new parallel data, and stored in the second call memory based on the address information. When the bit identification information has a specific pattern, the input parallel data is stored in the first channel memory, and the bit of the input parallel data corresponding to the bit position indicated by the bit identification information is selected and output as serial data. .. The second conversion means inserts the input serial data at the bit position indicated by the bit identification information of the converted parallel data read from the second speech path memory based on the address information in the first half cycle of the clock. The parallel data is converted into new parallel data, and the converted parallel data is stored at the address indicated by the address information in the second speech path memory in the latter half cycle of the clock.

[0008]

EXAMPLES Example 1. An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numerals 1a and 1b are a first call path memory and a second call memory, 2 is input parallel data, 3 is a control memory, 4 is address information output from the control memory 3, and 5 is a control. Bit identification information output from the memory 3, 6 is a negative logic AND gate, 7 is flag information output from the negative logic AND gate 6 when the bit identification information 5 is a specific bit pattern, and 8 is a channel memory 1a is parallel data, 9 is a selector which is a first converting means, 10 is serial data which is output from the selector 9, 1
Reference numeral 1 is input serial data, 12 is a selector that is the second conversion means, 13 is parallel data output from the selector 12, and 14 is parallel data that is read from the channel memory 1b and output. It is.

FIG. 2 shows the configuration of the control memory 3. In the case of this embodiment, the input parallel data 2 is 8 bits × 32 octets, the output serial data 10 is 32 bits of serial data, and the input serial data 11 is similarly 32 bits of serial data. When the output parallel data 14 has a frame structure of 8 bits × 32 octets, the address information 4 in FIG. 2 has 5 bits and the bit identification information 5 has 3 bits. Further, the specific pattern having the bit identification information 5 is set to "000", that is, a pattern of zero.

In FIG. 3, the input parallel data 2 is connected to the output serial data.
4 shows the timing of conversion into the data 10, and FIG. 4 shows the timing of conversion of the input serial data 11 into the output parallel data 14.

The conversion operation of the input parallel data 2 into the serial data 10 will be described with reference to FIGS. 1 and 3. The parallel data 2 is connected to the channel memory 1a with 8 bits × 32 octets. At this time, whether or not to actually write in the speech path memory 1a is limited to when the bit identification information 5 output from the control memory 3 is "0" which is a specific pattern.
As shown in FIG. 3, first, at the time of T1, the parallel data 2 is D.
A0 to DA7 are input, and address information 4-bit identification information 5 is output from the control memory 3. At this time, since the bit identification information 5 indicates "0", a negative logic AND
Since the output of the gate 6 becomes "L" and the write enable input of the speech path memory 1a becomes significant, DA0 to DA7 are assigned to the addresses of the speech path memory 1a indicated by the above address information 4.
Parallel data 2 is written. On the other hand, the parallel data 2
It is also connected to the selector 9, and the bit identification information 5 is "
When "0" is indicated, the selector 9 selects D of the parallel data 2.
DA0 of bit 0 of A0 to DA7 is selected and output. This is to reduce the delay time from the writing of data to the reading of data in the communication path memory 1a.

Next, at T2, the bit identification information 5 is "
No data is written to the speech path memory 1a to indicate "1". The address information 4 indicates the same address as at T1, and the parallel data 8 of DA0 to DA7 written at T1 is read out by the selector. 9 is connected to the selector 9. The selector 9 uses DA because the bit identification information 5 indicates "1".
1 is selected and output. Similarly, at T5, DA2 changes to T
DA3 is output at 6:00, and DA7 is output at Ti. At the time of T3, the bit identification information 5 indicates "0", so that DB0 to DB7 of the parallel data 2 are written in the address 1 of the speech path memory 1b.
DB0 is output as serial data 10 from the selector 9, and at time T4, DB1 indicated by the bit identification information 5 is output from the selector 9 among the parallel data 8 of DB0 to DB7 from the channel memory 1b. By performing the above operation, DA0 to DA of the parallel data 2 which is time-divided in units of octets.
7, each bit of DB0 to DB7 can be exchanged with the serial data 10 on a bit-by-bit basis under the instruction of the control memory 3.

Next, the operation of exchanging the input serial data 11 for the parallel data 14 will be described with reference to FIGS. The serial data 11 is a 32-bit serial data, and the selector 12
Connect to. As shown in FIG. 4, at T1, the serial data is
DA0 of the data 11 is input to the selector 12. At this time, from the channel memory 1b, T / 2 in the first half of the clock cycle T
DA0-1 to DA7-1 which have already been written are read out and output from the address 0 indicated by the address information 4 within the time and are added as the input of the selector 12. In the selector 12, the parallel data 14 and the serial data 11 described above are provided.
In response, the bits of the parallel data 14 indicated by the bit identification information 5 from the control memory 3 are replaced with the serial data 11. In this example, since the bit identification information 5 indicates "0", the first bit DA0-1 of DA0-1, DA1-1, DA7-1 of the parallel data 14 is the serial data 11 DA0
In the latter half of the clock cycle T, that is, DA0, DA1-1, DA7-1 at address 0 of address information 4 within T / 2 hours.
The parallel data 13 of will be written. Next T
At 2 o'clock, DA1 is input to the selector 12 in the serial data 11. Similarly to the above, the address 0 is set in the first half cycle of the cycle T of the clock.
Parallel data 14 of DA0, DA1-1, DA7-1 from the address
Is read out, and in the selector 12, only the bit indicated by the bit identification information 5 is replaced with DA1 of the serial data 12. In this case, DA1-1 is replaced with DA1, and D
It becomes parallel data 13 of A0, DA1, DA7-1 and is written and updated at address 0 of the speech path memory 1b.
Similarly, at T5, DA0, DA1, DA2, DA7
-1, at T6, DA0, DA1, DA2, DA3,
DA7-1, and DA0, DA1, DA at time Ti
2, DA7 and all bits are updated, speech path memory 1
As a result, the data is written in the address 0 of b, and as a result, the conversion of the bit data from the serial data 11 into the octet data is realized at the time Ti. Further, at the time of T2, the DB0 of the serial data 11 also realizes the conversion into octets by the same sequence.

Example 2. Although the speech path memory 1a and the speech path memory 1b are configured with a single buffer having a one-sided memory configuration, they may be configured with a double buffer having a two-sided memory configuration. In this embodiment, 8 bits x
Although the 32 octet configuration has been described, the number of bits or the number of octets may be any configuration regardless of the above numerical values.

[0015]

As described above, without increasing the operating speed of the speech path memory, the control memory and the peripheral circuits, the increase in the capacity of the control memory can be kept low, and the reading and writing of the speech path memory can be further suppressed. There is an effect that can be converted from parallel data to serial data and from serial data to parallel data only with the control memory. Further, the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a time divisional switch according to an embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a control memory according to the embodiment of the present invention.

FIG. 3 is a timing chart showing a conversion operation from input parallel data to serial data according to the embodiment of the present invention.

FIG. 4 is a timing chart showing a conversion operation from input serial data to parallel data according to the embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a conventional time divisional switch.

FIG. 6 is a timing chart showing the operation of a conventional time divisional switch.

[Explanation of symbols]

 1a 1st channel memory 1b 2nd channel memory 2 input parallel data 3 control memory 4 address information 5 bit identification information 8 output parallel data 9 selector 10 which is the first conversion means output serial data Data 11 input serial data 12 selector which is the second conversion means

[Procedure amendment]

[Submission date] March 13, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0006

[Correction method] Change

[Correction content]

[0006]

A time-division switch according to the present invention includes a first speech path memory for storing input parallel data, and read from the input parallel data and the first speech path memory. First conversion means for converting the parallel data to serial data and outputting the converted parallel data, second conversion means for converting the input serial data and the converted parallel data to new parallel data, and the converted new parallel data. A second channel memo that stores data and outputs it as output parallel data,
The memory comprises a first channel memory, a control memory that stores address information for reading and writing the second channel memory, and bit identification information for controlling the first conversion unit and the second conversion unit. Further, when the bit identification information is a specific pattern, a unit for selecting a bit corresponding to the bit position indicated by the bit identification information of the input parallel data and outputting it as output serial data is provided. Further, when the bit identification information is a specific pattern, there is provided means for writing the input parallel data in the first communication path memory based on the address information from the control memory. Also, based on the address information from the control memory, the parallel data read from the second speech path memory for the first half cycle of the clock cycle T is input to the second conversion means and identified as Mitsu in the second half cycle of the clock T. There is provided means for inserting and reporting the input serial data at the bit position indicated by the information, and writing it as parallel data from the second conversion means to the address indicated by the address information of the second communication path memory.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0011

[Correction method] Change

[Correction content]

First, the operation of converting the input parallel data 2 into the serial data 10 will be described with reference to FIGS. 1 and 3. The parallel data 2 is connected to the channel memory 1a with 8 bits × 32 octets. At this time, whether or not to actually write in the communication path memory 1a is limited to when the bit identification information 5 output from the control memory 3 is "0" which is a specific pattern. As shown in FIG. 3, DA is first set as parallel data 2 at T1.
0 to DA7 are input, and the control memory 3 outputs address information 4 and bit identification information 5. At this time, since the bit identification information 5 indicates “0”, the negative theory AND
Since the output of the gate 6 becomes "L" and the write enable input of the communication path memory 1a becomes significant, DA0 to DA7 are assigned to the addresses of the communication path memory 1a indicated by the address information 4 above.
Parallel data 2 is written. On the other hand, parallel data 2 is
It is also connected to the selector 9, and when the bit identification information 5 indicates "0", the selector 9 selects DA0 of bit 0 of DA0 to DA7 of the parallel data 2 and outputs it. This is to reduce the delay time from the writing of data to the reading of data in the communication path memory 1a.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction content]

[0015]

As described above, parallel data to serial data and serial data can be read and written to and from the control memory without speeding up the operation speed of the communication path memory, the control memory and the peripheral circuits. To parallel data
In addition, there is an effect that the bit unit can be exchanged .
Further, the circuit scale can be reduced.

[Procedure correction 4]

[Document name to be corrected] Drawing

[Name of item to be corrected] Figure 3

[Correction method] Change

[Correction content]

[Figure 3]

Claims (4)

[Claims] 1. A first channel memory for storing input parallel data, and a first channel for converting parallel data read from the input parallel data and channel memory into serial data. Conversion means, second conversion means for converting input serial data into parallel data, second communication path memory for storing the parallel data converted by the second conversion means, and the first and second conversion means. A time division switch comprising a second communication path memory and a control memory for storing address information and bit identification information for controlling the first and second conversion means. 2. When the bit identification information is a specific pattern, the bit corresponding to the bit position indicated by the bit identification information is selected from the input parallel data and output from the first conversion means as serial data. 2. The time divisional switch according to claim 1, further comprising means for outputting as. 3. When the bit identification information from the control memory is the specific pattern, there is provided means for writing the input parallel data to the first speech path memory based on the address information from the control memory. Claim 1 characterized by the above.
The time division switch described. 4. The converted parallel data read from the second speech path memory in the first half cycle of the clock cycle T based on the address information from the control memory is input to the second conversion means. In the latter half cycle of the clock T, the input serial data is inserted into the bit position of the output parallel data indicated by the bit identification information, and the second conversion means outputs new parallel data from the second speech path. The time divisional switch according to claim 1, further comprising means for writing to an address indicated by the address information of the memory.