JPH05199256A - Atm exchange - Google Patents

Abstract

PURPOSE:To provide a same function with a small capacity of memory by reducing the table capacity for a VPI/VCI conversion of the exchange. CONSTITUTION:The ATM exchange 1 divides bits of a VPI/VCI 4 in a transfer cell into plural blocks. The exchange is provided with a device selecting sequentially plural blocks, an address equivalent memory 7a, and a conversion VPI/VCI information memory 7b, and generates an address required to read the memory for next time by reading the memory 7a, reads the memory 7 and a block selection device 2 for plural number of times and obtains the conversion destination VPI/VCI by the read of the final memory 7b.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a switch in a broadband ISDN, and more particularly to an ATM switch for exchanging information in an asynchronous transfer mode (ATM).

[0002]

2. Description of the Related Art Asynchronous Transfer Mode (hereinafter referred to as AT
In M), all information is converted into fixed-length cells for transmission and exchange. For example, in data communication, when a variable-length message received from a terminal is transmitted to another terminal, the message is transferred by dividing it into a plurality of cells, and the receiving side receives all the cells constituting the message,
The original message is assembled and sent to the destination terminal. FIG. 6 is a diagram showing how cells are generally transferred to and from several exchanges between terminals. In the figure, T1 and T2 are terminals, E1 to E4 are ATM exchanges, and L
1 to L6 are transmission lines, and C1 is a cell. Of the information transmitted, H1 and H2 are called headers,
It is at the beginning of the cell. M1 is a VPI / VCI conversion table, which will be described later, inside the exchange E1.

The header of each cell of the transmitted information has VPI / VCI (Virtial Path Identifier /
It contains the logical channel information called "Virtial Channel Identifier"). This VPI / VCI
Is used to identify the logical channel in which the cell is transferred in the transmission path. The cell is transferred to the destination terminal via a plurality of transmission lines, but the logical channel to which the cell is transferred differs for each transmission line, and VPI / VCI also has a different value for each transmission line. Therefore, in the exchange, when the cell is transferred to another exchange or terminal, the VPI / VCI included when the cell is received is converted into the VPI / VCI corresponding to the destination to be transferred and is written in the header. That action is required. For example,
Looking at the cell C1 which is the information to be transmitted, the value of VPI / VCI was 3 in the transmission line L1, but the value was rewritten in the exchange E1 to be 7 in the transmission line L2.

In order for the exchange to perform the above-mentioned operation,
VPI / VCI at the time of receiving a cell, identification information of the transmission path transmitting the received cell, and VPI / V of the conversion destination
Correspondence table that correlates with CI is required.
It is called an I / VCI conversion table. As a method to realize this table, IEICE Technical Report Vol.88No
27 As described in “Prototype of ATM Switch for Wideband ISDN” by Kato and Hatsukano et al., The VPI / VCI value at the time of receiving a cell is read as a memory address from the memory, and the read content is related to the received content. There is a method in which the identification information of the transmission path for transmitting the cell and the VPI / VCI of the conversion destination are set. This memory is called a VPI / VCI conversion table M1.

In this system, for example, 20 in the header.
If a bit area is assigned to VPI / VCI, in order to convert it to the same 20-bit VPI / VCI, at least V20 of size 20 @ 20 bits is required.
The PI / VCI conversion table M1 is required. However, in practice, not all 220 VPI / VCI values are used, but if it is sufficient to convert 210 VPI / VCI values to another 210 VPI / VCI values, in practice, VPI / VCI conversion table M1 used
Has a size of 210 × 20 bits, and most of the VPI / VCI conversion table M1 is unused.

In order to eliminate the above-mentioned problem, a method of increasing unused memory efficiency by packing unused addresses can be considered. For example, VPI / VCI is "1-19", "30"
~ 38 "," 41-43 ", the unused addresses 20-29, 39, 40 ...
0 to 38 "at the addresses 20 to 28, and" 41 to 4 "
It is conceivable to store 3 "in addresses 29 to 31. However, in this method, for example, successive comparison is performed to refer to the VPI / VCI conversion table.
The upper half and the lower half will be sorted and compared, and the time for comparison will increase dramatically. Therefore, it is not an appropriate method for a switching device in which delay is a problem.

[0007]

The conventional ATM switch is constructed as described above, and such VPI / VC is used.
The configuration of the I conversion table M1 has a problem that an extremely large amount of memory is required as compared with the area used for implementation. The present invention has been made to solve such a problem, and an object of the present invention is to obtain an ATM switch having a small capacity memory and a conversion table search time not so long by using indirect addressing in multiple stages. I am trying.

[0008]

In the exchange according to the present invention, the address for referring to the conversion table is divided into a plurality of stages, and the reference time is increased, but each stage of the nail is registered in the next section. The number of memories used is reduced by repeatedly referring to only the existing address and referring to the conversion table at the end. Specifically, the register holding the VPI / VCI before conversion and the numerical value held in this register are divided into a plurality of stages, and the numerical values of the divided stages are fetched for each comparison, and the address memory described later is also used. The address generation register that fetches the registered address equivalent from the address generation register, if these values match, the next-stage numerical value is fetched, and the previously designated numerical value is fetched from the address memory equivalent, and the VPI / VCI conversion to the last matched numerical value. A table is provided so that the converted VPI / VCI value can be obtained.

[0009]

In the exchange according to the present invention, the VPI / VCI values in the transferred cells are divided and compared a plurality of times, and the numerical value of the conversion table of the address of the matching numerical value is designated as the converted value. ..

[0010]

EXAMPLES Example 1. FIG. 1 is an overall configuration diagram of an embodiment of a VPI / VCI conversion table in the device according to the present invention. As an example, a case where VPI / VCI is 16 bits will be described. In FIG. 1, 1 is a VPI before conversion
/ VCI value holding registers 1a to 1d are four blocks obtained by dividing the pre-conversion VPI / VCI holding register 1 into 4 bits. Reference numeral 2 is a block selection mechanism, 3 is an initial upper address register, 4 is a counter, and 5 is an upper address selection mechanism. 6 is an address generation register,
6a represents the upper address part and 6b represents the lower address part. 7 is a memory, which is an upper address information area 7a
And area 7b containing the converted VPI / VCI information
Consists of. Then, the converted VPI / VCI information area 7b
Respectively, the identification information 8a of the transmission path for transmitting the reception cell.
The required number of sets of VPI / VCI 8b of the conversion destination are accommodated.

The function of each unit will be described below. The counter 4 counts the number of readings to the memory 7. In this embodiment, a 4-bit block is extracted from the 16-bit VPI / VCI and is used as the lower address of the address for reading to the memory 7. Therefore, in order to extract all 16 bits, four reads are performed. Do it. That is, the reference count increases to 4. First, before conversion VPI /
The VCI holding register 1 stores the VPI / VCI before conversion. The block selection mechanism 2 has four blocks 1 a to 1 d in the register 1 according to the count number of the counter 4.
One of the blocks is selected and output to the lower address portion 6b in the address generation register 6. As an example, here, before the first read, the block 1a is
Block 1b before the second read, block 1c before the third read, and block 1d before the fourth read.
Shall be selected. The high-order address selection mechanism 5 selects either the initial high-order address register 3 or the value output from the memory 7 according to the count number of the counter 4, and outputs the selected value to the high-order address portion 6a in the address generation register 6. ..

Before the first read, the initial upper address register 3 is selected, and before the second to fourth read, the output of the memory 7 is selected. The initial high-order address register 3 specifies the value set in the high-order address portion 6a at the time of the first read. For example, here, it has the same number of bits as the high-order address portion 6a and the value of each bit. Are all 0. The address generation register 6 is composed of an upper address portion 6a and a lower address portion 6b, and stores the values output by the upper address selection mechanism 5 and the block selection mechanism 2. The value stored in the register 6 is used to specify the address of the memory 7. In the memory 7, the contents read in the first to third readings indicate the value of the upper address of its own address, and the contents read in the fourth reading are the identification information 8a of the transmission transmission path of the reception cell and the conversion destination. It is assumed that VPI / VCI 8b is set.

Next, the operation of the above embodiment will be described with reference to FIG. 1 using FIG. 2 as an example. Before conversion VPI / V
It is assumed that a bit pattern of VPI / VCI before conversion as shown in the figure is set in the CI holding register 1.
The numerical values written in the blocks 1a and 1b are expressed in decimal numbers in units of 4 bits. 0, 1, 5
The number column 9 of 2.103.201 is the upper address of the address in the memory 7, and the number column 10 of 0-15
Is the lower address. 8a is the identification information of the transmission path for transmitting the reception cell, 8b is the VPI / VCI of the conversion destination,
It is included in the range of the converted VPI / VCI information area 7b of the memory 7. In FIG. 2, VPI / VCI before conversion
It is shown that VPI / VCI to be converted can be obtained by sequentially reading 4-bit blocks from the 16-bit of the holding register 1 and reading the memory 7. In this embodiment, the memory 7 is read out four times in total.

In this embodiment, first, V before conversion is used.
The PI / VCI value is stored in the pre-conversion VPI / VCI holding register 1. Here, as an example, in decimal notation, 1 for block 1a, 7 for 1b, 10 for 1c,
It is assumed that 5 is stored in 1d. Immediately before the first reading of the four readings to the memory 7, the upper address selecting mechanism 5 selects the initial upper address register 3 and the block selecting mechanism 2 selects the block 1a. Therefore, the value stored in the address generation register 6 is such that the combination of (upper address 6a, lower address 6b) is (0, 1). Therefore, in the first read, the address (0, 1) is designated, and the value read from the memory 7 becomes 103, as can be seen from FIG. Next, before the second read, the upper address selection mechanism 5 selects the output of the memory 7 and the block selection mechanism 2 selects the block 1b, so the values stored in the address generation register 6 are (103, 7). Become. Therefore, in the second read, the address (103, 7) is designated, and the value read from the memory 7 is 52.

Before the third read, the upper address selection mechanism 5 selects the output of the memory 7, and the block selection mechanism 2 selects the block 1c. Therefore, the address generation register 6 is selected.
The value stored in is (52, 10). Therefore, in the third read, the address (52, 10) is designated, and the value read from the memory 7 becomes 201. Before the last fourth read, the high-order address selection mechanism 5
Selects the output of the memory 7 and the block selection mechanism 2 selects the block 1d, so the value stored in the address generation register 6 is (201, 5). Therefore, in the fourth read, the address (201, 5) is designated and the memory 7
The identification information 8a of the transmission path and the VPI / VCI.8b of the conversion destination are obtained by reading from.

Next, the operation when the value stored in the pre-conversion VPI / VCI holding register 1 is a VPI / VCI not registered in the conversion table will be described below with reference to FIG. In FIG. 3, for example, [1a, 1b, 1
It is assumed that the converted VPI / VCI for the VPI / VCI such as the combination [c, 1d] [1, 7, 9, X] is not registered (X is an arbitrary decimal value of 0 to 15).
At this time, the case where the value stored in the pre-conversion VPI / VCI holding register 1 is [1, 7, 9, 10] will be described. As in the case of FIG. 2, the output of the memory 7 is 103 in the first read, and the output is 5 in the second read.
It becomes 2. However, in the third reading, unlike the case of FIG. 2, a value (unregistered pattern) such as -1 that the apparatus cannot read into the memory is obtained. VPI at this point
The operation of the / VCI conversion ends. The memory 7 does not have a memory location having the information of the upper address of the address necessary for the fourth reading, and the memory location having the information of the converted VPI / VCI is not taken in the converted VPI / VCI information area 7b.

Embodiment 2. In the first embodiment, the upper address of the address used for the next read is read until the third read to the memory 7, and the converted VPI / VCI is read by the fourth read to the memory 7. Similarly, different pieces of upper address information and converted VPI / VCI information are stored in the same memory, but there is an embodiment in which these pieces of information are stored in different memories. FIG. 4 shows an embodiment of the present invention, in which upper address information is stored in the address memory 11, and transmission line identification information for transmitting cells and VPI / VCI information of the conversion destination VPI / VCI information. Are stored in the conversion VPI / VCI information memory 12 different from the address memory 11.
The difference in operation from the first embodiment will be described below with reference to FIG.

As in FIG. 2, it is assumed that VPI / VCI is 16 bits. Assuming that the pre-conversion VPI / VCI holding register 1 holds the same bit pattern as that of FIG. 2 showing the first embodiment, the address memory 11 is read three times, and the converted VPI / VCI information memory 12 is read. Will be needed once. Until the third read to the address memory 11, the same operation as the third read to the memory 7 in FIG. 2 is performed. But 4
The second read is the conversion VPI / VCI information memory 12
Be done from. An address is generated from the content obtained in the third reading and the bit pattern of block 1d,
Converted VPI / VCI memory 1 according to the obtained address
2 is read, and the contents to be read are converted VPs.
I / VCI information is set. In this embodiment, the number of bits required to represent the upper address information and the conversion V
This is effective in increasing the efficiency of memory usage when the number of bits required to represent PI / VCI information is different.

Example 3. VC depending on the specific VPI value
There is a case where the cell is transferred only by converting the VPI regardless of the I value. Therefore, if only the VPI value of the transferred cell is taken out and only the VPI needs to be converted, only the VPI is converted and the operation is terminated.
When the I value also needs to be converted, V of the receiving cell is further converted.
A method is conceivable in which the CI value is taken out and the operation is continued to obtain the converted VPI / VCI. In the third embodiment, as shown in FIG.
I conversion memory 16 and VPI / VCI conversion memory 18
2 types of memory are arranged. Memory for VPI conversion 16
May be considered to correspond to the address memory in the first embodiment. Both may be arranged in areas of different addresses on the same memory. The operation of the third embodiment will be described below with reference to FIG. Pre-conversion VPI / VCI holding register 1
In 3, the VPI / VCI bit pattern is divided into VPI bit 14 and VCI bit 15. Further V
Set the PI bit to VPI block of 1 to M (M ≧ 1) by V
The CI bit is divided into 1 to N (N ≧ 1) VCI blocks. In this case, part of the VCI conversion memory 18 also includes an address memory.

First, the first VP is processed in the same manner as in the first embodiment.
VP using I block to Mth VPI block
The I conversion memory is read. The information read out at the last M times is set with information 17a that indicates whether the operation is finished only by the VPI conversion or the VPI / VCI conversion is required. Instruction information 17
When a indicates that the operation ends only by the VPI conversion, the read content includes the identification information 17b of the transmission path for transmitting the cell and the conversion destination VPI · 17c, and the VPI is converted. The operation is ended by simply When the instruction information 17a indicates that VPI / VCI conversion is required, an address is generated from the read content and the first VCI block, and the VPI / VCI conversion memory 18 is read. Then, the second VC
From the I block to the Nth VCI block, VPI /
The VCI conversion memory 18 is read and the last Nth memory is read.
By the read using the VCI block, the identification information 19a of the transmission path for transmitting the reception cell and the VPI of the conversion destination
/ VCI · 19b is obtained.

As described above, in this device, only the information about the conversion VPI / VCI used is converted into the conversion VPI / VC.
Conversion VPI / VC used to register in I memory
The smaller I is, the more memory is saved.
For example, in the first embodiment, when the VPI / VCI is 16 bits, the VPI / VCI having 1000 different values.
In order to realize a table for converting each to 1000 VPI / VCI, the conventional method requires about 64K × 1.
Although a memory having a size of 6 bits is required, a detailed description is omitted in this device, but in the worst case, it is 20368.
A memory of size x16 bits is sufficient.

Example 4. In the above embodiment, an example in which the address memory corresponding to the address specified by the address fetched in the address generation register 6 is accessed is shown. However, the size of the address generation register is increased and the next comparison operation is performed. May be specified. That is, as in the first embodiment, consider an example in which VPI / VCI is 16 bits and is divided into 4 bits. The numerical value is [1,
7, 10, 5]. In FIG. 1, the address generation register 6 first reads 4 bits, that is, 16 addresses including the registered highest address of the memory 7. The block selection mechanism 2 takes in the highest numerical value 1a, looks at the address of the address generation register 6, which is 1, in this example, and checks whether it is registered.
If registered, then the address generation register 6
Reads out 16 addresses of the registered address memory 7 of [1] in this example. Some of these addresses are registered and some are not. Only the registered address is entered numerically, and the address generation register 6 is checked by the next 4 bits 1b read by the block selection mechanism 2. In this example, since it is registered at [7], the contents of the address memory 7 at this address are read.

Hereinafter, the block selection mechanism 2 is 1c [1
0] is read and compared with the contents of [7] of the address memory read by the address generation register 6. If registered, the contents of the next address memory [10] are read. It is checked by comparing with this and whether or not 1d [5] read by the block selection mechanism 2 is registered. If registered, the data in the VPI / VCI information area 7b after conversion of the memory
The data becomes the data corresponding to that before conversion.

The case where the VPI / VCI has 16 bits has been described above, but the present invention is not limited to this, and can be applied to the case where the VPI / VCI has an arbitrary fixed length bit number. Although the bit pattern is divided into four bits here, the bit pattern may be divided into any appropriate number of bits. Furthermore, the device according to the invention, although used here for VPI / VCI conversion, can be applied to the realization and invocation of any other conversion or correspondence table which makes the content of one data correspond to another.

[0025]

As described above, according to the present invention, the ATM
In the exchange, the input is divided into a plurality of stages and sequentially referenced, and a conversion table is provided for the last matching numerical value to obtain the corresponding converted VPI / VCI value. It has the effect that the bull can be realized with a small capacity memory.

[Brief description of drawings]

FIG. 1 is an overall configuration diagram of a VPI / PCI conversion table in an exchange of the present invention.

FIG. 2 is an operation explanatory diagram (Embodiment 1) of a VPI / PCI conversion table in the exchange of the present invention.

FIG. 3 is another operation explanatory diagram (Embodiment 1) of the VPI / PCI conversion table in the exchange of the present invention.

FIG. 4 is an operation explanatory diagram (second embodiment) of a VPI / PCI conversion table in the exchange of the present invention.

FIG. 5 is an operation explanatory diagram (third embodiment) of a VPI / PCI conversion table in the exchange of the present invention.

FIG. 6 VPI / V when cells are transferred to and from the switch
It is a figure which shows a mode that CI conversion is performed.

[Explanation of symbols]

1 Pre-conversion VPI / VCI holding register (Embodiment 1) 2 Block selection mechanism 3 Initial upper address register 4 Counter 5 Upper address selection mechanism 6 Address generation register 7 Memory 7a Upper address information area in memory 7b Conversion VPI / in memory 7 VCI information area 8a Transmission line identification information in memory 7 8b Conversion destination VPI / VCI 9 in memory 7 Upper address of memory 10 Lower address of memory 11 Address memory 12 Conversion VPI / VCI information memory 12a Transmission line in conversion VPI / VCI information memory Identification information 12b Conversion destination VPI / VCI in conversion VPI / VCI information memory 13 Pre-conversion VPI / VCI holding register (Example 3) 14 VPI bit 15 VCI bit 16 VPI conversion memory 16a Upper address information area 16b in VPI conversion memory Conversion VPI / VC in VPI conversion memory
I information area 17a Instruction information in VPI conversion memory 17b Transmission path identification information in VPI conversion memory 17c Destination VPI in VPI conversion memory 17d Upper address in VPI conversion memory 18 VPI / VCI conversion memory 18a VPI / VCI conversion Address information area 18b in the memory for conversion VPI / VCI conversion VP in the memory for conversion
I / VCI information area 19a Transmission path identification information in VPI / VCI conversion memory 19b Conversion destination V in VPI / VCI conversion memory
PI / VCI

Front page continuation (72) Inventor Kazuhiro Sato 1-1-6 Uchisaiwaicho, Chiyoda-ku, Tokyo Nihon Telegraph and Telephone Corporation (72) Inventor Eiichi Horiuchi 5-1-1 Ofuna, Kamakura-shi Mitsubishi Electric Corporation System Research Laboratory (72) Inventor Hiroyuki Sato 5-1-1 Ofuna, Kamakura City Mitsubishi Electric Corp. Communication Systems Research Laboratory (72) Inventor Toshihiro Kanama 5-1-1 Ofuna, Kamakura City Communication System Research In-house

Claims (3)

[Claims] 1. An ATM switch for receiving a cell including a header including a logical channel number, converting the logical channel number and transferring the cell, and a register for holding bits constituting a logical number of a received cell, and the above logic. Numbers are divided into multiple blocks, the address memory that systematically stores the registered address for each block, and the numerical values of the divided blocks are fetched from the register that holds the logical number, and the previously specified address memory An address generation register that captures the registered address equivalent from the equivalent, a means that captures the numerical value of the address memory specified by the address generation register as the next reference numerical value, and finally the logical number of the transfer destination at the address specified by the address generation register. An ATM switch having a conversion table described in (1). 2. An ATM switch that receives a cell including a header including a logical channel number composed of a VPI bit and a VCI bit, converts the logical channel number, and transfers the cell. A register for holding, an address memory for dividing the logical number into blocks of VPI and VCI, systematically storing a registered address for each block, and a register for holding the logical number from VPI or VC.
The value of the address block specified by the address generation register and the address generation register that acquires the registered address from the previously specified address memory equivalent and the value of the address memory specified by the address generation register are referenced next time. And a conversion table in which the VPI bit of the transfer destination is described in the last VPI address when VCI conversion is not required from the read value of the address memory, and the VCI conversion from the read value. If conversion is needed,
It is characterized in that it comprises means for reading the VCI memory and repeating the same operation, and finally, a conversion table in which the VPI / VCI logical number of the transfer destination is described at the address designated by the address generation register. ATM switch. 3. An ATM switch for receiving a cell including a header including a logical channel number, converting the logical channel number and transferring the cell, and a register for holding bits constituting a logical number of the received cell, and the above logic. Numbers are divided into multiple blocks, the address memory that systematically stores the registered address for each block, and the numerical values of the divided blocks are fetched from the register that holds the logical number, and the previously specified address memory If the address generation register that takes in the registered address equivalent group from the equivalent, and the numerical value from the above holding register corresponds to the numerical value in the registered address equivalent group that is taken in by the address generation register,
An ATM switching system characterized by including means for fetching the numerical value of the corresponding address memory as the next reference numerical value, and finally a conversion table in which the logical number of the transfer destination is described at the address specified by the address generation register. ..