JPH08191312A - Atm interface circuit - Google Patents

Abstract

PURPOSE: To simplify the control signal and data write sequence of ATM cell generation processing. CONSTITUTION: This ATM interface circuit is provided with a data FIFO memory 4 which stores data in their arrival order and an address FIFO memory 5 which stores address information in the arrival order corresponding to the addresses of the data FIFO memory 4. Even if different data series are written mixedly in a single data FIFO memory 4, the data series can be discriminated according to the contents of the address FIFO memory 5, so a proper cell header is selected out of the contents and added to pay load data. Cell headers are previously written in a header memory as to all possible communication parties. Consequently, the ATM cell generation processing can be made fast. Further, the throughput of data transfer can be improved.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an asynchronous transfer mode (AT
It is used for M: Asynchronous Transfer Mode). In particular,
The present invention relates to a technique for converting a data packet into an ATM cell format.

[0002]

2. Description of the Related Art ATM used in ATM networks
Cell is a 48-byte user data area (payload)
And a total of 53 bytes of data of a 5-byte cell header used for network control. In data communication, VPI (Virtual Path Identifie) in the header is used.
r), a route is selected based on the value of attribute information called VCI (Virtual Channel Identifier), and the ATM cell is transmitted to a desired destination.

To transmit a data sequence of arbitrary length using ATM cells, the data sequence is divided into payload-sized data segments, and an ATM cell header is added to the data segments to be transmitted sequentially. To extract the payload part from the ATM cell and re-synthesize the data sequence on the receiving side,
It is necessary to identify the ATM cell including the beginning and the end of the data series.

Referring to FIG. 6, ATM according to the AAL5 standard
The cell processing will be described. FIG. 6 is a block diagram of an ATM cell. The data packet is divided into 48-byte packets. At this time, if the data packet is not an integral multiple of 48 bytes, dummy data is inserted at the end to adjust the length. A cell header is added to each of the packets thus divided. Further, the byte length of the data series and the CRC calculation result of all data are inserted at the end.
Based on the value of PTI (Payload Type Identifier) in the cell header, it is determined whether the ATM cell includes the last payload of the data sequence.

As described above, an ATM interface circuit is required to convert a data sequence generated by a computer into ATM cells. For that purpose, the ATM interface circuit and the CPU are connected via a data bus. As a data memory of the ATM interface circuit connected to the data bus, there are a method using a shared memory and a method using a FIFO memory.

A conventional example using a shared memory having address signal lines will be described with reference to FIG. FIG. 7 is a block diagram of a conventional ATM interface circuit using a shared memory. In the ATM interface circuit shown in FIG. 7, all the data series to be processed are written in the shared memory and then the cell formation process is started. A data series, an address pointer designating a range in which the data series exists, and the contents of the cell header are prepared, and a processing start command is sent to start the cell formation processing. The ATM interface circuit reads the contents of the shared memory 48 bytes at a time, adds a cell header, and sends it.

When the processing of the last payload of the data series is completed, a signal for notifying the end of the processing is output to the computer side to prompt the writing of the next data. When inputting to a plurality of data series and adding another cell header, the address area of the data memory is divided and a pointer and a cell header are prepared for each data series. The ATM interface circuit time-divisions the processing of each data series to form cells.

On the other hand, there are two types of conventional examples using a data FIFO memory. One is simply a header, data, end data (signal length, CRC, etc.) and payload of an ATM cell at the end for AAL processing. (Parameters added to the
This is a method of writing to the IFO memory. However, since this conventional example has only a FIFO and has almost no function, a description thereof will be omitted.

A conventional example using the other data FIFO memory will be described with reference to FIG. FIG. 8 shows data F of the conventional example.
It is a block configuration diagram of an ATM interface circuit using an IFO memory. A data series is written from the data bus 1 to the data FIFO memory 4. The cell header is preset in the header memory 14. When the end of the data series is written in the data FIFO memory 4, the end signal is input from the data bus 1. A upon receiving the end signal
The TM cell conversion process is started. At this time, the data FIFO
If the next data series is written to the data FIFO memory 4 before the EMPTY signal indicating that the O memory 4 has become empty is detected, the boundary with the previous data becomes unclear and the ATM cell conversion process is performed. Becomes impossible.

That is, in the system using the FIFO memory as the data memory, the cell assembling process is started from the time when some data is written in the data FIFO memory,
Sequential processing of sequentially written data series. Instead of needing a pointer that indicates the location of the data series,
A termination instruction signal is required from the CPU side to notify the ATM interface circuit of the completion of the writing of the data series.
The ATM interface circuit uses a termination instruction signal and a FIFO.
When the EMPTY signal of the memory is detected, the process of adding the number of data, CRC, and dummy data to the last payload is finally performed. When transmitting a new data sequence on the CPU side, after the end instruction signal is issued, after waiting for the contents of the FIFO memory to become empty, writing of the next data sequence is started.

[0011]

As described above, in the ATM interface circuit using the shared memory, the length of the data series that can be processed at one time is limited by the capacity of the shared memory, and from the start of writing the data series. The delay until the transmission of ATM cells is large. Furthermore, it is difficult to obtain high speed due to the overhead of the limiting procedure such as the designation of the pointer, the instruction to start the process, and the confirmation of the end of the process.

On the other hand, when the FIFO memory is used as the data memory, the means of dividing the area of the data memory cannot be taken. Therefore, in order to simultaneously process a plurality of data series, the same number of FIFO memory banks are required. Will be required.

In both configurations, since a new data series is written after the processing of the previous data series is completed and the data memory is released, the pipeline processing of data input and cell formation cannot be performed.

The present invention has been made against such a background, and it is possible to speed up the ATM cell processing.
It is an object to provide a TM interface circuit.
An object of the present invention is to provide an ATM interface circuit capable of simplifying control signals in ATM cell conversion processing. The present invention can simplify the data write sequence in the ATM cell conversion process.
It is an object to provide a TM interface circuit.
An object of the present invention is to provide an ATM interface circuit that can improve the throughput of data transfer.

[0015]

According to the present invention, there is provided a data input terminal to which data arrives in time series, an address input terminal to which destination information including a header index of an ATM cell arrives corresponding to the data, A memory for temporarily storing data and the destination information and an ATM for controlling this memory
It is an ATM interface circuit including a control circuit for creating cells.

Here, the feature of the present invention is that the memory stores a data FIFO memory for storing the data arriving at the data input end in the order of arrival, and the destination information arriving at the address input end for the data FIFO. Address FIF stored in order of arrival in correspondence with memory address
An O memory is separately provided, and a read circuit for synchronously reading the contents of the two FIFO memories, and a header table selected in accordance with the destination information appearing at the output of the read circuit in which a plurality of ATM cell header information are recorded in advance. It is equipped with and. As a result, it is possible to simplify the control signal and the data write sequence in the ATM cell conversion process, improve the throughput of data transfer, and speed up the ATM cell conversion process.

Here, the data FIFO memory and the address FIFO memory may be composed of two memories different in terms of hardware, but may be realized by dividing the memory area of a single memory into two. . Also,
In this case, the input and output are two inputs
The O memory area and the address FIFO memory area may be operated in parallel, or the data FIFO memory area and the address FIFO memory area may be operated substantially (apparently) in parallel as one input and one output. May be.

It is desirable to provide a header generation circuit for generating header information according to the data coming to the data input terminal and storing it in the header table.

The read circuit includes means for detecting an end signal from the destination information arriving at the address input, and means for generating an error correction code by detecting the end signal and setting the error correction code at the end of the data. Is desirable. As a result, the error correction code can be added to the end of the ATM cell.

The read circuit includes a counting circuit for counting the number of data read from the data FIFO memory,
It is desirable to include means for setting data length information to the end of the data from the contents of the counting circuit by detecting the end signal. As a result, the information of the data sequence length is
It can be added to the end of the TM cell.

The two FIFO memories include a fixed-size writable / readable memory, a write address generation circuit for generating the write address of the writable / readable memory by inputting the destination information, and the read circuit. It is desirable to include a read address generation circuit for generating a read address of the writable / readable memory under control.

[0022]

In the ATM interface circuit according to the present invention,
Even if different data series are mixed and written in a single data FIFO memory, the data series can be identified by the content of the address FIFO memory. Therefore, select an appropriate cell header from this content and add it to the payload data. You can In addition, the value of the address FIFO memory is set to A
Since it is also used to control the TM interface circuit, C
The control procedure of the ATM interface circuit from PU can be simplified. At this time, the cell header does not need to be loaded each time the cell assembling process is performed by writing in advance in the header table for all the communication partners that can communicate, which also improves the speed and simplifies the control procedure. Can contribute.

Further, in order to correspond to a new communication partner, a header generation circuit for generating header information according to incoming data and storing it in a header table may be provided. Thereby, it is possible to flexibly deal with the change of the communication partner.

The end signal of the data series may be added to the value of the address FIFO memory in addition to the selection information of the cell header. This makes it possible to detect the end of the data series, generate an error correction code, and set it at the end of the data series. It is also possible to count the data length and set the result together with the error correction code at the end of the data series.

The write control is performed by generating write addresses of the data FIFO memory and the address FIFO memory using the destination information as an input, and the data FIFO memory is controlled according to the control of the read circuit for synchronously reading the contents of the two FIFO memories. By controlling the reading by generating the read address of the address FIFO memory, the write / read control procedure of the FIFO memory can be simplified.

[0026]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The construction of an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of an apparatus according to the present invention. Figure 2 shows the data FIFO memory and address FI
It is a figure which shows the corresponding state with FO memory.

The present invention comprises a data bus 1 as a data input terminal to which data arrives in time series, and an address bus as an address input terminal to which destination information including a header index of an ATM cell corresponding to this data arrives. 2, and a memory 15 for temporarily storing the data and the destination information
And an control circuit 20 for controlling the memory 15 to create an ATM cell.

Here, the feature of the present invention is that the memory 15 shows the data FIFO memory 4 for storing the data arriving at the data bus 1 in the order of arrival and the destination information arriving at the address bus 2 in FIG. So that the data FIFO
An address FIFO memory 5 for storing the addresses in the order of arrival in correspondence with the addresses of the memory 4 is separately provided, and these two FIFOs are provided.
It is provided with a read circuit 10 for synchronously reading the contents of the O memory, and a header table 12 in which a plurality of header information of ATM cells are recorded in advance and selected according to destination information appearing in the output of the read circuit 10. .

The header generating circuit 11 is provided for generating header information according to the data coming to the data bus 1 and storing it in the header table 12.

The read circuit 10 has a FI as a means for detecting an end signal from the destination information coming to the address bus 2.
FO memory reading circuit 6, sequence length count / CRC calculation circuit 7, counter / CRC memory 8 and selector as means for generating a CRC as an error correction code by setting the end signal and setting the CRC at the end of the data. 9 and 9 are included.

Data FIFO memory 4 and address F
The IFO memory 5 has a fixed-size writable / readable memory (RAM), an address decoder 3 as a write address generation circuit which receives the destination information as an input and generates a write address of the writable / readable memory, and a FIFO. A read address generation circuit 13 for generating a read address of the writable / readable memory under the control of memory read circuit 6.

Next, the operation of the embodiment of the present invention will be described. A data series input from the CPU of the computer via the data bus 1 is first written in the data FIFO memory 4. The address area in which the writing to the data FIFO memory 4 is valid is determined by the address decoder 3 by inputting the upper bits of the address bus shown in FIG. FIG.
FIG. 4 is a diagram showing function allocation of address signal lines. When writing the data series to the data FIFO memory 4, at the same time, the contents of the middle-order bit of the address signal line are changed to the address FI.
Store in the FO memory 5. Therefore, the data FIFO
As shown in FIG. 2, the memory 4 and the address FIFO memory 5 store the same number of one-to-one corresponding data.

The FIFO memory read circuit 6 uses the data FI.
ATM in the FO memory 4 and the address FIFO memory 5
The operation starts when the payload data for one cell (48 bytes in the case of a standard ATM cell) is stored. First, the head data is read from the address FIFO memory 5, and the contents of the header table 12 are referred to by a signal value (hereinafter referred to as an index) represented by a bit string excluding the least significant 1 bit.

This header table 12 has a content of 40 bits per entry, and has as many entries as the number corresponding to the bit width of the index. Therefore, if the index is 4 bits, a table memory having a capacity of 16 entries × 40 bits and 5 entries is 32 entries × 40 bits. Since the contents of different cell headers are set in advance in each entry of the header table 12, the types of cell headers that can be selected and used at the same time without interrupting the ATM cell conversion processing described below are It is the number of entries.

The selector 9 first sequentially transmits the contents of one entry specified by the index from the header table 12 by 5 bytes. Next, switch the selector 9,
The payload data for one cell is read from the data FIFO memory 4 and sequentially transmitted. Of the contents of the address FIFO memory 5 corresponding to the payload data, the data other than the one data used for reference of the header table 12 becomes unnecessary and is discarded only by the read operation. That is, the data FIFO
If the data word width of the memory 4 is 8 bits, it takes 48 steps to read one payload data. Therefore, if the data of 47 pieces in the address FIFO memory 5 is 32 bits, it takes 12 steps to read, so 11 pieces of data are written. Reject. Therefore, when a plurality of data sequences are divided and input by a plurality of write operations, the size of payload data for one cell (48 for a standard ATM cell) is used.
It is necessary to limit the write operation to the unit of an integral multiple of (byte).

As shown in FIG. 3, the contents of the lower bits of the signal lines of the address bus are not used. Therefore, for the data written in the address in the range determined by the number of signals of the lower address bits to be ignored, the same numerical value is used for the address FI
It will be written in the FO memory 5. This is to cope with the fact that DMA (Direct Memory Access) is used to move data at high speed in data transfer using the data bus 1 of the computer. In the write by DMA, the address values on the bus are sequentially added, so this change should not affect the value written in the address FIFO memory 5. For example, the data FIFO
If the capacity of the memory 4 is 32 bits × 4096 words, the lower address signal lines of 12 bits or more are ignored.

In order to carry out the cell formation processing according to the AAL5 standard, it is necessary to calculate the total number of data bytes of each data series and the CRC. The sequence length count / CRC calculation circuit 7 calculates the total number of data and the CRC calculation from the payload data read from the data FIFO memory 4 for each data sequence, that is, for each index. The value being calculated is temporarily stored in the counter / CRC memory 8. The capacity of the counter / CRC memory 8 requires the same number of entries as the header table 12, and in the case of AAL5, each entry requires 16 bits for the counter and 8 bits for the CRC, for a total of 24 bits.

Of the contents stored in the address FIFO memory 5, the least significant 1 bit excluding the index referring to the header table 12 is used to notify the ATM interface circuit that the writing of the data series is completed. To be In the bit allocation of the address signal line of FIG. 3, the address map is arranged as shown in FIG. FIG. 4 is a diagram showing the address map of the data FIFO memory 4 and the writing range of the data series. In normal data writing, data writing is performed in the range shown in the example of writing in areas # 1 and # 2 in FIG. Address F corresponding to this data
The index of the least significant bit of the IFO memory 5 changes to "0" according to the write area (# 1, # 2, ..., #M) and becomes selection information of the cell header. When writing a long data series, the write operation is repeated with division. As described above, since the contents of the address FIFO memory 5 are referenced only once in the payload (48 bytes), when writing another data series between the divided writing,
The data written up to that point must be a multiple of 48 bytes. As long as this condition is satisfied, a plurality of parallel data sequences within the number of entries in the header table 12
Division writing and continuous cell processing can be performed.

When the data string including the end of the data series is to be written at the end, the final data is written so as to cross the boundary as in the example of writing to the area #M in FIG. As a result, the least significant bit of the address index corresponding to the final data becomes "1", and the FIFO detecting this value
The memory read circuit 6 is a sequence length count / CRC calculation circuit 7.
In the case of cell processing according to the AAL5 standard, dummy data for adjusting the size of the payload, the data series length and the final result of the CRC calculation are added to the end, and a series for one data series is added. Ends the process.

This operation will be described in more detail with reference to FIG. FIG. 5 is a diagram showing a procedure for generating the end signal. As a write pattern of a data packet from the data bus 1, one packet is not always completed by writing once. Thereby, the data packet can be written without being limited by the capacity of the data FIFO memory 4.
At this time, when the data packet is divided and written, if it is intermittent, the data FIFO memory 4 may temporarily lose data, but this cannot be the end of the data sequence. A termination signal is required.

Unlike the conventional example in which a dedicated end signal line is used for the end signal, the least significant 1 bit of the address FIFO memory 5 is used in the present invention. An end signal is obtained by setting the least significant 1 bit to "1". Therefore, one word is written in the last data writing end area #M. Since the data writing uses DMA, the address is incremented each time one word is written. By causing the tail end to stick out and be caught in the write end address area, data writing and the process of setting the lowest bit of the address FIFO memory 5 by 1 bit can be performed at the same time. Further, in the present invention, it is possible to determine the end of the data packet even if the data FIFO memory 4 does not become completely empty.

The contents of the cell header to be prepared in the header table 12 are written in advance from another port directly connected to the data bus 1 and the address bus 2. Although the header generation circuit 11 is shown in FIG. 1, this circuit may be provided on the computer side. Here, the header table 12
The number of types of cell headers that can be set at once is determined by the number of bits of the index written in the address FIFO memory 5. For example, if the content of the address FIFO memory 5 is 5 bits, one of them is used as a data end display flag signal, and 1 is determined by identifying the remaining 4 bits.
Six types of cell headers (denoted by M in FIG. 4) can be used.

As described above, in the ATM network circuit according to the present invention, different cell headers are added while adopting a structure using the FIFO memory which can start the cell assembling process immediately after the payload data is written in the data FIFO memory 4. It enables data writing in which a plurality of data series should be mixed and cell processing thereof. Further, since only the change of the write address is used to notify the end of the data series from the data bus 1 side,
Since the program control on the data writing side is simplified without the need for incidental control signals, high speed data input to the ATM interface circuit can be performed.

[0044]

As described above, according to the present invention,
The ATM cell processing can be speeded up. That is, according to the present invention, the control signal and the data write sequence in the ATM cell conversion process can be simplified. As a result, the throughput of data transfer can be improved.

[Brief description of drawings]

FIG. 1 is a block configuration diagram of an apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing a correspondence state between a data FIFO memory and an address FIFO memory.

FIG. 3 is a diagram showing function allocation of address signal lines.

FIG. 4 is a diagram showing an address map of a data FIFO memory and a writing range of a data series.

FIG. 5 is a diagram showing a procedure for generating an end signal.

FIG. 6 is a block diagram of an ATM cell.

FIG. 7 is a block configuration diagram of an ATM interface circuit using a shared memory of a conventional example.

FIG. 8 is an ATM using a conventional data FIFO memory.
FIG. 3 is a block configuration diagram of an interface circuit.

[Explanation of symbols]

 1 data bus 2 address bus 3 address decoder 4 data FIFO memory 5 address FIFO memory 6 FIFO memory read circuit 7 sequence length count / CRC calculation circuit 8 counter / CRC memory 9 selector 10 read circuit 11 header generation circuit 12 header table 13 read Address generation circuit 14 Header memory 15 Memory 20 Control circuit

Claims (5)

[Claims] 1. A data input terminal to which data arrives in time series, an address input terminal to which destination information including a header index of an ATM cell arrives corresponding to this data, and the data and the destination information are temporarily stored. Memory and
An ATM interface circuit including a control circuit for controlling the memory to create an ATM cell, wherein the memory includes a data FIFO memory for storing data arriving at the data input end in the order of arrival, and an address input end for the data FIFO memory. Address FI for storing destination information to be stored in the order of arrival in correspondence with the address of the data FIFO memory
A FO memory is separately provided, and a read circuit for synchronously reading the contents of the two FIFO memories, and a header table selected according to destination information appearing in the output of the read circuit in which a plurality of ATM cell header information is recorded in advance An ATM interface circuit comprising: 2. The ATM according to claim 1, further comprising a header generation circuit for generating header information according to the data arriving at the data input terminal and storing the header information in the header table.
Interface circuit. 3. The read circuit includes means for detecting an end signal from destination information arriving at the address input, and means for detecting an end signal to generate an error correction code and setting the error correction code at the end of the data. An ATM interface circuit according to claim 1 or 2, including the following. 4. The data FIFO is provided in the read circuit.
4. The ATM interface according to claim 3, further comprising: a counting circuit for counting the number of data read from the memory; and means for setting data length information from the contents of the counting circuit to the end of the data by detecting the end signal. circuit. 5. The two FIFO memories are a writable and readable memory having a fixed size, a write address generation circuit that receives the destination information and generates a write address of the writable and readable memory, and the read. 5. An ATM interface circuit according to claim 1, further comprising a read address generation circuit for generating a read address of the writable / readable memory under the control of the circuit.