CN100531123C - Method and device for converting data-packet-mode into element-frame-mode - Google Patents
Method and device for converting data-packet-mode into element-frame-mode Download PDFInfo
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- CN100531123C CN100531123C CNB2005101306049A CN200510130604A CN100531123C CN 100531123 C CN100531123 C CN 100531123C CN B2005101306049 A CNB2005101306049 A CN B2005101306049A CN 200510130604 A CN200510130604 A CN 200510130604A CN 100531123 C CN100531123 C CN 100531123C
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Abstract
This invention discloses the device and method that realizes the data packet mode switching to cell frame, it is applied to communication field, this device includes: data packet reception module, it is used to receive the data packet sent from external network, and writes the signal at the beginning and the end, then it stores the signal to FIFO data packet; cell frame generating module, it is used to read the data in FIFO data packet and assembles the cell frame according to the system setting cell frame size, then store it to SRAM module; cell frame FIFO module, it is used to realize the stated cell frame cushioning, and has the management to SRAM state, the stated SRAM state is virtualized to FIFO memory; cell frame sending module, it is used to read the cell frame and send it to the next system from the cell frame FIFO module. The adoption of this invention can achieve the effects of rapid data transmission and the simplified system design, it saves the SRAM resources in FPGA and improves the utilization of system resources.
Description
Technical field
The present invention relates to communication field, particularly relate to the method that data are transmitted in a kind of this field from the mode data packet to the element-frame, realize the data forwarding between the different pieces of information pattern.
Background technology
In communication system, there is different data-transmission modes in different chips, sums up and gets up to have two kinds: a kind of bag that is based on transmits, and another kind is based on the transmission of cell frame.The difference of these two kinds of pattern maximums is that packet (Data Packet) pattern has the special signal indication, comprising: unwrap beginning signal SOP (Start OfPackage), end-of-packet signal EOP (End Of Package) and data useful signal ENA (Enable) (as shown in Figure 1); And cell frame (Cell Framer) pattern becomes littler unit cell (Cell) transmission with complete bag fractionation, the cell frame is formed (as shown in Figure 2) by header CH (Cell Header) and cell load CP (Cell Payload), frame information adds among the CH, the character, cell length and the cell passage that indicate this cell residing position, bag in bag, CH mainly is made up of Type (cell type) and Length (cell length), and receiver side recovers complete packet according to CH.
At present, realize that the existing method that data are changed adopts two FIFO (First-In First-Out from the mode data packet to the element-frame, first in first out) formation realizes that a fifo queue is used for depositing the CP of cell frame, and another is used for depositing the CH part, this method at first will generate CH and CP respectively, and deposit among each self-corresponding FIFO, when receiver side can receive cell, transmitter side at first will read header CH, analyze CH again, remove to read CP according to the content of CH.This method needs two FIFO, system complex, and complex operation influences the stability of a system.
Summary of the invention
Technical problem to be solved by this invention is to provide a kind of devices and methods therefor of realizing mode data packet to the element-frame conversion, is used for overcoming the system complex that prior art exists, and complex operation influences problem and defectives such as the stability of a system.
To achieve these goals, the invention provides a kind of device of realizing mode data packet to the element-frame conversion, be applicable to communication field, it is characterized in that, comprising:
One packet receiver module is used to receive external network and passes the packet of coming, and fills in sign at the head and tail of this packet, and deposits among the packet FIFO;
One cell frame generation module is used for reading the packet of described packet FIFO and is assembled into a cell frame according to the cell frame sign of default, and deposits in the SRAM module;
One cell frame fifo module is used to realize the buffering of described cell frame, and the SRAM state is managed, and described SRAM module is invented a FIFO memory; And
One cell frame sending module is used for reading the cell frame and sending to the next stage system from described cell frame fifo module.
Described realization mode data packet is to the device of element-frame conversion, and wherein, described packet receiver module comprises a packet bus interface, a packet generation module and described packet FIFO again;
The data channel that described packet bus interface enters FPGA as packet;
Described packet generation module is used for receiving data according to SOP, the EOP of described packet bus interface and ENA signal, and in packet, add data packet head and packet tail tag will, generation is suitable for the data packet format that next stage is handled, and the packet that generates is deposited among the described packet FIFO again;
Described SOP is for unwrapping the beginning signal, and described EOP is the end-of-packet signal, and described ENA is the data useful signal.
Described realization mode data packet is to the device of element-frame conversion, and wherein, described cell frame generation module comprises that again a cell generation module and writes SRAM address control module;
Described cell generation module is used for from described packet FIFO read data packet, this packet is cut apart, generate header and cell load, be assembled into a complete cell frame, and stamp sign at the starting and ending of each described cell frame, more described cell frame is deposited in the described SRAM module;
The described SRAM of writing address control module is used to cooperate that described cell generation module generates header and cell load writes the SRAM address.
Described realization mode data packet is to the device of element-frame conversion, and wherein, described cell frame fifo module comprises a described SRAM module and a SRAM administration module again; Wherein
Described SRAM module has the data check position as the beginning flag of cell frame as a FPGA internal SRAM;
Described SRAM administration module is used for described SRAM module is invented a FIFO memory, generates to read SRAM address, the empty full scale will of FIFO and read-write SRAM permission sign.
Described realization mode data packet is to the device of element-frame conversion, and wherein, described cell frame sending module comprises a cell frame read module and a cell bus interface again;
Described cell frame read module is used for allowing to indicate the disposable complete cell frame that reads according to the read-write SRAM of described cell frame fifo module;
Described cell bus interface is used for described complete cell frame is sent to the next stage chip.
To achieve these goals, the invention provides a kind of method of utilizing described device realization mode data packet to the element-frame conversion, be applicable to communication field, it is characterized in that, comprise step:
Step 610, the packet receiver module receives external network and passes the packet of coming, and fills in sign at the head and tail of this packet, and deposits among the packet FIFO;
Step 620, cell frame generation module reads the packet among the described packet FIFO, is assembled into the cell frame according to the cell frame sign of default, and deposits in the SRAM module;
Step 630, cell frame fifo module realize described cell frame buffering, and the SRAM state is managed, and described SRAM module is invented the FIFO memory; And
Step 640, cell frame sending module reads the cell frame and sends to the next stage system from described cell frame fifo module.
Described realization mode data packet wherein, in the described step 610, is filled in sign according to SOP and eop signal at the head and tail of this packet to the method for element-frame conversion; Described SOP is for unwrapping the beginning signal, and described EOP is the end-of-packet signal.
Described realization mode data packet is to the method for element-frame conversion, wherein, in the described step 620, comprise also whether the cell generation module of judging in the described cell frame generation module continues to inquire about the step of the SRAM administration module in described packet FIFO and the described cell frame fifo module; If described packet FIFO comprises one or more complete packets and described SRAM administration module allows then to stop inquiry when described SRAM module writes data, continue inquiry if not.
Described realization mode data packet is to the method for element-frame conversion, wherein, in the described step 620, also comprise cell generation module in the described cell frame generation module from described packet FIFO by the continuous read data packet of word, deposit described SRAM module in by the SRAM address that SRAM address control module generates of writing in the described cell frame generation module, and to the step of cell length counting.
Described realization mode data packet wherein, in the described step 620, also comprises this packet is cut apart to the method for element-frame conversion, generates the step of header and cell load.
Described realization mode data packet is to the method for element-frame conversion, wherein, in the described step 620, also is included in described header and defines type, the length of whole cell and cell beginning flag position is set and this header is write the step of SRAM module.
Described realization mode data packet is to the method for element-frame conversion, and wherein, in the described step 640, described cell frame sending module is read the cell frame according to the information of described header.
A kind of simple address control provided by the invention realizes the method and apparatus of mode data packet to the element-frame conversion, has solved the system complex that exists in the prior art, and complex operation influences problem and defectives such as the stability of a system; Compared with prior art, beneficial effect of the present invention is:
Adopt the method for the invention and device, obtained and used address control directly the SRAM in the cell frame fifo module to be operated, realization is placed on progress among the same FIFO with header CH and cell load CP, having reached rapid data transmits and the simplified system design effect, saved FPGA (FieldProgrammable Gate Array, field programmable logic array) internal SRAM (Static RandomAccess Memory, static random access memory) resource has improved resource utilization ratio.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is the sequential chart of data packet transmission pattern;
Fig. 2 is the sequential chart of cell frame transmission mode;
Fig. 3 is modular structure figure of the present invention;
Fig. 4 is a Data Labels of the present invention position key diagram;
Fig. 5 is flow chart of data processing figure of the present invention.
Embodiment
Below in conjunction with accompanying drawing the control of simple address is realized that mode data packet is described in further detail to the enforcement of the method and apparatus of element-frame conversion.
See also shown in Figure 3ly, be modular structure figure of the present invention.In conjunction with shown in Figure 4, this modular structure comprises with lower module for the present invention's simple address control realizes the device of mode data packet to the element-frame conversion:
Packet receiver module 301 is used to receive external network and passes the data of coming, and fills in sign at the head and tail of packet, deposits among the packet FIFO, and it comprises packet bus interface 302, packet generation module 303 and packet FIFO304.Wherein, packet bus interface 302 is data channel that packet enters FPGA, packet generation module 303 receives data according to SOP, EOP and the ENA signal of packet bus interface 302, and in packet, add data packet head and packet tail tag will, generation is suitable for the data packet format (as shown in Figure 4) that next stage is handled, and then the packet that generates is deposited among the packet FIFO304.
Cell frame generation module 305 is used for the packet of read data packet FIFO304 and assembles cell according to the cell size of default, deposits among the SRAM, and it comprises cell generation module 306 and writes SRAM (static memory) address control module 307.Wherein, cell generation module 306 is read data packet from packet FIFO304, packet is cut apart, generate header CH and cell load CP, be assembled into a complete cell frame, and stamp flag bit (it is identical that flag bit definition and the starting and ending flag bit of packet define, referring to shown in Figure 4) at the starting and ending of each cell frame, then the cell frame is deposited in the SRAM module 309; That writes that SRAM address control module 307 cooperates that cell generation modules 306 generate header CH and cell load CP writes the SRAM address.
Cell frame fifo module 308 is used to realize cell frame buffering, and the SRAM state is managed, and SRAM is invented a FIFO memory, and it comprises SRAM module 309 and SRAM administration module 310.Cell frame fifo module 308 is virtual FIFO, and for cell frame generation module 305, cell frame fifo module 308 is SRAM, and write address can be controlled; And for cell frame sending module 311, cell frame fifo module 308 is FIFO of a standard, and it is uncontrollable to read the address.Wherein, SRAM module 309 is FPGA internal SRAMs, has the data check position, can be used as the beginning flag of cell frame; SRAM administration module 310 is that SRAM module 309 is invented a FIFO, and it is finished and generates functions such as reading SRAM address, the empty full scale will of FIFO and read-write SRAM permission sign.
Cell frame sending module 311 is used for reading the cell frame and sending to the next stage system from cell frame fifo module 308, and it comprises cell frame read module 312 and cell bus interface 313.Wherein, cell frame read module 312 is to read a complete cell frame according to the read-write SRAM of cell frame fifo module 308 sign is disposable, and cell bus interface 313 is that complete cell frame is sent to the next stage chip.
See also shown in Figure 4ly, be Data Labels of the present invention position key diagram.In the figure, the Data Labels position comprises the head and tail of flag data bag, is made up of bit16, bit17, and it is defined as: word in the middle of the 00 expression packet, and 01 expression packet banner word, 10 expression packets finish word, and 11 expression packets finish and are wrong.
See also shown in Figure 5ly, be flow chart of data processing figure of the present invention.This flow chart comprises the steps:
Step 4, flag bit is set to 01, and changes step 8;
Step 5 judges whether eop signal equals 1, if not, then changes step 7; If continue step 6;
Step 6, flag bit is set to 10, and changes step 8;
Step 7, flag bit is set to 00;
Step 8 receives data and forms new data with flag bit and deposits buffer in, continues step 9 or step 10;
Step 9 is returned step 1;
Has step 11 judged whether a complete packet? if not, return step 10; If continue step 12;
Step 12 is write the SRAM address process;
Step 13 reads a word and deposits SRAM in from FIFO, write address adds 1;
Does step 14 judge that further the end-of-packet sign is 1? if change step 16; If not, continue step 15;
Does step 15 further judge whether to reach maximum length? if not, return step 13; If continue step 16;
Step 16, the assembling header also deposits SRAM in;
Does step 17 further judge whether to run through a packet? if not, return step 13; If return step 10.
Describe in further detail below and analysis chart 5 in for the step that enters processing data packets of the present invention, simultaneously in conjunction with shown in Figure 3, specifically comprise:
Step 1: receive packet, packet receiver module 301 detects the ENA signal when being high, begin to receive the data on the bus, and the data that deposit packet FIFO304 in are carried out mark according to SOP and eop signal, when EOP was 1, flag bit was 2 ' b10, when SOP is 1, flag bit is 2 ' b01, otherwise the flag bit of other data all is 2 ' b00.Packet FIFO304 is provided with marking signal after receiving a complete data packet, handles to cell frame generation module 305 read data packet of giving notice.
Step 4, cell generation module 306 constantly reads by word from packet FIFO304, deposit SRAM module 309 in by the SRAM address of writing 307 generations of SRAM address control module, and to cell length counting Counter (counter), up to reaching the maximum cell length of system's setting when the Counter value or detecting the bag flag bit is that 2 ' b10 stops, and in the end a word adds flag bit (the flag bit definition is identical with the definition of packet flag bit) 2 ' b10, enters step 5 and handles.Write SRAM address control module 307 simultaneously and constantly the SRAM address is added 1 operation, generate and write the SRAM address.In reading of data, be 2 ' b01 if detect the bag flag bit, it is 1 that leader will Packet_Head (packet header) then is set, otherwise puts 0.
Step 5 writes SRAM address control module 307 current address value is deposited in the tail address variable, and the current address is set to the leading address variate-value.
Step 6, cell generation module 306 generates header CH, the type field of header CH is filled according to the flag bit and the Packet_Head of the last character that reads from packet FIFO304, the Length field of header CH is filled according to the Counter value, flag bit at header CH word is set to 2 ' b01, then whole header CH word is write in the SRAM module 309 by the address of writing SRAM address control module 307 and providing.
Step 7 is write SRAM address control module 307 current address values and is set to tail address variate-value.Enter step 2, continue data query bag FIFO304 and SRAM administration module 310.
Step 8,310 pairs of SRAM modules 309 of SRAM administration module manage, word space and cell number in the record SRAM module 309, after receiving a complete cell frame, flag bit is set waits for 312 inquiries of cell frame read module, when cell frame read module 312 reads the cell frame, generate and read SRAM module 309 addresses.
Step 9, cell frame read module 312 be inquiry SRAM administration modules 310 constantly, when a complete cell frame is arranged in inquiring SRAM module 309, read SRAM module 309, are that 2 ' b01 stops up to detecting the cell flag bit.The cell frame is sent to the next stage system by cell bus interface 313.Finish of the forwarding of whole packet to the cell frame.
Adopt the method for the invention and device, obtained and used address control directly the SRAM in the cell frame fifo module to be operated, realization is placed on progress among the same FIFO with header CH and cell load CP, having reached rapid data transmits and the simplified system design effect, save FPGA internal SRAM resource, improved system resource utilization.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (12)
1, a kind of device of realizing mode data packet to the element-frame conversion is applicable to communication field, it is characterized in that, comprising:
One packet receiver module is used to receive external network and passes the packet of coming, and fills in sign at the head and tail of this packet, and deposits among the packet FIFO;
One cell frame generation module is used for reading the packet of described packet FIFO and is assembled into a cell frame according to the cell frame sign of default, and deposits in the SRAM module;
One cell frame fifo module is used to realize the buffering of described cell frame, and the SRAM state is managed, and described SRAM module is invented a FIFO memory; And
One cell frame sending module is used for reading the cell frame and sending to the next stage system from described cell frame fifo module.
2, realization mode data packet according to claim 1 is characterized in that to the device of element-frame conversion described packet receiver module comprises a packet bus interface, a packet generation module and described packet FIFO again;
The data channel that described packet bus interface enters FPGA as packet;
Described packet generation module is used for receiving data according to SOP, the EOP of described packet bus interface and ENA signal, and in packet, add data packet head and packet tail tag will, generation is suitable for the data packet format that next stage is handled, and the packet that generates is deposited among the described packet FIFO again;
Described SOP is for unwrapping the beginning signal, and described EOP is the end-of-packet signal, and described ENA is the data useful signal.
3, realization mode data packet according to claim 1 and 2 is characterized in that to the device of element-frame conversion, and described cell frame generation module comprises that again a cell generation module and writes SRAM address control module;
Described cell generation module is used for from described packet FIFO read data packet, this packet is cut apart, generate header and cell load, be assembled into a complete cell frame, and stamp sign at the starting and ending of each described cell frame, more described cell frame is deposited in the described SRAM module;
The described SRAM of writing address control module is used to cooperate that described cell generation module generates header and cell load writes the SRAM address.
4, realization mode data packet according to claim 1 is characterized in that to the device of element-frame conversion described cell frame fifo module comprises a described SRAM module and a SRAM administration module again; Wherein
Described SRAM module has the data check position as the beginning flag of cell frame as a FPGA internal SRAM;
Described SRAM administration module is used for described SRAM module is invented a FIFO memory, generates to read SRAM address, the empty full scale will of FIFO and read-write SRAM permission sign.
5, realization mode data packet according to claim 4 is characterized in that to the device of element-frame conversion described cell frame sending module comprises a cell frame read module and a cell bus interface again;
Described cell frame read module is used for allowing to indicate the disposable complete cell frame that reads according to the read-write SRAM of described cell frame fifo module;
Described cell bus interface is used for described complete cell frame is sent to the next stage chip.
6, a kind of described device of claim 1 that utilizes is realized the method for mode data packet to the element-frame conversion, is applicable to communication field, it is characterized in that, comprises step:
Step 610, the packet receiver module receives external network and passes the packet of coming, and fills in sign at the head and tail of this packet, and deposits among the packet FIFO;
Step 620, cell frame generation module reads the packet among the described packet FIFO, is assembled into the cell frame according to the cell frame sign of default, and deposits in the SRAM module;
Step 630, cell frame fifo module realize described cell frame buffering, and the SRAM state is managed, and described SRAM module is invented the FIFO memory; And
Step 640, cell frame sending module reads the cell frame and sends to the next stage system from described cell frame fifo module.
7, realization mode data packet according to claim 6 is characterized in that to the method for element-frame conversion, in the described step 610, fills in sign according to SOP and eop signal at the head and tail of this packet; Described SOP is for unwrapping the beginning signal, and described EOP is the end-of-packet signal.
8, according to claim 6 or 7 described realization mode data packets method to the element-frame conversion, it is characterized in that, in the described step 620, comprise also whether the cell generation module of judging in the described cell frame generation module continues to inquire about the step of the SRAM administration module in described packet FIFO and the described cell frame fifo module; If described packet FIFO comprises one or more complete packets and described SRAM administration module allows then to stop inquiry when described SRAM module writes data, continue inquiry if not.
9, according to claim 6 or 7 described realization mode data packets method to the element-frame conversion, it is characterized in that, in the described step 620, also comprise cell generation module in the described cell frame generation module from described packet FIFO by the continuous read data packet of word, deposit described SRAM module in by the SRAM address that SRAM address control module generates of writing in the described cell frame generation module, and to the step of cell length counting.
10, according to claim 6 or 7 described realization mode data packets method, it is characterized in that, in the described step 620, also comprise this packet is cut apart, generate the step of header and cell load to the element-frame conversion.
11, realization mode data packet according to claim 10 is to the method for element-frame conversion, it is characterized in that, in the described step 620, also be included in described header and define type, the length of whole cell and cell beginning flag position is set and this header is write the step of SRAM module.
12, realization mode data packet according to claim 11 is characterized in that to the method for element-frame conversion in the described step 640, described cell frame sending module is read the cell frame according to the information of described header.
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| CNB2005101306049A CN100531123C (en) | 2005-12-14 | 2005-12-14 | Method and device for converting data-packet-mode into element-frame-mode |
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| CNB2005101306049A CN100531123C (en) | 2005-12-14 | 2005-12-14 | Method and device for converting data-packet-mode into element-frame-mode |
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| CN100531123C true CN100531123C (en) | 2009-08-19 |
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Families Citing this family (5)
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| CN105471767A (en) * | 2014-08-25 | 2016-04-06 | 深圳市中兴微电子技术有限公司 | Switch access module, cell packaging method and switch network system |
| CN105262562A (en) * | 2015-09-07 | 2016-01-20 | 香港中文大学深圳研究院 | Preprocessing method for grouping and recombining algebraic exchange engine data packets |
| CN105446699A (en) * | 2015-12-07 | 2016-03-30 | 中国电子科技集团公司第十研究所 | Data frame queue management method |
| CN106878196B (en) * | 2017-01-16 | 2021-02-05 | 许继集团有限公司 | Data processing method and device of ADC plug-in |
| CN106961324A (en) * | 2017-04-19 | 2017-07-18 | 福建中金在线信息科技有限公司 | A kind of message encryption method and device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08191312A (en) | 1995-01-11 | 1996-07-23 | Nippon Telegr & Teleph Corp <Ntt> | Atm interface circuit |
| CN1351784A (en) * | 1999-03-05 | 2002-05-29 | 美商传威股份有限公司 | Method and apparatus for managing multiple ATM cell queues |
| CN1476212A (en) * | 2002-08-12 | 2004-02-18 | 深圳市中兴通讯股份有限公司上海第二 | Method and device for realizing data package transmission on synchronous digital system |
| CN1150728C (en) * | 1998-06-15 | 2004-05-19 | 诺基亚高速接入产品公司 | Switching system data interface |
| US6829240B1 (en) * | 1996-11-27 | 2004-12-07 | Mindspeed Technologies, Inc. | System for, and method of, ATM segmentation and re-assembly of cells providing streaming data |
-
2005
- 2005-12-14 CN CNB2005101306049A patent/CN100531123C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH08191312A (en) | 1995-01-11 | 1996-07-23 | Nippon Telegr & Teleph Corp <Ntt> | Atm interface circuit |
| US6829240B1 (en) * | 1996-11-27 | 2004-12-07 | Mindspeed Technologies, Inc. | System for, and method of, ATM segmentation and re-assembly of cells providing streaming data |
| CN1150728C (en) * | 1998-06-15 | 2004-05-19 | 诺基亚高速接入产品公司 | Switching system data interface |
| CN1351784A (en) * | 1999-03-05 | 2002-05-29 | 美商传威股份有限公司 | Method and apparatus for managing multiple ATM cell queues |
| CN1476212A (en) * | 2002-08-12 | 2004-02-18 | 深圳市中兴通讯股份有限公司上海第二 | Method and device for realizing data package transmission on synchronous digital system |
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