JPH10341238A - Reception atm cell processing controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the reception ATM cell processing controller employing a retrieval means for an address pointer to process storage of received asynchronous transfer mode ATM cells to a reception buffer based on virtual path identifier/virtual channel identifier (VPI/VCI) data with a smaller circuit-scale and at an enhanced retrieval speed. SOLUTION: The controller is provided with a VC table 6 that is separated into banks I-N including a plurality of entries, data in all VPI/VCI fields 62 in a bank selected by a selector 5 are simultaneously outputted, the data are compared with VPI/VCI data having been extracted from an ATM cell header and stored by a VPI/VCI comparator circuit 2 and coincident entry numbers are detected. Pointer data in a buffer storing a payload of the ATM cell are read from a pointer field 61 in the entry of the VC table 6 by a pointer read circuit 3 based on the entry number.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ATM (Asynchro
Nous Transfer Mode) For a receiving cell processing device in a communication terminal, more specifically, a VC (Vir
tual Connection) table search circuit.

[0002]

2. Description of the Related Art In an ATM communication terminal, in order to store a received ATM cell in a reception buffer, a VC table is used to determine which packet in the reception buffer is a part of the received ATM cell based on information of an ATM cell header. Judgment is made using this, and the packet is added to the found packet.

FIG. 3 is a schematic diagram showing an example of a conventional processing means for a received ATM cell and an operation flow thereof.
Referring to FIG. 3, in the receiving ATM cell processing device 8, the received 53-byte ATM cell 81 is stored in the receiving cell FIFO 82, and the 5-byte ATM cell header 812 is first read. Each entry of the VC table 6 has a VPI (Virtual Path Identifier) / VC
There are an I (Virtual Channel Identifier) field 62, a pointer field 61 indicating a reception buffer, and other fields 63, and a VPI (Virtual Path Identifier) / VCI that matches the value of the VPI / VCI in the header.
From the entry in the VC table 6 having the (Virtual Channel Identifier) field 62, the data value of the pointer field 61 indicating the reception buffer is read. ATM received based on the data value of the pointer field 61
The address for storing the 48-byte payload 811 of the cell 81 is calculated. Then, the payload 811 of 48 bytes read from the reception cell FIFO 82 is stored in the main memory 9 of the system in the VPI corresponding to the payload.
The data is written to the address 92 calculated as the storage location of the / VCI reception buffer 91.

FIG. 4 is a diagram showing the structure of an ATM cell 81 conventionally used and also shown in FIG. In FIG. 4, A
The TM cell 81 is composed of 53 bytes. The first 5 bytes form an ATM cell header 812, and the remaining 48 bytes form a payload 811 for storing information.

FIG. 5 shows a data value of VPI / VCI in the ATM cell header 812 or a VPI / VCI in the VC table 6.
5 is a configuration diagram illustrating a bit string of a PI / VCI field 62. FIG. V read from the ATM cell header 812
PI / VCI data value and V in the VC table 6
The data value of the PI / VCI field 62 has a VPI data value 112 in the upper 8 bits and a VCI data in the lower 16 bits.
Is a 24-bit data value 11 configured by combining the data values 111 of.

As described above, in order to store the payload 811 in the received ATM cell 81 in the reception buffer 91, the VPI / VCI field 62 corresponding to the VPI / VCI data value in the ATM cell header 812 is required. It is necessary to find an entry in the VC table 6. As this method, a method using a search table is cited as an example of the related art.

FIG. 6 is a configuration diagram showing an example of a search table used in a conventional reception ATM processing device. Referring to FIG. 6, the search table 12 includes entries corresponding to data values of VPI / VCI, and each entry includes a pointer to each entry in the VC table 6. FIG.
Since the VPI / VCI data value is 24 bits, the search table 12 has entries from 0 to 16777215 corresponding to the VPI / VCI data value. In FIG. 3, the VPI in the ATM cell header 812
To find an entry in the VC table 6 that has a VPI / VCI field 62 that matches the data value of / VCI, the search table 12 in FIG. 6 is used. The entries in the search table 12 are prepared for the number of data values of all the VPI / VCIs and are arranged in the order of the data values of the VPI / VCI. The table pointer 121 is read. Then, the entry in the VC table 6 is designated by the read pointer.

[0008]

In the case of the above-mentioned method using the search table, if all bits of the data value of the VPI / VCI are used, the entry of the table becomes 16
If it is assumed that 777216 pieces are required and two bytes of memory are used for one entry, 32 Mbytes of memory will be required. As described above, the conventional method using the lookup table requires a very large amount of memory,
There has been a problem that the circuit scale becomes large and causes an increase in cost. SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems in the related art, and has been developed as an address pointer search means for performing processing for storing a received ATM cell in a reception buffer based on VPI / VCI data in a header. It is an object of the present invention to provide a receiving ATM cell processing device using means for reducing the circuit scale and improving the search speed.

[0009]

According to a first aspect of the present invention, there is provided a VC table having at least an entry having a VPI / VCI field and a pointer field, and data stored in an entry of the VC table. And a VPI holding the VPI / VCI data read from the received ATM cell header.
/ VCI register, the selector and the VPI / VC
A VPI / VCI comparison circuit for comparing output data of an I register, a pointer read circuit for reading data stored in a pointer field in an entry of the VC table, and a VC table search control circuit for controlling the search of the VC table. Wherein the selector outputs only data stored in a VPI / VCI field in an entry of the VC table to the VPI / VCI comparison circuit, and the VC table search control circuit Is the V that stores data that matches from the comparison result by the VPI / VCI comparison circuit.
Sending data designating an entry in the C table to the pointer reading circuit,
Pointer data stored in a pointer field in an entry of the VC table is read based on designated data from the VC table search control circuit.

According to a second aspect of the present invention, in the first aspect of the present invention, the VC table is divided into banks including a plurality of entries, and the VC table search control circuit outputs
The selector outputs data designating the bank of the C table. The selector selects the bank specified by the output of the VC table search control circuit, and selects the VPI in the entries of all the VC tables in the selected bank. /
The data stored in the VCI field is simultaneously
This is output to the I / VCI comparison circuit.

According to a third aspect of the present invention, in the first or the second aspect of the present invention, the VC table has a VC table cache, and the data stored in the hit entry is stored in the VC table.
A means for copying to the C table cache and a means for changing the priority of data stored in each entry of the VC table cache are provided.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a configuration diagram showing a processing circuit portion including a VC table search circuit of a reception ATM cell processing control device according to an embodiment of the present invention. Referring to FIG. 1, a VC table 6 composed of a plurality of entries, a selector 5 for selecting and outputting data in the entries of the VC table 6, and a data value of VPI / VCI read from the ATM cell header 812 Hold V
PI / VCI register 4, selector 5 and VPI / VC
A VPI / VCI comparison circuit 2 for comparing the output of the I register 4, a pointer reading circuit 3 for reading the data value of the pointer field 61 from the VC table 6, and a VC table search control circuit 1 for controlling the search of the VC table 6 It is included in the reception ATM cell processing device, and is a portion corresponding to the reception ATM cell processing device 8 in the conventional device shown in FIG.

The VPI / VCI register 4 corresponds to the AT of FIG.
The VPI / VCI data value extracted from the M cell header 812 is held and output to the VPI / VCI comparison circuit 2. The VC table 6 manages a bank including an arbitrary number (here, M) of entries by dividing the bank by bank, and selects a bank selected by the selector 5 from the VC table 6 (here, consisting of N banks). The data values of all VPI / VCI fields 62 in the bank are output simultaneously. Further, in response to a request from the pointer read circuit 3, the data value of the pointer field 61 of the designated entry is read.

The selector 5 selects a bank in the VC table 6 according to the bank number specified by the VC table search control circuit 1, and selects all VPI / VCI fields 62 output from the selected bank in the VC table 6.
Outputs the data value of. The VPI / VCI comparison circuit 2
The output from the VPI / VCI register 4 is compared with the output from the selector 5, and the comparison result is sent to the VC table search control circuit 1. The pointer reading circuit 3 designates the matched VPI / VCI according to the comparison result by the VC table search control circuit 1, and reads the data value of the pointer field 61 from the designated entry in the VC table 6.

The operation of one embodiment of the receiving ATM cell processing apparatus will be described below. Referring to FIGS. 1 and 3, the data value of the VPI / VCI extracted from the ATM cell header 812 in the received ATM cell 81 is stored in the VPI / VCI register 4 when input to the present apparatus. When a search start command comes, the VC table search control circuit 1
In order to search the VC table 6, the bank numbers are sequentially given to the selector 5. First, the bank number 1 is given to the selector 5. The selector 5 simultaneously reads out all the data values of the VPI / VCI field of each entry of the bank 1 from the VC table 6, and
Output to the I comparison circuit 2.

The VPI / VCI comparison circuit 2 has a VPI / V
ATM cell header 81 stored in CI register 4
2 and the data value of the VPI / VCI field 62 for one bank input from the selector 5 at the same time, and as a result, information as to whether or not a hit has occurred, Information about the entry is sent to the VC table search control circuit 1. VC
The table search control circuit 1 includes:
If there is no hit, the values from 2 to N are sequentially passed to the selector 5 as the bank number, and the above-described series of search operations is repeated. In the above search operation, if a hit is found, the VC table search circuit calculates the entry number in the VC table 6 and sends the VC number to the pointer read circuit 3.
A table entry number is sent, and reading of the VC table 6 is requested.

The pointer reading circuit 3 calculates the address of the pointer field 61 included in this entry in the VC table 6 from the VC table entry number,
It sends the data value to the VC table 6 and requests the data value stored in the pointer field 61 to be read. VC table 6
, Outputs the data value stored in the pointer field 61 in response to the pointer read request. The pointer read circuit 3 receives the data value of the pointer,
It is passed to the table search control circuit 1. The VC table search control circuit 1 passes the data value of the pointer, and ends the search.

As described above, the VC table search for ATM cell reception does not use the conventional search table 12 in which entries are prepared corresponding to all the data values of VPI / VCI. Of the ATM cell header 812.
Since the VC table 6 is searched by comparing it with the data value of I, it is possible to reduce the circuit scale without requiring much memory.

Next, the reception ATM cell processing device 8 using the VC table cache will be described. FIG.
FIG. 2 is a configuration diagram of a VC table and a VC table cache part in an example in which a VC table cache is used in the reception ATM cell processing circuit shown in FIG. 1. Referring to FIG. 2, the VC table cache 7 as an example of the reception ATM cell processing circuit has one bank of entries, and each entry has a VPI / VCI 71, a VC table entry number 72, and a priority 73 field. , The entry in the VC table 6 includes the VPI / VCI field 62 from the hit entry in the VC table 6.
Is copied, and the number of the entry is stored.

As the priority, values from 1 to M are assigned as numbers in order from the most recently hit entry. Here, as for the priority, 1 is the highest and M is the lowest. In the case of this configuration, the bank of the VC table cache 7 is first searched. When an entry of the priority L in the VC table cache 7 is hit, the priority of the entry becomes 1, and the priority of the entry whose priority is 1 to L-1 is 2 to L. Be changed.

Further, the VC table entry number 72 is read from the hit VC table cache 7 and passed to the VC table search control circuit 1 in FIG. The VC table search control circuit 1 performs an operation of reading the pointer data stored in the VC table 6 based on the VC table entry number. When an entry in the VC table 6 is hit, the data content stored in the VPI / VCI field 62 of the hit entry is stored in the entry of the priority M in the VC table cache 7 together with the number of the entry. Entry priority is 1
Is changed to The priority field of the other entries in the VC table cache 7 is incremented by one, and the fields from 1 to M-1 are changed from 2 to M, respectively.

Other operations are the same as the configuration without the VC table cache. In normal communication, the same VPI / V
It is considered that the ATM cell 81 having the data value of CI is often received continuously. Therefore, in normal reception,
Since there is a high possibility of hitting the data stored in the entry in the cache, if the cache bank is searched first, the average VC table search time can be made faster than when the cache is not used. It becomes possible.

The VC table 6 is divided into banks without using the conventional search table 12 in which all the data values of the VPI / VCI are prepared in the entries, and the data values of the VPI / VCI are sequentially determined for each bank. By configuring the receiving ATM cell processing device 8 by combining the comparing method and the above-described method using the VC table cache, the circuit scale can be reduced, and the average search speed can be reduced. Can also be improved.

[0024]

The VP included in the header of the received ATM cell
The data value of the I / VCI is not used in the conventional search table in which all the data values of the VPI / VCI are prepared in the entry. The scale of the memory used for preparing the table is obtained by outputting the data to the comparison circuit, further dividing the VC table into banks, and simultaneously comparing the VPI / VCI data values sequentially for each bank. And the size of the circuit associated therewith can be reduced. In addition to the above, by using a configuration using a VC table cache, it is possible to improve the average search speed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a processing portion including a VC table search circuit of a reception ATM cell processing device according to an embodiment of the present invention.

FIG. 2 is a configuration diagram showing an example of using a cache in a VC table of the reception ATM cell processing device shown in FIG. 1;

FIG. 3 shows a reception ATM as an example of a conventional reception ATM processing device.
It is the schematic which shows the processing means of a cell, and the flow of the operation.

FIG. 4 is a cell configuration diagram showing a bit sequence for each byte of a conventionally used ATM cell.

FIG. 5 is a data configuration diagram showing a bit string of a data value of VPI / VCI conventionally used.

FIG. 6 is a table configuration diagram showing an example of a search table used in a conventional reception ATM processing device.

[Explanation of symbols]

1 VC table search control circuit 2 VPI / VCI comparison circuit 3 Pointer reading circuit 4 VPI / VC
I register, 5 ... selector, 6 ... VC table, 7 ... V
C table cache, 8 ... received ATM cell processing device,
9: Main memory, 11: VPI / VCI bit string,
12 ... search table, 61 ... pointer field, 62
... VPI / VCI field, 63 ... other fields, 71 ... VPI / VCI, 72 ... VC table entry number, 73 ... priority, 81 ... ATM cell, 82 ... receive cell FIFO, 91 ... receive buffer, 92 ... payload storage Start address, 111 ... VCI, 112 ... VP
I, 121 ... VC table pointer, 811 ... Payload, 812 ... ATM cell header.

Claims (3)

[Claims] 1. A VC table composed of entries each having at least a VPI / VCI field and a pointer field, a selector for selecting and outputting data stored in an entry of the VC table, and a selector read from a received ATM cell header. A VPI / VCI register for holding the VPI / VCI data, a VPI / VCI comparison circuit for comparing the output data of the selector and the VPI / VCI register, and a data stored in a pointer field in an entry of the VC table. A receiving AT comprising a pointer reading circuit for reading, and a VC table search control circuit for controlling the search of the VC table;
An M-cell processing control device, wherein the selector comprises:
Only the data stored in the VPI / VCI field in the entry of the C table is output to the VPI / VCI comparison circuit.
/ VCI sends data designating an entry in the VC table storing matching data from the comparison result to the pointer reading circuit, and the pointer reading circuit sends the designated data from the VC table search control circuit. A receiving ATM cell processing control device for reading pointer data stored in a pointer field in an entry of the VC table. 2. The VC table is divided into banks including a plurality of entries, and the VC table search control circuit outputs data designating the bank of the VC table, and the selector controls the VC table search control. A bank designated by a circuit output is selected, and data stored in VPI / VCI fields in entries of all VC tables in the selected bank are simultaneously output to the VPI / VCI comparison circuit. 2. The receiving ATM cell processing control device according to claim 1, wherein: 3. A means having a VC table cache in the VC table, and copying data stored in a hit entry into the VC table cache;
3. The received ATM cell processing device according to claim 1, further comprising means for changing the priority of data stored in each entry of the C table cache.