JPH05199215A - Frame synchronization reinforcing circuit - Google Patents

Abstract

PURPOSE:To obtain the frame synchronization reinforcing circuit, which can be economically and exactly operated even for a pay broadcast having independent data, by adding a strong synchronization protecting circuit to the external part of a conventional PCM decoder. CONSTITUTION:A bit stream inputted from an input terminal 11 is inputted to a synchronization protecting circuit 1, and the circuit 1 checks a frame synchronizing pattern for each frame by a synchronizing detection timing signal FD, executes a front protecting operation having a prescribed front protect number M, detects the frame synchronizing pattern, generates a reset signal RS at this detection timing, resets a timing generation circuit 3 and establishes new frame synchronization. Synchronously to the frame synchronization, the circuit 3 transmits a frame synchronizing pulse generation timing signal FT to a frame synchronizing pulse generation circuit 5. The circuit 5 generates a frame synchronizing pulse PS and transmits it to a switch circuit 7. The circuit 7 changes over a switch while defining a frame synchronizing gate signal FG as a control input, changes over the switch and transmits the bit stream to a PCM decoder 105.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to P in satellite broadcasting and the like.
The present invention relates to a frame synchronization enhancing circuit that enhances a frame synchronization protection function of a voice decoder that receives and decodes a CM voice signal.

[0002]

2. Description of the Related Art When voice data and non-voice data, that is, independent data are framed and transmitted as in the case of PCM voice broadcasting in satellite broadcasting, the receiver side uses bit data as a countermeasure against errors in the transmission path. It is generally practiced to restore the original frame after performing interleaving and error correction processing.

FIG. 7 is a diagram showing the circuit configuration of a conventional pay broadcast PCM audio decoder generally used in conventional satellite broadcasting. In the figure, a bit stream, that is, a data string after QPSK demodulation is input terminal 8
It is input to the PCM decoder 105 via 07 and is supplied to the synchronization detection / BCH correction circuit unit 810. This circuit unit 810 detects frame synchronization, frame synchronization protection, and BC.
After H-correction processing is applied to the bit stream, the bit stream is supplied to the pay broadcast descramble circuit 704 as frame data. The data descrambled by the pay-broadcasting descramble circuit 704 is supplied to the audio data processing circuit unit 806 of the PCM decoder 105, where it is subjected to processing such as interpolation and time axis expansion, and then audio data from the output terminal 808. Is output as.

FIG. 8 shows the PCM decoder 105 shown in FIG.
9 is a block diagram showing in detail the circuit configuration of a synchronization detection / BCH correction circuit unit 810 of FIG. In the figure, the input terminal 80
The bit stream input from 7 is the synchronization protection circuit 8
01, the frame synchronization signal is detected, and synchronization protection processing is performed. The synchronization protection circuit 801 performs functions such as synchronization protection processing together with the timing circuit 802.

Then, the following processing is performed according to the timing of the frame established by the synchronization protection circuit 801. That is, in the next descramble circuit 803, the scrambling applied in frame synchronization for spread spectrum is descrambling, the bit deinterleaver 804 restores the data sequence to the original frame order, and the BCH correction circuit 805 generates the data in the transmission line. The error is corrected, and the frame data which is the BCH-corrected data sequence is output from the output terminal 809 according to the original frame order, and is supplied to the pay broadcast descramble circuit 704 shown in FIG.
This frame data includes audio data and independent data used in data broadcasting, pay broadcasting, and the like.

The frame data output from the BCH correction circuit 805 is supplied to the pay data processing circuit 806, the voice data in the frame data is subjected to interpolation processing, time axis expansion processing, etc., and output from the output terminal 808. It is output as voice data.

In the case of normal free broadcasting, the output terminal 80
The frame data after the BCH correction process outputted from No. 9 is not used, and the PCM decoder alone obtains the audio data output. On the other hand, in the case of pay broadcasting, FIG.
As shown in, the pay broadcasting descrambling circuit 704 descrambles the descrambled data by using the descramble information superimposed on the independent data part of the data string after the BCH correction processing, and PCM
It is returned to the decoder 105. PCM decoder 105
Performs processing such as interpolation on the descrambled data, and outputs audio data from the output terminal 808.

By the way, the PCM decoder 105 is developed for free broadcasting, and the synchronization protection capability is often designed so that the synchronization limit is about C / N = 4 to 5 dB. This is sufficient for receiving PCM voice in free broadcasting, and the frame synchronization forward protection number N of the synchronization protection circuit 801 shown in FIG. ing.

The pay broadcast PCM audio decoder shown in FIG. 7 includes a pay broadcast descramble circuit 704 for handling independent data. Here, the information for descrambling is extracted from the independent data, and the decryption cycle is set to a minimum of 1 second.
If the information for descrambling cannot be extracted, the descrambling cannot be performed normally for at least the next 1 second. Therefore, when a pay broadcast channel is selected in a radio wave condition where sound is heard intermittently during free broadcast, sound that is hardly descrambled, that is, noise is heard or muted. The inaudible state will continue. That is, normal sound cannot be heard even intermittently. Further, since the descramble information of the video is also extracted from the independent data, the descramble operation cannot be performed continuously in the radio wave condition described above.

[0010]

[Problems to be Solved by the Invention] In free broadcasting,
The broadcast content can be understood even with C / N = 4 to 5 dB, whereas in the pay broadcast using independent data, C / N = 4 despite using the same PCM decoder.
In the state of ~ 5 dB, the broadcast contents cannot be understood at all. In other words, there is a problem that the service limit of broadcasting becomes worse in pay broadcasting.

For these reasons, receivers handling independent data are generally required to have high synchronization protection capability. For this reason, in a pay broadcast decoder, a PCM decoder having a high synchronization protection capability must be newly designed, but this causes a problem of an increase in cost of the pay broadcast decoder.

The present invention has been made in view of the above,
The purpose is to provide a frame synchronization enhancement circuit that can operate economically and accurately even for pay broadcasting having independent data by adding a strong synchronization protection circuit to the outside of the conventional PCM decoder. To do.

[0013]

To achieve the above object, the frame synchronization enhancing circuit of the present invention is a frame synchronization enhancing circuit for enhancing the frame synchronization function of an audio decoder for receiving and decoding a PCM audio signal. Receiving a bit stream input to the audio decoder, extracting a frame synchronization signal, and applying a frame synchronization signal to the frame synchronization signal, the frame synchronization protection being stronger than the frame synchronization protection function of the audio decoder. A frame that outputs and outputs a frame synchronization gate signal synchronized with the frame synchronization signal, and a frame that is controlled by the frame synchronization gate signal and outputs the frame synchronization signal in the bitstream from the synchronization protection unit. The gist is to have a replacement means for replacing with a synchronization signal.

[0014]

In the frame synchronization enhancing circuit of the present invention, the synchronization protection means and the replacement means are provided on the front side of the audio decoder.
A frame synchronization in which a bit stream input to an audio decoder is supplied to a synchronization protection unit to extract a frame synchronization signal, and the frame synchronization signal is subjected to stronger frame synchronization protection than the frame synchronization protection function of the audio decoder. Outputs a signal, outputs a frame sync gate signal synchronized with the frame sync signal, and controls the frame sync signal in the bitstream to replace the frame sync signal with the frame sync signal output from the sync protection means. is doing.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a circuit configuration of a frame synchronization enhancing circuit according to an embodiment of the present invention. The frame synchronization strengthening circuit shown in the figure has a frame synchronization protection circuit unit 10 added to the front side of the conventional PCM decoder 105 described in FIG. The synchronization protection function is stronger than the protection number N = 6, for example, the forward protection number N = 20.

The frame synchronization protection circuit section 10 supplies the bit stream as shown in FIG. 2A input from the input terminal 11 to the synchronization protection circuit 1, whereby the frame synchronization of the bit stream is strongly synchronized. Established with protection. That is, the synchronization protection circuit 1 has the input terminal 1
A 16-bit frame synchronization pattern as shown in FIG. 2A is detected from the bit stream input from 1, the reset signal RS is generated at this detection timing, and the timing generation circuit 3 is reset. A synchronization detection timing signal FD, which is a timing signal for checking whether or not a frame synchronization pattern exists at the same position for each frame, is returned to the synchronization protection circuit 1. Although FIG. 2 shows the data format in the MTSC satellite broadcasting, one frame is composed of 2048 bits, and the first 16 bits of the frame is a frame synchronization pulse.

The synchronization protection circuit 1 checks the frame synchronization pattern for each frame by the synchronization detection timing signal FD and can detect the frame synchronization pattern continuously (M + 1) times for a predetermined forward protection number M, for example M = 20. When there is not, the forward protection operation of performing the re-detection operation is performed. That is, without using the synchronization detection timing signal FD, a bit string that matches the frame synchronization pattern in the bit stream is searched for, and at the time of searching, the timing generation circuit 3 is generated by the reset signal RS.
Is reset and a new frame synchronization is established. The larger the front protection number M is, the stronger the protection ability is. Therefore, it is determined as necessary.

The timing generation circuit 3 generates the frame synchronization pulse generation timing signal FT at the timing synchronized with the frame synchronization established as described above, and supplies it to the frame synchronization pulse generation circuit 5. The frame synchronization pulse generation circuit 5 generates a frame synchronization pulse FS as shown in FIG. 2C at the position of frame synchronization in the bit stream, and supplies the frame synchronization pulse FS to the other input of the switch circuit 7. To do. In addition, in (c) of FIG.
The original frame synchronization pulses S1 and S shown in FIG.
2, ... S16 is underlined below each letter S of the frame sync pulse in order to represent the correct frame sync pulse FS which has been subjected to the sync protection processing of the forward protection number M in the frame sync protection circuit unit 10. Is shown.

Further, the timing generation circuit 3 is shown in FIG.
A frame synchronization gate signal FG as shown in (b) is generated in synchronization with the frame synchronization pattern, and this frame synchronization gate signal FG is supplied as a control input of the switch circuit 7.

The switch circuit 7 is a timing generation circuit 3
When the frame sync gate signal FG from the above is supplied as a control input, the correct frame sync pulse FS, which is reinforced to the forward protection number M from the frame sync pulse generating circuit 5 supplied to the other input, is output. The switch is switched, and the frame synchronization pulse FS is used for (a) in FIG.
The original frame sync pulse shown in FIG. 2 is replaced, and the bit stream in which the frame sync pulse is replaced is shown in FIG.
Is output and supplied to the PCM decoder 105.

The bit stream subjected to the replacement operation as described above has the correct frame synchronization established unless the synchronization protection circuit 1 having a sufficiently strong synchronization protection capability such as the forward protection number M = 20 is in the synchronization error state. It has a frame synchronization pattern. Therefore, the PCM decoder 105
As long as the synchronization protection circuit 1 does not enter the synchronization error state, the established frame synchronization can be established.

FIG. 3 is a block diagram showing a circuit configuration of a frame synchronization enhancing circuit according to another embodiment of the present invention.
The frame synchronization strengthening circuit shown in the figure is intended to prevent malfunction of the synchronization error state in the embodiment shown in FIG. 1, that is, when the synchronization protection circuit 1 enters the synchronization error state in the embodiment of FIG. There is a case where frame synchronization is established by a false frame synchronization pattern without generating a synchronization error signal and a malfunction occurs, but the frame synchronization enhancement circuit shown in FIG. 3 is intended to prevent such a malfunction. ..

More specifically, in the embodiment shown in FIG. 1, the timing generation circuit 3 is not reset when the synchronization protection circuit 1 enters a synchronization error state in an empty channel where broadcasting is not serviced. The circuit 3 and the frame synchronization pulse generation circuit 5 are in the free-run state. Therefore, even though the frame synchronization is not established, the frame synchronization pulse FS
Since the frame synchronization gate signal FG is output, the replacement of the frame synchronization pulse in the frame synchronization described above is performed even in the synchronization error state. As a result, the conventional PCM decoder 105 establishes the frame synchronization by the frame synchronization pulse replaced in this synchronization error state, that is, the false frame synchronization pulse, so that the synchronization error signal is output from the synchronization protection circuit 801 as shown in FIG. No output.

The PCM decoder 105 shown in FIG. 8 uses a synchronization error signal to perform mute processing of voice, pre-state protection of a flag (control bit) of modes such as stereo and monaural, and noise at the time of synchronization error. The occurrence is suppressed. Therefore, when selecting an empty channel, the conventional P
The CM decoder 105 establishes frame synchronization with a false synchronization frame pulse, does not enter into a synchronization error state, and malfunctions.

Therefore, the frame synchronization enhancing circuit shown in FIG. 3 uses the synchronization protection circuit 21 for generating the frame synchronization error signal FE instead of the synchronization protection circuit 1 in the embodiment shown in FIG. The arithmetic means 23 is used instead of 7, and the arithmetic means 23 receives the bit stream from the input terminal 11 at one input and the frame synchronization pulse FS from the frame synchronization pulse generation circuit 5 at the other input. , The frame sync error signal F from the sync protection circuit 21 to the control input
E and the frame synchronization gate signal FG from the timing generation circuit 3 are supplied. Other configurations are the same as those of the frame synchronization enhancing circuit shown in FIG.

Then, when the synchronization protection circuit 21 enters the synchronization error state and the frame synchronization error signal FE is input from the synchronization protection circuit 21 to the calculation means 23, the calculation means 23.
Stops the frame sync pulse replacement processing, or fixes the frame sync pulse of the bit stream supplied to the PCM decoder 105 to "1" or "0". By doing this,
Since a false frame sync pulse is not included in the bit stream input to the PCM decoder 105,
The decoder 105 also enters a synchronization error state, and audio mute processing and the like are appropriately performed.

4 to 6 are calculation means 23 shown in FIG.
3 is a circuit diagram showing various specific circuit configurations of FIG.

First, the arithmetic means 23 shown in FIG. 4 inputs the bit stream and the frame synchronization pulse FS from the input terminal 11 to both inputs of the switch circuit 31 and also a signal obtained by inverting the frame synchronization error signal FE by the inverter 33. The output of the AND circuit 32 to which the frame sync gate signal FG and the frame sync gate signal FG are input is supplied to the control input of the switch circuit 31, and the switch circuit 31 is operated when the frame sync error signal FE is at a high level.
Is controlled so as to output a bit stream from the input terminal 11, whereby the replacement of the frame sync pulse described above is stopped.

Further, the calculation means 23 shown in FIG.
The AND circuit 3 is connected to the other input of the switch circuit 31.
The output of 2 is connected, the frame synchronization pulse FS is supplied to one input of the AND circuit 32, the frame synchronization error signal FE inverted by the inverter 33 is supplied to the other input, and the control of the switch circuit 31 is further performed. The frame sync gate signal FG is supplied to the input, and when the frame sync error signal FE is at a high level, the input signal supplied to the other input of the switch circuit 31 is fixed to "0". As a result, a false frame sync pulse does not exist in one frame sync in the bit stream output from the switch circuit 31.

Further, the calculation means 23 shown in FIG.
The output of the OR circuit 34 is connected to the other input of the switch circuit 31, and the frame synchronization pulse F is connected to the input of the OR circuit 34.
When the frame synchronization error signal FE is at a high level, the input signal supplied to the other input of the switch circuit 31 is fixed to "1" when S and the frame synchronization error signal FE are input. As a result, a false frame sync pulse does not exist in one frame sync in the bit stream output from the switch circuit 31.

The arithmetic means 23 shown in FIG. 6A connects the output of the switch circuit 31 to one input of the AND circuit 32, and the other input of the AND circuit 32 via the inverter 33 through a frame synchronization error. The signal FE is input, and when the frame synchronization error signal FE is at a high level, all bit streams output from the AND circuit 32 are fixed to "0". There is no false frame sync pulse in one frame sync.

Further, the calculation means 23 shown in FIG.
The output of the switch circuit 31 is configured to explain one input of the OR circuit 34 and to input the frame synchronization error signal FE to the other input of the OR circuit 34, and the frame synchronization error signal FE is high. In the case of the level, all bit streams output from the OR circuit 34 are fixed to "1" so that no false frame sync pulse exists in the output bit stream in one frame sync. ..

[0034]

As described above, according to the present invention,
A synchronization protection unit and a replacement unit are provided on the front side of the audio decoder, the bit stream input to the audio decoder is supplied to the synchronization protection unit, and a frame synchronization signal is extracted.
In the bit stream, the frame sync signal that is stronger than the frame sync protection function of the audio decoder for the frame sync signal is output, and the frame sync gate signal that is synchronized with the frame sync signal is output. Since the frame synchronization gate signal is controlled so that the frame synchronization signal output from the synchronization protection means is replaced by the frame synchronization signal of
The synchronization protection function can be economically enhanced by simply adding a circuit for enhancing the synchronization protection to the front side of the conventional audio decoder without developing a CM decoder, and can be used for a data receiver that handles data. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a circuit configuration of a frame synchronization enhancing circuit according to an embodiment of the present invention.

FIG. 2 is a timing diagram showing an operation of the frame synchronization enhancing circuit shown in FIG.

FIG. 3 is a block diagram showing a circuit configuration of a frame synchronization enhancing circuit according to another embodiment of the present invention.

FIG. 4 is a specific circuit diagram of an arithmetic means used in the frame synchronization enhancing circuit shown in FIG.

5 is another specific circuit diagram of the calculating means used in the frame synchronization enhancing circuit shown in FIG.

FIG. 6 is another specific circuit diagram of the calculating means used in the frame synchronization enhancing circuit shown in FIG.

FIG. 7 is a block diagram of a conventional pay broadcast audio decoder.

8 is a PC used in the audio decoder shown in FIG.
It is a block diagram which shows the detailed structure of an M decoder.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 synchronization protection circuit 3 timing generation circuit 5 frame synchronization pulse generation circuit 7 switch circuit 23 computing means 105 PCM decoder

Claims (2)

[Claims] 1. A frame synchronization enhancing circuit for enhancing a frame synchronization function of an audio decoder for receiving and decoding a PCM audio signal, wherein a frame synchronization signal is extracted by receiving a bit stream input to the audio decoder. Then, the frame synchronization signal that is stronger than the frame synchronization protection function of the audio decoder with respect to the frame synchronization signal is output, and the frame synchronization gate signal that is synchronized with the frame synchronization signal is output. A frame synchronization strengthening circuit, comprising: means for switching the frame synchronization signal controlled by the frame synchronization gate signal and replacing the frame synchronization signal in the bitstream with the frame synchronization signal output from the synchronization protection means. 2. The synchronization protection means has means for generating a synchronization error signal when the synchronization error state occurs, and suspends the replacement by the replacement means based on the synchronization error signal and the frame synchronization gate signal. 2. The frame synchronization strengthening circuit according to claim 1, further comprising means for setting a signal of at least a portion corresponding to the frame synchronization signal in the bit stream to a predetermined signal other than the frame synchronization signal.