JPH05236030A - Line quality monitor circuit - Google Patents

Abstract

PURPOSE:To improve a line fault detection time by detecting a parity of a reception signal, applying 1/N frequency division to a parity noncoincident signal, comparing N sets of frequency division signal intervals for a prescribed time, and monitoring the line quality for each parity noncoincident signal. CONSTITUTION:A reception processing unit 11 receives a demodulated digital multiplex signal 101 and outputs a parity noncoincident signal 102 and a clock signal 103 with a prescribed parity detection means. The signal 102 is given to a 1/N frequency divider circuit 12 and the signal 103 is given to N-sets of clock signal counter circuits 13. The circuit 12 receiving the signal 102 outputs N-sets of frequency division signals 104 and they are inputted to the N-sets of the circuits 13 as the control signals. The circuit 13 uses the signal 104 as the control signal to count a prescribed number of clock signals. N-sets of the count results 105 from the circuits 13 are ORed by an OR circuit 14, from which line changeover information 106 is outputted as line quality information. Furthermore, the results 105 are ANDed by an AND circuit 15, from which line switch-back information 107 is outputted as the line quality information.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to communication line quality monitoring means. In particular, it relates to a line quality monitoring means for improving the line failure detection time in a digital wireless transmission device.

[0002]

2. Description of the Related Art If a received signal is distorted due to fading or the like in a digital radio transmission system, inter-code interference occurs and the code error rate deteriorates. Therefore, a line affected by fading is switched to a protection line without interruption. A method of relieving line quality deterioration is often performed. FIG. 2 is a block diagram showing an example of a line quality monitoring circuit that outputs line quality information used in a conventional switching control unit. Received signal processor 21
Receives the demodulated digital multiplexed signal 201, has a predetermined parity detecting means, and receives the parity mismatch signal 20.
2 and a parity match signal 203 are output. The parity mismatch signal counting circuit 22 and the parity matching signal 203 are input to the matching signal counting circuit 23, respectively. The mismatch signal counting circuit 22 and the match signal counting circuit 23 form a competitive counting system. (For example, IEICE Transactions '73
/ 1 Vol. 56 "Invention by design method of frame synchronization protection circuit") A conventional line quality monitoring circuit counts a predetermined coincidence signal and a non-coincidence signal for a code error caused by fading or the like generated in a digital radio transmission line, and encodes the code. Detect the error rate. That is, when the code error rate generated on the transmission line is deteriorated below a predetermined error rate, the mismatch signal counting circuit 22 causes the match signal counting circuit 23 to
The line switching information 205 that is counted earlier than the line quality information is output. Further, when the code error rate generated on the transmission path becomes better than a predetermined error rate, the coincidence signal counting circuit 23 is counted before the non-coincidence signal counting circuit 22 to restore the line as the line quality information. The information 206 is output. Here, the error rate and accuracy to be detected are determined by the number and ratio of the counts of the coincidence signal counting circuit 22 and the non-coincidence signal counting circuit 23.

Next, the timing at which the line quality information is generated in the conventional line quality monitoring circuit will be described. Figure 4
In the conventional line quality monitoring circuit match signal, mismatch signal,
The timing chart of line switching information and line switching back information is shown. The code error rate (Pe) generated on the transmission line is X
When the error rate is lower than the predetermined error rate (P) at the time point, the line switching information 205 indicates that the mismatch signal 202 is reached after the X time point.
When a predetermined number (N) is counted, it is output at time A. However, the coincidence signal 203 is counted, and the line switchback signal 2 is output immediately before the line switching information is output (at the time B ').
When 06 is output, the non-coincidence signal counting circuit is returned to the initial value and again counts N coincidence signals, and outputs the line switching information at time B.

[0004]

In such a conventional example, when the line quality of the digital radio transmission line reaches a predetermined error rate, the detection time of the line switching information as the line quality information is calculated by the coincidence counting circuit. There is a drawback in that it may take about twice as long as the originally detectable time depending on the counting state.

The present invention eliminates such drawbacks, and an object of the present invention is to provide a line quality monitoring circuit having means for improving the line quality detection time.

[0006]

DISCLOSURE OF THE INVENTION The present invention is a line quality monitor provided with a reception signal processor provided in a reception station of a digital radio apparatus, which receives a digital multiplexed signal of an incoming reception signal and performs parity detection. In the circuit, the parity non-matching signal output from the received signal processor is input, the N frequency dividing circuit that divides the parity non-matching signal by N, and the frequency dividing signal output from the N frequency dividing circuit are input as control signals. And N clock signal counting circuits for counting the clock signals output from the received signal processor, an OR circuit for ORing the counting results output from the clock signal counting circuits, and the clock signal counting circuit. And a logical product circuit for logically multiplying the counting result output from the.

[0007]

The parity mismatch signal of the incoming digital multiplexed signal is divided by N, and each of the N divided signals thus divided is used as a control signal for the N clock counting circuits to count the clock signals. When it detects that the rising interval of one of the divided signals is less than the specified time, it outputs the line switching information from the OR circuit, and the rising interval of all the divided signals becomes more than the specified time. When this is detected, the logical product circuit outputs the line switchback information.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of this embodiment. As shown in FIG. 1, this embodiment is provided with a reception signal processor 11 which is provided in a reception station of a digital radio apparatus and which receives a digital multiplexed signal of an incoming reception signal and performs parity detection. As a feature of the invention, an N divider circuit 12 that receives a parity mismatch signal output from the reception signal processor 11 and divides the parity mismatch signal by N, and a component output from the N divider circuit 12. N clock signal counting circuits 13 for inputting frequency signals as control signals and counting clock signals output from the reception signal processor, and the clock signal counting circuit 1
OR circuit 14 for ORing the counting results output from 3
And a logical product circuit 15 that logically multiplies the counting results output from the clock signal counting circuit 13.

Next, the operation of this embodiment will be described. The reception signal processor 11 is a demodulated digital multiplexed signal 10
1 is input, a predetermined parity detection means is provided, and a parity mismatch signal 102 and a clock signal 103 are output. The parity mismatch signal 102 is input to the N frequency dividing circuit 12, and the clock signal 103 is input to the N clock signal counting circuits 13. The parity mismatch signal 102 is the N frequency dividing circuit 1
2 outputs N divided signals 104. The N divided signals 104 are respectively divided into N clock signal counting circuits 13
Is input as a control signal of. Here, N of the N divider circuit
Is a number equivalent to the number of counts of the mismatch signal counting circuit of the conventional line quality monitoring circuit, and has the same accuracy as the error detection of the conventional line quality monitoring circuit. A predetermined number of clock signals are counted using 104 as a control signal. The N counting results 105 from the clock signal counting circuit 13 are ORed by the OR circuit 14 and the line switching information 106 as the line quality information is output. Also, the N counting results 105 are logically ANDed by the AND circuit 15, and the line cutback information 10 as the line quality information is obtained.
7 is output.

Next, the operation of this embodiment will be described with reference to the timing chart of the mismatch signal and the line switching information of the line quality monitoring circuit shown in FIG. The code error rate (Pe) generated in the transmission line is a predetermined error rate (P) at the time point of X.
In the case of further deterioration, the non-matching signal 102 causes the output of the N frequency dividing circuit 12 to be output as N frequency-dividing signals 104 having a rising edge every time the non-matching signal occurs and every N non-matching signals. In the N clock signal counting circuits 13,
It is determined whether or not the clock signals are counted in a predetermined number or more within the rising interval of each of the N frequency-divided signals 104, and the count result 105 is output when the number is equal to or less than the predetermined number. The N counting results 105 are ORed, and when any of the N clock signal counting circuits counts a mismatch signal of a predetermined number or less, the line switching information 106 as the line quality information is output. In the case of the N frequency-divided signal 104 shown in FIG. 3, the number of clock signals within the N-2th frequency-divided signal interval is counted at the latest in the section in which the line error rate of the transmission path is P or more, so that the frequency is less than or equal to the predetermined number. It is determined that there is, the counting result 105 is output, and the line switching information 106 is output.
Is output. That is, the line switching information 106 is output at the time when N parity mismatch signals are counted (at time C) after time X at which the line quality is deteriorated. This corresponds to the time A when counting N disagreement signals shown in the conventional example. In addition, the bit error rate (P
When e) becomes better than the predetermined error rate (P) at the time point of Y, the clock signal counting circuit 13 causes the clock signal counting circuit 13 to output the predetermined number of clock signals within the rising interval of the N divided signal 104 of the mismatch signal. When the count results 105 are no longer output from all the clock signal counting circuits 13 as described above, the N count results 105 are logically ANDed and the line cutback information 107 as the line quality information is output at the time D. ..

[0011]

As described above, the present invention detects the parity of a digital multiplexed signal of an incoming received signal,
By dividing the parity mismatch signal by N, comparing the N frequency-divided signal intervals with a predetermined time, and monitoring the line quality for each parity mismatch signal, the effect of improving the line quality detection time is obtained.

Further, by using the line quality monitoring circuit of the present invention in the digital radio transmission device having the non-interruption standby switching means, the quality is deteriorated against the line quality deterioration due to a natural phenomenon such as fading occurring in the transmission line. Is detected promptly and switched to the protection line, there is an effect that the quality of the line can be maintained above a predetermined quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional example.

FIG. 3 is a timing chart showing the operation of the embodiment of the present invention.

FIG. 4 is a timing chart showing an operation of a conventional example.

[Explanation of symbols]

 11, 21 Received signal processor 12 N frequency divider circuit 13 Clock signal counting circuit 14 Logical sum circuit 15 Logical product circuit 22 Mismatch signal counting circuit 23 Match signal counting circuit

Claims (1)

[Claims] 1. A line quality monitoring circuit provided in a receiving station of a digital radio apparatus, comprising a received signal processor for inputting a digital multiplexed signal of an incoming received signal and performing parity detection, wherein: The parity non-matching signal output from is input, and the N frequency dividing circuit that divides the parity non-matching signal by N and the frequency dividing signal output from this N frequency dividing circuit are input as the control signal, N clock signal counting circuits for counting the output clock signals, an OR circuit for ORing the counting results output from the clock signal counting circuit, and a counting result output from the clock signal counting circuit. A line quality monitoring circuit comprising: a logical product circuit for multiplying.