JP3139778B2 - Paid broadcast mute signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[Object of the Invention]

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pay broadcast mute signal generating circuit for generating a mute signal for suppressing noise generated at the time of channel switching in a pay satellite broadcast pay receiver.

[0003]

2. Description of the Related Art FIG. 11 is a block diagram showing a configuration of a portion of a pay broadcast receiver, particularly related to audio reception. Also,
The pay-broadcast receiver in FIG. 1 shows a receiver of the NTSC system in Japan.

In FIG. 11, a first intermediate frequency signal supplied from a BS antenna (not shown) is input from an input terminal 403 to a BS tuner 401. Here, in the case of a program that is not a pay broadcast, that is, a program that is not scrambled, an analog audio output signal is output from the analog audio output terminal 405 of the BS tuner 401.
To view a pay broadcast, a pay decoder (BS decoder) 402 separate from the BS tuner 401 is required. A bit stream output from the BS tuner 401 is input to the pay decoder 402, and the bit stream Extract the information about the included subscription,
After descrambling, an analog audio output signal is output from the output terminal 404.

In FIG. 11, when the user wants to switch the channel, the viewer operates a switch such as a remote controller to input a channel switching request signal from the channel switching request generator 406 to the BS tuner 401. The channel is switched.

FIG. 12 is a block diagram showing the configuration of the audio receiving circuit of the BS tuner 401 shown in FIG.

In the case of a broadcast without scrambling, an audio signal can be reproduced by the audio receiving circuit of the BS tuner shown in FIG. Here, mute at the time of channel switching will be described. As mentioned above,
When the viewer operates a switch such as a remote controller to switch the channel, and a channel switching request signal is input from the channel switching request generating means 406 to the microcomputer 608 from the input terminal 610 in FIG. 12, as shown in FIG. , The microcomputer 608
Is used to selectively extract the signal of that channel.
Output a channel selection signal to the converter 601.
In this case, since the respective parts of the pay broadcast receiver are in a transitional state in which normal operation is not performed due to the lack of synchronization or the like, the microcomputer 608 mutes before outputting the channel selection signal. The signal is supplied to the analog mute circuit 607 to prevent noise from being output from the output terminal 612 due to this transient state.

[0008] As described above, when pay broadcasting is not received,
Output terminal 612 for analog audio output signal of BS tuner
(In FIG. 11, the output terminal 405 of the BS tuner 401)
Mute processing at the time of channel switching can be easily realized on the side of.

However, since a channel switching request signal cannot be directly obtained with respect to an analog audio output signal from an audio output terminal (FIG. 11) corresponding to pay broadcast reception, a pay charge having a configuration as shown in FIG. Since the broadcast receiver cannot directly obtain the channel switching request signal,
It is impossible to take a direct method as shown in FIG. 12 to realize mute processing at the time of channel switching.

FIG. 13 shows a BS tuner 4 similar to FIG.
01, BS tuner 501 corresponding to pay decoder 402 and channel switching request generating means 406, pay decoder 502 and channel switching request generating means 50
5 is a block diagram showing a circuit configuration of a pay broadcast receiver composed of 5 units. This circuit configuration allows the pay decoder 502 to perform a mute process at the time of channel switching in the BS tuner 501 by the above-described direct method. B
The configuration is such that a channel switching signal is output from the S tuner 501 to the pay decoder 502.

As described above, when the channel switching signal is BS
When supplied from the tuner 501 to the pay decoder 502, as described above, a mute signal is generated by using the channel switching request signal, thereby simplifying the mute processing so that noise is not generated at the time of channel switching. Can be done.

However, the conventional BS tuner does not have a channel switching signal output terminal as shown in FIG. 11, and therefore cannot perform the mute processing by such a simple method.

The background will be described with reference to FIG.
1 is provided in the BS tuner 401 shown in FIG.
It is necessary to send a channel selection signal to the BS 1 and a channel switching request signal to the BS tuner 401 is essential as a pay broadcast receiver.

More specifically, FIG. 14 is a basic block diagram showing a necessary configuration of a portion related to audio processing of a conventional pay decoder. In FIG.
The bit stream input from 505 is input to the PCM decoder 1501, and the frame is synchronized with the frame synchronization pattern. Since the bit stream is subjected to fixed scrambling for spread spectrum, the fixed scrambling is removed in synchronization with the extracted frame synchronization.

[0015] In addition, since bit interleaving is performed in a frame to cope with a burst error,
Deinterleave processing is performed. This means that a data sequence for one frame before deinterleaving is converted to a PCM decoder 1501.
A deinterleave process is realized by a method in which the data is directly written into a RAM within the RAM and read in an original order. That is, a BCH correction process is performed, and the data sequence after the BCH correction is output to the descrambling control circuit 1504. The descrambling control circuit 1504 extracts relevant information packet data for descrambling the scrambled broadcast multiplexed on the BCH-corrected data, decrypts the data, and converts the descrambled data sequence into a PCM decoder 1504.
Output to 1. The PCM decoder 1501 descrambles the BCH-corrected data (that is, scrambled for concealment) using this descrambled data sequence, performs range processing and the like, and converts the digital audio signal into a D / A & LPF. Output to the circuit 1502. Further, the signal is converted into an analog audio signal by the D / A & LPF circuit 1502, and is output from the output terminal 1506 through the analog mute circuit 1503.

A mute signal (mute signal B) at power-on is input from a terminal 1507 to an analog mute circuit 1503. Mute at power-on is generally realized by an analog mute circuit 1503. In other words, the analog mute circuit 1503 is necessary for power-up as described above, regardless of the channel switching mute processing. As described above, the conventional pay decoder 40 as shown in FIG.
2 does not require the second converter 601 as shown in FIG. 12, and it is difficult to consider that the processing at the time of channel switching is important and indispensable as a receiving system. It is considered that the channel switching signal has been overlooked in the development of.

However, as described above, mute processing at the time of channel switching is very important also in order to prevent a speaker, an amplifier and the like from being destroyed by a large noise generated at the time of channel switching.

Therefore, a BS tuner 40 as shown in FIG. 11 which is currently commercially available or is already used by viewers.
1 can be collected and modified to add a channel switching output terminal like the BS tuner 501 shown in FIG. 13 and then passed to the viewer together with the pay decoder 502, but this method is very costly. Takes and is not realistic. As another method, if the BS tuner 501 and the pay decoder 502 as shown in FIG. 13 are integrated, and it is assumed that pay broadcasting can be viewed only with such a pay broadcast receiver, the BS tuner 401 is already held. Some viewers have to purchase an expensive pay-broadcast receiver in which the BS tuner 501 and the pay decoder 502 are integrated, or have to rent it out from a broadcast station, which is a considerable burden. For this reason, there is a possibility that the pay broadcasting business itself cannot be established.

For the above reasons, it is necessary to realize the mute processing at the time of channel switching with the configuration as shown in FIG. 11, that is, with the configuration in which the channel switching signal is not output from the BS tuner 401.

By the way, there is a case where the receiving condition of the broadcast radio wave is deteriorated due to the weather or the like, that is, a low C / N state. In this case, if the degree of deterioration of the C / N falls below a certain point, a frame synchronization error occurs in the PCM decoder 605 shown in FIG. Also in this case, the output terminal 61
2. A frame synchronization error flag (mute signal) is converted to an analog mute circuit
To mute the audio signal. Also, at the time of channel switching, a frame synchronization error occurs because the head position of the frame of the bit stream input to the PCM decoder 605 changes.

FIG. 14 shows an example in which a mute process at the time of channel switching in the pay decoder 402 is performed using this. Directly, the analog mute circuit 1503 indicates the frame synchronization error flag as indicated by a two-dot chain line.
However, a channel switching signal is necessary for the descrambling control circuit 1504 as indicated by the solid line due to the unique situation of the pay decoder, and the signal is input to the descrambling control circuit 1504. This relates to the timing relationship between the related information packet data (hereinafter abbreviated as related information) for descrambling the scrambled broadcast multiplexed on the data stream after the BCH correction and the descrambling data stream.

FIG. 15 shows the timing of the mute operation at the time of channel switching. This timing includes the timing relationship between the related information and the descrambling data sequence. The related information is basically sent in units of a cycle T of the scramble timing. The cycle T of the scramble timing is set to, for example, 1 second. In a normal state, for example, the related information sent in the period C in FIG. 15 is used in the period D which is the next scramble timing cycle, and the initial value of pseudo random data generation and the like are set so that descrambling can be performed correctly. The descrambled data string is updated to the descramble control circuit 150.
4 is output.

However, the probability of correctly receiving related information during the period A in FIG. 15 including the transitional state at the time of channel switching is small. Therefore, it is necessary to mute the audio signal during the next period B. In addition, since the related information of the channel before the switching cannot be used in the period A, it is necessary to mute the period A. The mute signal A indicating the mute period must have a signal indicating the rising period. This is used as a channel switching signal.

FIG. 16 shows a circuit for generating the mute signal A. The channel switching signal is supplied to terminal 7
07 and is connected to the reset input of the counter 701. Further, a scramble timing signal is supplied from a terminal 704 to a clock input of the counter 701. The output Q of the counter 701 is input to the decoder 702. The decoder 702 outputs a high-level signal only when the output Q of the counter 701 is not "2". This output signal is provided to the count enable input of counter 701, which causes counter 701 to output Q
The counting operation is stopped when becomes "2". The output of the decoder 702 is output from a terminal 705 as a mute signal A. The timing of this occurrence is shown in FIG.

When a channel switching signal is input from the terminal 707 , the counter 701 is reset and its output Q becomes "0". Since this is Q ≠ 2, the output of the decoder 702, that is, the mute signal A goes high. Further, since the count enable input of the counter 701 is at a high level, the output Q is incremented by one at the next scramble timing. Further, at the next scramble timing, the output Q becomes “2”, the counter 701 stops, and the mute signal A goes low. As is clear from FIG. 17, unless the channel switching signal is supplied to the mute signal A generation circuit (included in the descrambling control circuit 1504 shown in FIG. 14) as soon as possible from the channel switching position, the mute signal A The occurrence will be delayed.

When the frame synchronization error flag of the PCM decoder 1501 is used as the channel switching signal as in the conventional case shown in FIG. 14, the mute signal A is generated for the number of frames n of the forward protection by the forward protection function. Although delayed, the generation timing of the mute signal A at the time of channel switching in FIG. 15 will now be described.

The channel selection signal from the microcomputer 608 of the BS tuner shown in FIG.
01 to perform channel switching. At this time, the signal is output from the terminal 611 of the BS tuner 401 and the terminal 1505 of the pay decoder 402 (FIG. 14).
The bit stream input to the channel changes from the previous channel with a high probability of the start position of the frame. Therefore, P
It takes n frames or more before the synchronization error flag is generated by the forward protection function having the frame protection forward protection number n of the CM decoder 1501 (FIG. 14). BCH during this time
The corrected data operates at the frame synchronization timing of the previous channel, and the data other than the data of one frame related to the bit deinterleaving is the data of the switching destination channel. It becomes noise. Also, during this period (until the frame synchronization error flag is output after the channel is switched), the mute signal A is not output.
6 will be mixed with noise.
In this situation, the mute signal A is supplied to the analog mute circuit 15.
The same applies to the case where the signal is input to the terminal 03 and the signal is input to the digital mute input terminal of the PCM decoder 1501 and digitally muted.

Further, conventionally, there is also a method of generating a mute signal using the frequency of occurrence of a BCH error. However, in such a method, a mute signal is generated with a delay, and noise at the time of channel switching is appropriately prevented. Can not.

[0029]

As described above,
With the conventional configuration, it is difficult to properly mute the noise at the time of channel switching, and this noise may cause discomfort to the viewer and may damage the speaker or the amplifier.

The present invention has been made in view of the above,
The purpose is to quickly detect channel switching information only from the bit stream that is the input data sequence, generate a mute signal to mute the noise at the time of channel switching, and mute the pay broadcast mute signal to prevent the occurrence of noise. It is to provide a generating circuit.

[Structure of the Invention]

[0032]

According to a first aspect of the present invention, there is provided a pay mute signal generating circuit for switching a channel from an input data sequence including a frame synchronization pattern received in a scrambled broadcast. A mute signal generation circuit for detecting a frame synchronization pattern from the input data sequence and having a forward protection function of a first predetermined number n of frames, A reference synchronization pattern generation circuit for generating a reference synchronization pattern in response to a frame synchronization signal detected by the synchronization processing circuit to detect frame synchronization; a frame synchronization pattern in the input data sequence and a reference synchronization pattern from the reference synchronization pattern generation circuit; Is a ratio that compares whether or not A determination circuit that compares a comparison result of the comparison circuit with a predetermined threshold value and generates a mute signal when the number of bits that do not match the comparison result is greater than a predetermined threshold value. It is the gist to have.

[0033]

According to the pay signal mute signal generation circuit of the present invention, the frame synchronization in the input data sequence specified by the reset signal and the frame clock signal output in response to the frame synchronization signal from the frame synchronization processing circuit is provided. The number of mismatched bits is counted by comparing the pattern with the reference synchronization pattern from the reference synchronization pattern generation circuit, and a mute signal is generated when the counted result is larger than a predetermined threshold value.

[0034]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a circuit configuration of a channel switching signal generation circuit used for a pay mute signal generation circuit according to an embodiment of the present invention.

In the figure, an input data string composed of a bit stream including a frame synchronization pattern is supplied to a terminal 10.
7 to n frames are input to a frame synchronization processing circuit 105 having a forward protection function. The frame synchronization signal detected by the frame synchronization processing circuit 105 is supplied to a timing generation circuit 106, and the timing generation circuit 106
Generates a reset signal and a frame clock signal which are frame synchronization signals.

The reset signal from the timing generation circuit 106 is supplied to the reference synchronization pattern generation circuit 101 and the mismatch bit number counter 102. The reference synchronization pattern generation circuit 101 generates a reference synchronization pattern serving as a correct reference at the timing of the reset signal supplied from the timing generation circuit 106,
This reference synchronization pattern is supplied to the mismatch bit number counter 102. Further, the timing generation circuit 1
The frame clock signal from 06 is supplied to the determination circuit 103 and the forward protection circuit 104.

The mismatch bit number counter 102 is reset by a reset signal from the timing generation circuit 106, and receives a frame synchronization pattern in an input data sequence supplied from a terminal 107 and a reference from the reference synchronization pattern generation circuit 101. The bit is compared with the synchronization pattern one bit at a time, and the number of bits that do not match is counted. Then, the count value of the number of mismatch bits is supplied to the determination circuit 103. The determination circuit 103 calculates the count value of the number of mismatch bits by the timing generation circuit 106.
Terminal 1 in advance with the timing of the frame clock signal from
If the count value of the number of mismatched bits is larger than the threshold value, the channel switching signal a is generated from the terminal 108.

FIG. 2 is a timing chart showing the operation of the circuit of FIG. 1 described above. As shown in FIG.
The frame synchronization pattern included in the input data sequence supplied to 7 is 16 bits consisting of S1, S2,..., S16. Then, in this 16-bit frame synchronization pattern, S4 ', S7', S9 ', S
The fourth, seventh, ninth, tenth, thirteenth, and sixteenth bits, which are indicated with "'" as in 10', S13 ', and S16', for a total of 6
If the bits are different from the correct frame synchronization pattern, that is, the reference synchronization pattern, the different bit signals are counted by the mismatch bit number counter 102. Then, this counting result is, as shown in FIG.
At the position of the frame clock signal output from the timing generation circuit 106, the frame clock signal is supplied to the determination circuit 103, and compared with a threshold value supplied from the terminal 110 and set to, for example, "4" at the determination circuit 103. In this case, the count value of the mismatch bit number counter 102 is “6”, which is larger than the threshold value “4”.
Outputs the channel switching signal a. This channel switching signal a is generated using the following conditions.

(1) The input data string after the channel switching has a very high probability that the head position of the frame is different from that before the channel switching.

(2) After the frame clock signal and the reset signal are switched by the forward protection function of the frame synchronization processing circuit, at least n frames are generated in synchronization with the frame of the channel before switching.

(3) There is a very high probability that the data sequence at the position of the frame synchronization pattern before the channel switching specified by the frame clock signal and the reset signal in the input data sequence after the channel switching is completely different from the frame synchronization pattern. , The probability that each bit matches each bit of the correct frame sync pattern is approximately 0.5.

(4) When the C / N ratio is reduced in transmission, an error occurs randomly in bit units.

Under these conditions, the channel switching signal a is output one to two frames after the channel is switched, and it is possible to mute at the time of the channel switching as compared with the conventional case where n or more frames are required. Become. By the way, among the conditions described above, (4) is low C / N
Means that a burst error does not occur at the time of, but in practice a burst error often occurs (the data of the audio frame is bit-interleaved in satellite broadcasting to deal with the burst error). . Therefore, in such a transmission system, no matter how high the threshold is, not only at the time of channel switching, but also at a low C / N ratio (however, no synchronization error occurs). The case where the signal a is output frequently occurs. In this case, when the channel switching signal a is used as the analog mute signal, there is not much problem. However, when the channel switching signal a is used as the channel switching signal, it is not possible to distinguish between the low C / N and the channel switching. Sometimes occurs.

The channel switching signal b output from the terminal 109 of the circuit shown in FIG. 1 is provided with the above-mentioned countermeasures by protecting the channel switching signal a in front. That is, the judgment circuit 10
3 from the front protection circuit 10
At (4), (m-1) frames are captured at the timing of the frame clock signal output from the timing generation circuit 106. Then, the channel switching signal b is output from the terminal 109 only when the channel switching signal a for m frames is continuously generated by the current channel switching signal a and the channel switching signal a for the past (m-1) frames. are doing.

The reason will be described with reference to the example of the front protection circuit shown in FIG. 3 and its output timing diagram shown in FIG. The frame synchronization pattern of the input data sequence before the channel is switched is between the frame clock signal and the reset signal as shown in FIG. 2, but at least n frames after the channel switching is performed by the frame synchronization processing circuit 105. , The frame clock signal and the reset signal remain synchronized with the frame synchronization pattern position of the channel before the channel switching. This n
During a frame, the probability that the input data sequence between the frame clock signal and the reset signal matches the frame synchronization pattern is (1/2) ^N, which is quite small. Note that N is the bit length of the frame synchronization pattern. Therefore, after switching channels, the channel switching signal a is output with high probability within one frame. This channel switching signal a is input from the terminal 304 in FIG. Then, the output of the D-type flip-flop 301 is further input to the D-type flip-flop 302, and each D-type flip-flop 30
Since the frame clock signal is input from the terminal 305 to the clock inputs 1 and 302, the D-type flip-flops 301 and 302 respectively transmit the previous and previous frames by 2 frames.
The channel switching signal a before the frame is held. The outputs of the D-type flip-flops 301 and 302 and the channel switching signal a are input to the three-input AND gate 303. When the channel switching signal a is output for three consecutive frames, the channel switching signal b is output from the terminal 306. Will be. That is,
The forward protection number m = 3. Therefore, the channel switching signal b is output within m frames from the channel switching position. By the way, when m> n, a new frame synchronization may be acquired at a position of n frames from the channel switching position, and the frame clock signal and the reset signal may be synchronized with this. As a result, the channel switching signal a becomes low level, and there is a possibility that the channel switching signal a does not occur. Therefore, it is necessary that m <n. Further, by setting the threshold value sufficiently large and adjusting m under the above-mentioned limit, the channel switching signal b can be generated only at the time of channel switching.

FIG. 5 is a block diagram showing the configuration of another embodiment of the present invention. In this embodiment, the channel switching detection circuit shown in FIG. 1 is replaced with the pay decoder 4 shown in FIG.
02.

In FIG. 5, a bit stream input from an input terminal 906 is supplied to a PCM decoder 901 to be synchronized with a frame by its frame synchronization pattern, and the bit stream is supplied to a channel switching mute signal generation circuit 905. Is done. Meanwhile, the frame synchronization processing circuit 105 and the timing generation circuit 106 shown in FIG. 1 may be provided in the PCM decoder 901 in FIG. 5, or may be provided in the channel switching mute signal generation circuit 905. Here, it is assumed that the frame synchronization processing circuit 105 and the timing generation circuit 106 are provided in the PCM decoder 901, and the other circuits shown in FIG. 1 are provided in the channel switching mute signal generation circuit 905. In this case, the frame clock signal and the reset signal in FIG. 1 are supplied from the PCM decoder 901 to the channel switching mute signal generation circuit 905, but the illustration of this relationship is omitted in FIG.

In FIG. 5, the channel switching signal a is output from the channel switching mute signal generation circuit 905. The channel switching signal a is supplied to the descrambling control circuit 904, As shown by, the analog mute circuit 903 is also supplied as a mute signal. At this time, the mute signal A is set to P as a digital mute signal.
It may be supplied to the CM decoder 901.

FIG. 6 is a timing chart showing the mute operation in the channel switching of the embodiment of FIG. P
The data sequence after the BCH correction due to the deinterleave processing in the CM decoder 901 is delayed by about one frame from the channel switching position of the bit stream. Accordingly, the switching 1 of the channel switching signal a and the analog audio output signal is also delayed by one frame or more, but the channel switching signal a and the mute signal A rise earlier and within one frame, so that the noise output can be muted.

However, in the embodiment shown in FIG. 5, as shown in FIG. 7, there is a possibility that the channel signal occurs frequently due to the burst error at the time of the low C / N, and the mute signal A is kept generated. Even when noise is momentarily mixed at such a low C / N, it is desirable that the content be heard without being masked by the mute signal.

FIG. 8 is a block diagram showing the configuration of still another embodiment of the present invention. In this embodiment, as described above, it is prevented that a channel signal occurs frequently due to a burst error at the time of a low C / N and the mute signal A is kept from being generated. In this embodiment, the channel shown in FIG. 1 is used as a mute signal C of the analog mute circuit 1203, and the channel switching signal b is used for channel switching.

FIG. 9 is a timing chart showing the mute operation at the time of channel switching in the embodiment of FIG. As shown in the figure, the channel switching signal b is delayed by (m-1) frames or more with respect to the channel switching position of the bit stream. Accordingly, since noise is output only with the mute signal A, the mute is performed by the mute signal C including the channel switching signal a.

FIG. 10 is a block diagram showing the configuration of another embodiment of the present invention. This embodiment uses PCM as a channel switching signal of the descrambling control circuit 1304.
1 uses the frame synchronization error flag of the decoder 1201 and the channel switching signal a of FIG. 1 as the mute signal C of the analog mute circuit 1203.

Also in this case, the generation of the mute signal A is delayed by (n-1) frames or more depending on the channel switching position of the bit stream.
Mute is required.

In each of the above-described embodiments, when the input is only a bit stream, a data clock recovery circuit is required. When a clock synchronized with the data is also input as a pair with the data train, the clock recovery circuit is not necessary. The channel switching signal can be used not only for muting audio but also for muting video.

[0057]

As described above, according to the present invention,
Channel from only the bit stream that is the input data sequence
Channel switching information is quickly detected and channel switching is performed.
Generates a mute signal to mute noise when
Providing a mute signal generation circuit for pay broadcasting that prevents generation
can do.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a circuit configuration of a channel switching signal generation circuit used in a pay broadcast mute signal generation circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart showing the operation of the circuit of FIG.

FIG. 3 is a circuit diagram showing an example of a forward protection circuit used in the circuit of FIG.

FIG. 4 is a timing chart showing an operation of the circuit of FIG. 3;

FIG. 5 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 6 is a timing chart showing a mute operation in channel switching of the embodiment of FIG.

FIG. 7 is a timing chart for explaining a state in which a channel signal frequently occurs due to a burst error at the time of low C / N and a mute signal A is kept generated in the embodiment of FIG. 5;

FIG. 8 is a block diagram showing a configuration of still another embodiment of the present invention.

FIG. 9 is a timing chart showing a mute operation at the time of channel switching in the embodiment of FIG. 8;

FIG. 10 is a block diagram showing a configuration of another embodiment of the present invention.

FIG. 11 is a block diagram showing a conventional configuration of a pay broadcast receiver, particularly a portion related to audio reception.

12 is a block diagram illustrating a configuration of an audio receiving circuit of a BS tuner used in the pay broadcast receiver illustrated in FIG. 11;

FIG. 13 is a block diagram showing a configuration of a portion related to audio reception in particular of the same pay broadcast receiver as shown in FIG. 11,
In this circuit, a channel switching signal that is not output from a normal BS tuner is output.

FIG. 14 is a basic block diagram showing a necessary configuration of a part related to audio processing of a pay decoder used in a conventional pay broadcast receiver.

FIG. 15 is a diagram illustrating a timing of a mute operation at the time of conventional channel switching.

FIG. 16 is a circuit diagram showing a configuration of a conventional circuit for generating a mute signal A.

FIG. 17 is a diagram showing the generation timing of a mute signal A in the circuit of FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 101 Reference synchronization pattern generation circuit 102 Unmatched bit number counter 103 Judgment circuit 104 Forward protection circuit 105 Frame synchronization processing circuit 106 Timing generation circuit

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04H 1/00 H04B 1/10 H04N 5/44 H04N 7/16

Claims (1)

(57) [Claims] 1. A mute signal generation circuit for detecting a channel switching time from an input data sequence including a frame synchronization pattern received in a scrambled broadcast and generating a mute signal, wherein the mute signal generation circuit detects a frame synchronization pattern from the input data sequence. A frame synchronization processing circuit having a forward protection function for a first predetermined number of frames n, a reference synchronization pattern generation circuit for generating a reference synchronization pattern in accordance with a frame synchronization signal detected by the frame synchronization processing circuit, A comparison circuit for comparing whether or not a frame synchronization pattern in the input data string matches a reference synchronization pattern from the reference synchronization pattern generation circuit for each bit; and a comparison result of the comparison circuit and a predetermined threshold. Value and compare
A judging circuit for generating a mute signal when the number of unmatched bits in the comparison result is greater than a predetermined threshold value.