JPH05198749A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05198749A JPH05198749A JP1019692A JP1019692A JPH05198749A JP H05198749 A JPH05198749 A JP H05198749A JP 1019692 A JP1019692 A JP 1019692A JP 1019692 A JP1019692 A JP 1019692A JP H05198749 A JPH05198749 A JP H05198749A
- Authority
- JP
- Japan
- Prior art keywords
- type impurity
- impurity layer
- layer
- resistance element
- resistance value
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に多結晶シリコン層で形成された抵抗素子に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a resistance element formed of a polycrystalline silicon layer.
【0002】[0002]
【従来の技術】図5に、半導体基板に形成された多結晶
シリコンを利用した従来の抵抗素子の構造断面図を示
す。2. Description of the Related Art FIG. 5 shows a structural cross-sectional view of a conventional resistance element using polycrystalline silicon formed on a semiconductor substrate.
【0003】図5は、半導体基板1上に、シリコン酸化
膜2が形成されており、その上部に、両端が電圧引出し
用のN型不純物層4で構成され、電圧引出し用のN型不
純物層4以外の領域は、P型不純物層(a)5で形成さ
れており、さらに上部に堆積された層間絶縁膜6を介
し、アルミ配線7が、形成された従来の抵抗素子を示
す。In FIG. 5, a silicon oxide film 2 is formed on a semiconductor substrate 1, both ends of which are composed of N-type impurity layers 4 for voltage extraction, and N-type impurity layers for voltage extraction are formed. Regions other than 4 are formed of the P-type impurity layer (a) 5, and a conventional resistance element in which an aluminum wiring 7 is formed via an interlayer insulating film 6 deposited on the upper portion is shown.
【0004】前記図4の抵抗素子は、アルミ配線7に印
加される電位差で2端子間を流れる電流を制御し、抵抗
として使用するものである。前述の2端子間を流れる電
流は、電圧引出し部のN型不純物層4とP型不純物層
(a)5のジャンクションを流れる逆方向電流によって
制限される。The resistance element shown in FIG. 4 controls a current flowing between two terminals by a potential difference applied to the aluminum wiring 7 and is used as a resistance. The above-described current flowing between the two terminals is limited by the reverse current flowing through the junction between the N-type impurity layer 4 and the P-type impurity layer (a) 5 in the voltage drawing portion.
【0005】図4の曲線(B)は、アルミ配線7に印加
される電位差を横軸にとり、そのときの抵抗値を縦軸に
とった、従来の抵抗値の、電位差による依存性を示した
ものである。The curve (B) in FIG. 4 shows the dependence of the conventional resistance value on the basis of the potential difference, with the potential difference applied to the aluminum wiring 7 on the horizontal axis and the resistance value at that time on the vertical axis. It is a thing.
【0006】[0006]
【発明が解決しようとする課題】従来の抵抗素子は、図
4の曲線(B)に示すように、電位差による抵抗値の依
存性が大きい。例えば、電位差が0〜5Vの範囲で、従
来の抵抗素子を使用した場合、0V付近の抵抗値と5V
付近の抵抗値が、大きく変動し広い範囲の電圧で一定の
抵抗値を得るとことが困難であるという問題点を有す
る。In the conventional resistance element, as shown by the curve (B) in FIG. 4, the resistance value greatly depends on the potential difference. For example, when a conventional resistance element is used in a potential difference of 0 to 5V, a resistance value near 0V and 5V
There is a problem that the resistance value in the vicinity varies greatly and it is difficult to obtain a constant resistance value in a wide range of voltage.
【0007】そこで、本発明はこのような課題を解決し
ようとするもので、その目的とするところは、電位差に
よる抵抗値の依存性の少ない抵抗素子を提供するところ
にある。Therefore, the present invention is intended to solve such a problem, and an object thereof is to provide a resistance element in which the resistance value is less dependent on the potential difference.
【0008】[0008]
【課題を解決するための手段】本発明の半導体装置は、
第1導電型領域の両側に第2導電型領域が形成された多
結晶シリコン層からなる抵抗素子を具備する半導体装置
において、前記多結晶シリコン内に順方向ダイオードと
逆方向ダイオードが対向する方向に複数個直列に配設さ
れたことを特徴とする。The semiconductor device of the present invention comprises:
In a semiconductor device having a resistance element made of a polycrystalline silicon layer in which a second conductivity type region is formed on both sides of a first conductivity type region, a forward diode and a reverse diode are opposed to each other in the polycrystalline silicon. It is characterized in that a plurality of them are arranged in series.
【0009】[0009]
【実施例】図1に、半導体基板に形成された多結晶シリ
コンを利用した本発明の抵抗素子の構造断面図を示す。1 is a structural sectional view of a resistance element of the present invention using polycrystalline silicon formed on a semiconductor substrate.
【0010】図1は、半導体基板1上に、シリコン酸化
膜2が形成されており、その上部に両端が電圧引出し用
のN型不純物層4で、前記電圧引出し用のN型不純物層
4以外の領域は、N型不純物層(a)9、N型不純物層
(b)10とP型不純物層(a)5とP型不純物層
(b)12、P型不純物層(c)13、で構成された多
結晶シリコンで形成され,更に上部に層間絶縁膜6を介
し、アルミ配線7が形成された、本実施例の抵抗素子を
示す。In FIG. 1, a silicon oxide film 2 is formed on a semiconductor substrate 1, and both ends of the silicon oxide film 2 are N-type impurity layers 4 for extracting voltage, except for the N-type impurity layer 4 for extracting voltage. The region of N-type impurity layer (a) 9, N-type impurity layer (b) 10, P-type impurity layer (a) 5, P-type impurity layer (b) 12 and P-type impurity layer (c) 13 A resistance element of the present embodiment is shown which is formed of polycrystalline silicon configured and further has an aluminum wiring 7 formed on the upper part thereof with an interlayer insulating film 6 interposed therebetween.
【0011】図2に、本実施例の抵抗素子の等価回路を
示す。本実施例の抵抗素子は、順方向のダイオードと逆
方向のダイオードで組み合わされた従来の抵抗素子が、
直列に3個接続されたものである。図1を使い説明する
と、電圧引き出し用のN型不純物層4とP型不純物層
(a)5で逆方向ダイオードを構成しており、さらにP
型不純物層(a)5とN型不純物層(a)9で順方向ダ
イオードを構成し、この2つのダイオードで1つの抵抗
素子を形成している。同様にN型不純物層(a)9とP
型不純物層(b)12、P型不純物層(b)12とN型
不純物層(b)10で1つの抵抗素子を1つの抵抗素子
を形成し、さらにN型不純物層(b)10とP型不純物
層(c)13、P型不純物層(c)13と電圧引き出し
用N型不純物層4で1つの抵抗素子を形成しており以上
3つの抵抗素子が直列に形成されている。FIG. 2 shows an equivalent circuit of the resistance element of this embodiment. The resistance element of the present embodiment is a conventional resistance element in which a forward diode and a reverse diode are combined,
Three are connected in series. Referring to FIG. 1, an N-type impurity layer 4 for extracting voltage and a P-type impurity layer (a) 5 form a reverse diode, and P
The type impurity layer (a) 5 and the N type impurity layer (a) 9 form a forward diode, and these two diodes form one resistance element. Similarly, the N-type impurity layer (a) 9 and P
One resistance element is formed by the type impurity layer (b) 12, the P type impurity layer (b) 12 and the N type impurity layer (b) 10, and the N type impurity layer (b) 10 and P The type impurity layer (c) 13, the P-type impurity layer (c) 13 and the voltage-drawing N-type impurity layer 4 form one resistance element, and the above three resistance elements are formed in series.
【0012】そのため本実施例の抵抗素子により得られ
る抵抗値は、従来の抵抗素子に与えた印加電圧の3分の
1の電圧に於ける抵抗値の3倍になる。図4の曲線
(A)は、アルミ配線7に印加される電位差を横軸にと
り、そのときの抵抗値を縦軸にとった、本実施例の抵抗
値の、電位差による依存性を示したものである。Therefore, the resistance value obtained by the resistance element of this embodiment is three times as large as the resistance value at a voltage which is one third of the applied voltage applied to the conventional resistance element. The curve (A) in FIG. 4 shows the dependence of the resistance value of this embodiment on the potential difference, in which the horizontal axis represents the potential difference applied to the aluminum wiring 7 and the vertical axis represents the resistance value at that time. Is.
【0013】図4の曲線(A)に示すように、本発明に
よる抵抗素子の抵抗値は、従来の抵抗素子に比べ印加電
圧による電圧依存性が少なくなっている。As shown by the curve (A) in FIG. 4, the resistance value of the resistance element according to the present invention has less voltage dependency due to the applied voltage than that of the conventional resistance element.
【0014】次に、本発明の半導体装置の製造方法一実
施例を図3(a)〜図3(f)にもとづき説明する。Next, one embodiment of a method for manufacturing a semiconductor device of the present invention will be described with reference to FIGS. 3 (a) to 3 (f).
【0015】図3(a)は、半導体基板1上に約100
0Å堆積されたシリコン酸化膜2上部に、多結晶シリコ
ン3を約1000∂形成した後前述のシリコン酸化膜3
をパターンニングしたものだある。FIG. 3A shows a semiconductor substrate 1 having about 100 layers.
After forming about 1000∂ of polycrystalline silicon 3 on the 0Å deposited silicon oxide film 2, the above-mentioned silicon oxide film 3 is formed.
Is a pattern.
【0016】図3(b)は、フォトリソグラフィーによ
りパターンニングを行いレジストマスク8をマスクとし
ボロンイオンを約20kevで5×1013〜1×1014
/cm2打ち込んで多結晶シリコン層3にP型不純物層
を形成したものである。In FIG. 3B, patterning is performed by photolithography, and boron ions are used at 5 × 10 13 to 1 × 10 14 at about 20 kev using the resist mask 8 as a mask.
P-type impurity layer is formed on the polycrystalline silicon layer 3 by implanting / cm 2 therein.
【0017】図3(C)は、前述の多結晶シリコン層3
上にフォトリソグラフィーによりパターンニングを行い
レジスト膜8をマスクとし、多結晶シリコン層3の両端
部に電圧引出し用のN型不純物層4と電圧引出し用のN
型不純物層4以外の領域にN型不純物層(a)9、N型
不純物層(b)10を、砒素イオンを約60kevで1
×1015〜5×1015/cm2打ち込むことにより形成
したものである。なお図中、P型不純物層(a)5、P
型不純物層(b)12、P型不純物層(c)13は、前
工程で打ち込まれたP型不純物領域のうちN型不純物を
打ち込まない多結晶シリコン3の領域である。FIG. 3C shows the above-mentioned polycrystalline silicon layer 3
Patterning is performed thereon by photolithography and the resist film 8 is used as a mask, and an N-type impurity layer 4 for voltage extraction and an N-type impurity layer for voltage extraction are provided at both ends of the polycrystalline silicon layer 3.
The N-type impurity layer (a) 9 and the N-type impurity layer (b) 10 are formed in a region other than the type impurity layer 4 and arsenic ions are set at about 60 kev.
It is formed by implanting × 10 15 to 5 × 10 15 / cm 2 . In the figure, P-type impurity layers (a) 5, P
The type impurity layer (b) 12 and the P type impurity layer (c) 13 are regions of the polycrystalline silicon 3 in which the N type impurity is not implanted among the P type impurity regions implanted in the previous process.
【0018】図3(d)は、化学的気相成長法によりシ
リコン酸膜化膜を層間絶縁膜6として約3000Å形成
した後、前述の層間絶縁膜6上に、本抵抗素子の引出し
電極としてアルミ配線7を形成したことにより得られる
本実施例の構造を示したものである。FIG. 3 (d) shows that a silicon oxide film is formed as an interlayer insulating film 6 by chemical vapor deposition to form about 3000 Å, and then it is used as a lead electrode of the present resistance element on the interlayer insulating film 6 described above. The structure of this embodiment obtained by forming the aluminum wiring 7 is shown.
【0019】本実施例に於いては第1導電層にN型不純
物層、第2導電層にP型不純物層を使用したが、第1導
電層にP型不純物、第2導電層にN型不純物層を使用す
る場合も適応できる。In this embodiment, the N-type impurity layer is used for the first conductive layer and the P-type impurity layer is used for the second conductive layer. It is also applicable when using an impurity layer.
【0020】[0020]
【発明の効果】本発明による抵抗抵抗素子は、順方向の
ダイオードと逆方向のダイオードが対向したを複数個接
続した構造にすることにより、2端子間の電位差による
抵抗値の変化が少ない良好な抵抗素子を得る。いままで
電圧依存性が強いために設計的に制限されていた従来の
抵抗素子の使用範囲が広がると言う多大の効果を有す
る。The resistance element according to the present invention has a structure in which a plurality of forward diodes and opposite diodes are connected to each other, so that the resistance value is less likely to change due to the potential difference between the two terminals. Get a resistance element. This has a great effect that the range of use of the conventional resistance element, which has been limited by design because of its strong voltage dependency, is expanded.
【図1】本発明の半導体装置の構造断面図を示す図であ
る。FIG. 1 is a diagram showing a structural cross-sectional view of a semiconductor device of the present invention.
【図2】本実施例の抵抗素子の等価回路を示す図であ
る。FIG. 2 is a diagram showing an equivalent circuit of a resistance element of the present embodiment.
【図3】(a)〜(d)は、本発明の半導体装置の製造
方法の一実施例を示す図である。3A to 3D are diagrams showing an embodiment of a method for manufacturing a semiconductor device of the present invention.
【図4】抵抗値の電圧依存性を示す図である。曲線
(A)は、従来の抵抗素子における抵抗値の電位差依存
性を示す図である。曲線(B)は、本発明の抵抗素子に
おける抵抗値の電位差依存性を示す図である。FIG. 4 is a diagram showing voltage dependence of resistance value. A curve (A) is a diagram showing the potential difference dependency of the resistance value in the conventional resistance element. A curve (B) is a diagram showing the potential difference dependence of the resistance value in the resistance element of the present invention.
【図5】従来の半導体装置の構造断面図を示す図であ
る。FIG. 5 is a diagram showing a structural cross-sectional view of a conventional semiconductor device.
1 半導体基板 2 シリコン酸化膜 3 多結晶シリコン層 4 電圧引出し用のN型不純物層 5 P型不純物層(a) 6 層間絶縁膜 7 アルミ配線 8 レジスト膜 9 N型不純物層(a) 10N型不純物層(b) 12P型不純物層(b) 13P型不純物層(c) 1 semiconductor substrate 2 silicon oxide film 3 polycrystalline silicon layer 4 N-type impurity layer for voltage extraction 5 P-type impurity layer (a) 6 interlayer insulating film 7 aluminum wiring 8 resist film 9 N-type impurity layer (a) 10 N-type impurity Layer (b) 12P-type impurity layer (b) 13P-type impurity layer (c)
───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.5 識別記号 庁内整理番号 FI 技術表示箇所 H01L 29/91 7735−4M H01L 21/88 N 8225−4M 29/91 K ─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. 5 Identification code Internal reference number FI Technical display location H01L 29/91 7735-4M H01L 21/88 N 8225-4M 29/91 K
Claims (1)
が形成された多結晶シリコン層からなる抵抗素子を具備
する半導体装置において、 前記多結晶シリコン内に順方向ダイオードと逆方向ダイ
オードが対向する方向に複数個直列に配設されたことを
特徴とする半導体装置。1. A semiconductor device comprising a resistance element made of a polycrystalline silicon layer in which a second conductivity type region is formed on both sides of a first conductivity type region, wherein a forward diode and a reverse diode are provided in the polycrystalline silicon. A plurality of semiconductor devices are arranged in series in opposite directions.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1019692A JPH05198749A (en) | 1992-01-23 | 1992-01-23 | Semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1019692A JPH05198749A (en) | 1992-01-23 | 1992-01-23 | Semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05198749A true JPH05198749A (en) | 1993-08-06 |
Family
ID=11743537
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1019692A Pending JPH05198749A (en) | 1992-01-23 | 1992-01-23 | Semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05198749A (en) |
-
1992
- 1992-01-23 JP JP1019692A patent/JPH05198749A/en active Pending
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