JPH0519333B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a data error detection circuit built into a signal processing circuit used in a compact disc (CD) playback device.

(b) Conventional technology A CD playback device creates 8-bit symbols from data read out from a disc in the form of an EFM signal and restores music signal data, but data errors occur in these symbols. Sometimes. This is caused by defects when pits are written on the disc, defects caused by scratches etc. that occur during handling of the disc, or defects caused by mechanical fluctuations or disturbances in the playback device. Therefore, in order to detect and correct data errors, a system called a cross-linterleaved Reed-Solomon code (CIRC) is used in CDs.

This method will be briefly explained. First, when recording data on a disk, 6 pieces of 16-bit music signal data for each of the right channel and left channel are converted into 8 bits each.
Divided into bit symbols, a total of 24 symbols are created. After being selectively delayed and recombined, they are based on Reed-Solomon coding.
Parity data Q ₀ , Q ₁ , Q ₂ , Q ₃ (8 bits each) of C ₂ is attached. Furthermore, these 28 symbols are
Parity data P ₀ , P ₁ , P ₂ , and P ₃ (each 8 bits) of C ₁ are similarly created and added based on the Reed-Solomon coding method, each delayed by a different time. Then, a total of 32 symbols are selectively delayed, among which parity data Q ₀ , Q ₁ , Q ₂ ,
_Q3 , _P0 , _P1 , _P2 , and _P3 are inverted to form a data group for writing, which is EFM (8-14 modulation) modulated and recorded on the disk together with a frame synchronization signal.

Also, when playing a disc, the read
Thirty-two 8-bit symbols are created from the EFM signal, and these are processed in the opposite way as they were recorded.
That is, 32 symbols are selectively delayed and parity data Q ₀ , Q ₁ , Q ₂ , Q ₃ and P ₀ , P ₁ , P ₂ ,
_P3 is inverted and _C1 decoded. In the _C1 decoding process, a syndrome is calculated based on each symbol, and error detection and error correction are performed from the calculated syndrome according to the Reed-Solomon coding method. Further, the 28 symbols subjected to _C1 decoding are each delayed for a different time and then subjected to _C2 decoding. Similarly, the _C2 decoding process is
A syndrome is calculated from each symbol, and error detection and error correction are performed based on the calculated syndrome according to the Reed and Solomon coding methods. and,
The 24 symbols after the _C2 decoding process are rearranged and selectively delayed, and then returned to the original music signal data.

The CD system using the cross-interleaved Reed-Solomon coding method was introduced in 1982.
It is described in detail on pages 103 to 110 of the ``Illustrated Compact Disc Reader'' (Ohmsha) published on November 25, 2017.

Conventionally, when detecting errors based on the Reed-Solomon coding method, syndromes are calculated according to the following equation.

S ₀ S ₁ S ₂ S ₃ = 1 α ³¹ α ⁶² α ⁹³ 1 α ³⁰ α ⁶⁰ α ⁹⁰ …… …… …… 1 α α ² α ³ 1 1 1 1D ₀ D ₁ 〓 D ₃₁ ……( 1) Note that α is the root of the 8th order primitive polynomial F(X)=X ⁸ +X ⁴ +X ³ +X ² +1.

As a result of the above calculation, the syndromes S ₀ , S ₁ , S ₂ , S ₃
If all are "0", it is determined that there is no error.

On the other hand, if there is an error only in the j-th data D _j , S ₁ ² = S ₀ · S ₂ , S ₂ ² = S ₁ · S ₃ S ₀ ≠ 0, S ₁ ≠ 0, S ₂ ≠ The error data position is determined by calculating _{S 1 /} S ₀ =α ^j and taking the logarithm thereof.

Moreover, if there is an error in data D _j and D _i , α ^j + α ⁱ = S ₁・S ₂ + S ₀・S ₃ /S ₁ ² +S ₀・S ₂ α ⁱ・α ^j = S ₂ ² +S ₁ ·S ₃ /S ₁ ² +S ₀ ·S ₂ Since 0≦j, j≦31, and j≠i hold, it is therefore determined that there is a double error when j and i are obtained. Furthermore, data errors E _j and E _i are determined by E _j E _i =1/α ^j +α ^j S ₁ +α ^j ·S ₀ S ₁ +α ^j S ₀ .

Regarding CD data error detection and correction using the above-mentioned Reed-Solomon coding method, please refer to Japanese Patent Application Laid-Open No. 1986-
It is described in detail in Publication No. 77529.

(C) Problems to be Solved by the Invention However, the circuit for detecting and correcting data errors described above requires a ROM for logarithmic conversion and a large number of multiplication/division circuits, and this is especially difficult when performing double error detection. In addition, since multiplication and division must be repeated, it takes time to detect errors and calculate error positions, and the number of timing signals required for calculations increases.

(d) Means for solving the problems The present invention has been made in view of the above-mentioned points, and it is possible to determine the syndrome S ₀ ,
S ₁ , S ₂ , S ₃ are calculated, and the syndrome S ₀ ,
Syndrome calculation means that divides S ₁ , S ₂ , S ₃ by 1, α, α ² , α ³ (α is the root of an 8th order primitive polynomial), and syndromes S ₀ , S ₁ , S ₂ , S ₃ are all an error zero detection means for detecting "0"; a counting means for counting and holding the number of times j divided by 1, α, α ² and α ³ by the syndrome calculation means; and a result S ₀ ' of the calculation means. ,
Based on S ₁ ′, S ₂ ′, and S ₃ ′, S ₀ ′+S ₁ ′, S ₁ ′+S ₂ ′,
an addition means for calculating S ₂ ′+S ₃ ′; and the S ₀ ′+S ₁ ′,
A single error detection means for detecting that S ₁ ′+S ₂ ′, S ₂ ′+S ₃ ′ are all “0”, and S ₁ ′+S ₂ ′/α ^a and S ₂ ′+S ₃ ′/α 1/α arithmetic element and 1 respectively to obtain ^2a
K stages of /α ² arithmetic elements are connected in series, and a 1/ ^{α arithmetic element and a 1/α 2 arithmetic element are arranged after each of the 1/α K+} 1 arithmetic element and the 1/α ^{2 (K+1)} arithmetic element, respectively. They are connected in cascade and detect the coincidence between the output of each arithmetic element in each stage and S ₀ ′+S ₁ ′ and calculate S ₀ ′+S ₁ ′=S ₁ ′+S ₂ ′/α ^a =S ₂ ′+S ₃ ′ /α ^2a , a double error detection means for detecting a when it becomes /α 2a; an error position _calculation means for calculating i from j held in the counting means and the _a ; and an error calculation means for calculating an error component based on the error component.

(E) Effect According to the above means, the syndrome calculation means multiplies the symbols by 1, α, α ² and α ^3, respectively, depending on the timing when the symbols are sequentially applied.
By calculating the sum of the multiplication result and the symbol to be applied next, and further multiplying the sum by 1, α, α ² and α ³ , the above-mentioned equation (1) is calculated, and the syndrome S ₀ , Find S ₁ , S ₂ , and S ₃ . If the calculated syndromes S ₀ , S ₁ , S ₂ , and S ₃ are all "0", the error zero detection circuit determines that all the read data are correct. On the other hand, if there is an error, the calculation means calculates the syndromes S ₀ , S ₁ ,
The operation of dividing S ₂ and S ₃ by 1, α, α ² and α ^3, respectively, and then dividing the previous calculation result by 1, α, α ² and α ³ at the next timing is repeated. Furthermore, each time this division is executed, based on the division results S ₀ ′, S ₁ ′, S ₂ ′, S ₃ ′, the addition means adds S ₀ ′+S ₁ ′, S ₁ ′+S ₂ ′, S ₂ ′+S ₃ ′ is obtained, and S ₀ ′+S ₁ ′, S ₁ ′+S ₂ ′, and S ₂ ′+S ₃ ′ are applied to the single error detection means and also applied to the double error detection means. be done. Further, the number of divisions is counted and held in a counting means. That is, when the single error detection means detects S ₀ ′ + S ₁ ′ = S ₁ ′ + S ₂ ′ = S ₂ ′ + S ₃ ′ = 0, it is detected that there is one data error, and that The error position j can be determined based on the contents of the counting means at that time. In addition, the double error detection means detects the match detection output when S ₀ ′+S ₁ ′=S ₁ ′+S ₂ ′/α ^a =S ₂ ′+S ₃ ′/α ^2a and the calculation in which the match was detected. There were two data errors depending on the position of the element, and the difference between the error positions a(=i-
j) is determined, and the error position j can be determined based on the contents of the counting means at that time. Therefore, the error position calculation means can calculate the error position i from a and j. On the other hand, if no detection is performed, three or more errors have occurred, and in this case, correction is impossible. By each means acting in this manner, error detection can be easily performed with a small number of timing signals.

(f) Embodiments First, before explaining embodiments, data error detection of the present invention will be explained. For _C1 error detection,
Syndrome can be calculated from symbol using equation (1) mentioned above.
S ₀ , S ₁ , S ₂ , and S ₃ are determined, and in the case of the present invention, equation (1) is rewritten as follows.

S ₀ S ₁ S ₂ S ₃ = 1 α ³¹ α ⁶² α ⁹³ 1……1 1 α ³⁰ α ⁶⁰ α ⁹⁰ …… …… …… 1 α α ² α ³ 1 1 1 1D ₃₁ D ₃₀ 〓 D ₀
...(1)′ This is the subscript of symbols D ₀ to D ₃₁ in equation (1) reversed, and the symbol in equation (1)′ is
D ₃₁ is the actual symbol D ₀ . That is, the actual symbols are D ₀ ,
D ₁ , D ₂ ...D ₃₁ , but in the present invention, conversely,
Since D ₃₁ , D ₃₀ . . . D ₀ are used, the addresses are so-called reversed.

If there is no error in symbols D ₃₁ to _{D 0} , syndromes S ₀ , S ₁ , S ₂ , and S ₃ are all “0”. However, if an error occurs in symbols D _i and D _j (j≦i), the syndrome is S ₀ = E _i + E _j S ₁ = α ⁱ E _i + α ^j E _j S ₂ = α ²ⁱ E _i + α ^2j E _j S ₃ = α _3i E _i + α ^3j E _j ...(2). Note that E _i and E _j are each error components.

When these calculated syndromes S ₀ , S ₁ , S ₂ , S ₃ are divided by 1, α, α ² , α ³ j times, respectively, S ₀ ′,
Suppose S ₁ ′, S ₂ ′, S ₃ ′, becomes. Therefore, from equation (3), S ₀ ′+S ₁ ′=E _i (1+α ^ij ) ……(4) S ₁ ′+S ₂ ′=α ^ij E _i (1+α ^ij ) ……(5) S ₂ ′+S ₃ '=α ^2(ij) E _i (1+α ^ij ) ...(6) is obtained.

Here, in the case of a single error, assuming that i=j and E _i =0, equations (4), (5), and (6) become S ₀ ′+S ₁ ′=S ₁ ′+S ₂ ′=S ₂ ′+S ₃ '=0...(7) Therefore, a single error can be detected by detecting that equation (7) holds true. In addition, the error position is the number of times j of dividing the syndromes S ₀ , S ₁ , S ₂ , and S ₃
The error component E _j is the value of the syndrome S ₀ .

On the other hand, in the case of double error, from equations (4), (5), and (6), S ₀ ′+S ₁ ′=S ₁ ′+S ₂ ′/α ^ij =S ₂ ′+S ₃ ′/α ^2(i
-j) ...(8) is required. In equation (8), if i-j=a, since i and j are both 0 to 31, 1≦a≦31
becomes. Therefore, S ₁ ′+S ₂ ′ and S ₂ ′+S ₃ ′ are α,
A double error can be detected if equation (8) holds when divided by α ² a times. Also, the error position i is a+j
It can be found by Furthermore, the error component E _i is
From equation (4), E _i =S ₀ ′+S ₁ ′/1+α ^ij ...(9) is obtained. In equation (9), 1+α ^ij can be converted to α ^x in the Galois field, converting the above a to α ^x to obtain E _i , and further, S ₀ = E _i +
It is determined from E _j by E _j =S ₀ −E _i .

The single error error is made by adding the error component E _j to the symbol at the detected error position j,
Double error correction is performed by adding error components E _i and E _{j to the symbols at detected error positions i and j} , respectively.

FIG. 1 is a block diagram showing an embodiment of the present invention that implements the above-described error detection. In Figure 1, RAM1 is read from disk and EFM
Symbols D ₀ to _{D 31} of each converted frame
(The subscript indicates the actual address order) are written in a predetermined order by an address control circuit (not shown), and are read out during error detection and correction of _C1 and _C2 and when outputting to DA conversion. and a memory to which writing is performed, and are connected by an 8-bit data bus 2. The syndrome calculation means 3, 4, 5, and 6 are each connected to the data bus 2, and the symbols D ₃₁ to D ₀ (the subscript is the actual reverse address,
Use the reverse address below. ) and calculate the above-mentioned equation (1)′, and convert the calculated syndromes S ₀ , S ₁ , S ₂ , and S ₃ to 1, α, α ² , α ^{3 ,} respectively.
This is to calculate S ₀ ′, S ₁ ′, S ₂ ′, and S ₃ ′. In addition, the syndrome calculation means 3, 4, 5, 6
is a clock pulse created by the timing signal SYRAM that reads symbols _D31 to _D0 from RAM1 and the timing signal SYNDCL that executes division.
It operates with SCLK, and switching of division in syndrome calculation is done with control signal SCONT. The addition means 7, 8, and 9 are the syndrome calculation means 3, respectively.
Input the outputs S ₀ ′, S ₁ ′, S ₂ ′, S ₃ ′ of 4, 5, and 6,
It outputs S ₀ ′+S ₁ ′, S ₁ ′+S ₂ ′, and S ₂ ′+S ₃ ′, and performs the modulo 2 sum by E-OR of each bit. The respective outputs of the adding means 7, 8 and 9 are applied to error detection means 10, single error detection means 11, and double error detection means 12. The error zero detection means 10 detects the syndromes S ₀ , S ₁ , S ₂ ,
At the time when S ₃ is calculated, when it is detected that S ₀ = 0 and S ₀ + S ₁ = S ₁ + S ₂ = S ₂ + S ₃ = 0, the symbols D ₃₁ to D ₀ are It determines that there is no error and outputs signal ZE. On the other hand, the single error detection means 11 includes the syndrome calculation means 3,
Syndrome S ₀ , S ₁ , calculated in 4, 5, 6
Each time S ₂ and S ₃ are divided by 1, α, α ² , and α ³ , it is detected that equation (7) holds true, and if equation (7) holds, a single error occurs in the symbol. Outputs detection output 1E as hot. The double error detection means 12 includes syndrome calculation means 3, 4, 5,
Each time division by 6 is performed, it is detected that equation (8) holds true, and S ₁ ′+S ₂ ′ is divided by 1/α ^a , and S ₂ ′+S ₃ ′ is divided by 1/α ^2a Divide by and divide the division result and S ₀ ′ + S ₁
By detecting a match of ', it is possible to determine that there is an error and to obtain error location information a=ij. Then, the double error detection means 12 indicates error position information a.
32 detection outputs a _ij are output. That is, if there is an error in D _i and D _j of symbols D ₃₁ to _{D 0} , (3)
As is clear from equations to (8), the syndrome S ₀ ,
When dividing S ₁ , S ₂ , S ₃ by 1, α, α ² , α ³ j times
Only one of the 32 detection outputs a _ij becomes "1".
However, if there is a triple error or more,
While the syndrome calculation means 3, 4, 5, and 6 perform division 31 times, the detection output appears multiple times in the detection output a _ij . The detection output _aij is a 32-bit D-
is applied to the a register 13 consisting of FF and
All signals except a ₀ (when i=j) are applied to the OR gate 14, and the output of the OR gate 14 is output as the error detection output 2E. The counting means 15 counts the timing signal SYNDCL that causes the syndrome calculation means 3, 4, 5, and 6 to execute division by 1, α, α ² , and α ³ , and calculates the number of times the division has been performed. It consists of a counter 16 and a register 17 consisting of a 5-bit D-FF to which the output of the counter 16 is applied and stores the count contents. The latch pulse generating means 18 is applied with the detection output 1E from the single error detection means 11 and the detection output 2E outputted from the double error detection means 12 via the OR gate 14, and is based on the detection outputs 1E and 2E, respectively. counter 1
A pulse jLP that causes the 5-bit register 17 to hold the count contents of 6 is output from the OR gate 19.
Furthermore, the pulse jLP consists of a register 20 consisting of an 8-bit D-FF that stores and holds the output S ₀ ' of the syndrome calculation means 3, a 32-bit a register 13 that stores the detection output a _ij , and S ₀ '+S This serves as a clock for register 21 consisting of an 8-bit D-FF that stores ₁ '. Furthermore, the latch pulse outputted from the latch pulse generating means 18 based on the detection output 2E is applied to the uncorrectability determining means 22. The uncorrectable determination means 22 determines that the applied latch pulse is 1.
In the case of , it is determined that there is a double error, and it instructs the correction control means 23 to make a correction, and outputs a control signal 2ESIG that instructs the flag control means 24 to add the C ₁ or C ₂ flag, and If two or more latch pulses are applied, it is determined that there is a triple error or more, and the correction control means 23 is instructed to prohibit correction, and the flag control means 24 is set to C ₁ or
A control signal NG instructing to add the _C2 flag to the flag register 25 is output. These, the latch pulse generation means 18 and the uncorrectable determination means 22
and the correction control means 23 includes the error zero detection means 1
If the detection output ZE from 0 is applied and no error is detected, these operations are prohibited.
The encoder 26 to which the detection output _aij held in the a register 13 is applied converts the 32 signals into 5-bit binary data, and the 5-bit data after conversion is applied to the error position calculation means 27. be done. The error position calculation means 27 includes the counting means 1
The data held in the register 17 of 5, that is, the number of times j and i-j of the syndromes S ₀ , S ₁ , S ₂ , and S ₃ are divided by 1, α, α ² , and α ³ , respectively, are added together. This is an addition circuit that calculates the error position i. The output i (5 bits) of the error position calculating means 27 and the output j of the register 17 are both sent to inverters 28 and 29.
and selected by multiplexer 30.
It is supplied to the address control circuit of RAM1. That is, error positions i and j are used to specify the address of a symbol where an error has occurred and to correct the symbol. Here, the inverter 28,
The reason why data i and j are inverted by 29 is to restore the addresses of the symbols D ₀ to D ₃₁ since they have been given in reverse, as described above.

The error calculation means 31 inputs S ₀ '+S ₁ ' stored in the register 21 and the error position information a _ij stored in the a register 13, and calculates the error component of the symbol at the error position i based on equation (9). This is to calculate E _i , and 1
A decoder method is used to convert +α ^ij to α ^x ,
Calculations are simplified. The addition means 23 calculates the sum of error components E _i and E _j S′ ₀ (equal to the syndrome S ₀ ) and the error component E _i calculated by the error calculation means 31.
, and the error component E _j is calculated by E-OR for each bit. The calculated error components E _i and E _j are applied to each multiplexer 33
and the same control signal as multiplexer 33
Selectively output by SEL. That is, when multiplexer 30 selects and outputs error position data i, error component E _i is output from multiplexer 33, and when error position data j is selected, error component E _j is selected. An adder 34 to which the output of the multiplexer 33 is applied and a register 35 consisting of an 8-bit D-FF perform error correction, and the error position data i or the register 35 selected from the multiplexer 30 and applied to the address control circuit The error symbol D _i or D j read from RAM 1 based on j is held in the register 35, and the error symbol D i or D _j is
Modillo 2 of D _i or D _j and error component E _i or E _j
The addition result, ie, the corrected symbol, is stored again at the same address in RAM1. The operation of the addition means 34 is controlled by the control signal ENA output from the correction control means 23, and the addition operation is not performed in the case of no error and uncorrectable error, and in the case of a single error and double error. An addition operation is performed.

The error detection and correction circuit described above is C ₁
This circuit is used for both error detection and correction and _C2 error detection and correction, but in the case of _C2 error detection and correction, the number of symbols is 28 from _D0 to _D27 , so the syndrome Arithmetic means 3, 4, 5, 6
The number of timings for calculating the syndromes S ₀ , S ₁ , S ₂ , and S ₃ is 28, and the number of times of division by 1, α, α ² , and α ³ is 27. Therefore, during the _C2 error detection and correction period, the counter 16 is first preset to "4". Details regarding this point will be described later.

Next, main specific examples of the circuit shown in FIG. 1 will be explained below.

FIG. 2 shows syndrome calculation means 3, 4, 5,
6, which includes an E-OR gate 36 to which each bit _b0 to _b7 of the symbol sent to the data bus 2 is applied, and eight gates to which the output of the E-OR gate 36 is applied. D-FF37 and D-FF
37, and ^a multiplexer 40 that selects the output of each of the ^arithmetic elements 38 and 39 and applies it to each input of the E-OR gate 36. configured. D-
The FF 37 operates with the clock pulse SCLK generated by the timing signal SYRAM and the timing signal SYNDCL mentioned above, and the multiplexer 40 calculates the syndromes S ₀ , S ₁ , S ₂ , S ₃ and 1, α, α ² ,
It is controlled by a control signal SCONT that switches between dividing and dividing ^α3 . That is, when calculating the syndromes S ₀ , S ₁ , S ₂ , and S ₃ , the α ⁿ calculation element 38 is used,
When calculating S ₀ ′, S ₁ ′, S ₂ ′, and S ₃ ′ by division, the 1/α ⁿ calculation element 39 is used.

By the way, in the syndrome calculation means 3, (1)'
As is clear from the formula, syndrome S ₀ is a symbol
Since it is the sum of D ₃₁ to _{D 0} , and S ₀ ' is S ₀ divided by "1", the arithmetic element 38 is α ⁰ ,
Arithmetic element 39 is 1/α ⁰ . That is, in the case of the syndrome calculation means 3, the calculation elements 38, 39 and the multiplexer 40 are unnecessary, and the D-FF 37
It is sufficient to directly apply each of the outputs Q ₀ to Q ₇ to the E-OR gate 36. Therefore, the timing signal SYRAM for sequentially reading symbols D ₃₁ to D ₀ from RAM1
As a result, the first read symbol _D31 becomes D-
Symbol input to FF37 and then read out
D ₃₀ is the output of D-FF37, that is, D ₃₁ and E-OR
At gate 36, modulus 2 is added and converted to D-FF.
It is held at 37. Repeat this action 32 times (from D ₃₁ to D ₀
) until symbol D ₀ is read out, D-FF37 is read out.
The output of is the syndrome S ₀ .

Further, in the syndrome calculation means 4, the calculation element 38 is α, and the calculation element 39 is 1/α. This α calculation element 38 is, as shown in FIG. 3a,
Inputs I ₀ to I ₇ and outputs 0 ₀ to 0 ₇ are connected, and three E-
An OR gate 41 is provided, and
As shown in FIG. 3b, the 1/α calculation element 39 has inputs I ₀ to I ₇ and outputs 0 ₀ to 0 ₇ connected to each other, and is also provided with three E-OR gates 42. .
Therefore, in the syndrome calculation means 4, the symbol D ₃₁ first read out from the RAM 1 and stored in the D-FF 37 according to the timing signal SYRAM is
As the multiplication result of αD ₃₁ by α calculation element 38, E
− applied to OR gate 36 and then symbol D ₃₀
When is read out, αD ₃₁ +D ₃₀ is added in the E-OR gate 36, and the result is stored in the D-FF 37. By repeating this operation 32 times, the syndrome S ₁ shown in equation (1)' is calculated and can be output from the outputs Q ₀ to Q ₇ of the D-FF 37. On the other hand, each time one timing signal SYNDCL is applied with the 1/α calculation element 39 selected and the inputs b ₀ to b ₇ of the E-OR gate 36 set to “0”, the signal held in the D-FF 37 is Syndrome S ₁
is multiplied by 1/α by the 1/α calculation element 39 and held in the D-FF 37, and the outputs Q ₀ to Q ₇ become S ₁ '=S ₁ /α.

Therefore, by sequentially applying 31 timing signals SYNDCL, S ₁ ' from S ₁ /α to S ₁ /α ³¹ can be calculated.

Furthermore, the arithmetic element 38 of the syndrome arithmetic means 5
is α ² and the arithmetic element 39 is 1/α ² . This α ² calculation element 38 is an element having the input/output relationship shown in FIG. 3C, and is a two-stage series connection of the α calculation elements shown in FIG. 3A. On the other hand, the 1/α ² arithmetic element 39 is an element having the input/output relationship shown in FIG. 3d, and is also a two-stage series connection of the 1/α arithmetic elements shown in FIG. 3b. Further, the arithmetic element 38 of the syndrome arithmetic means 6 is α ³ and the arithmetic element 39 is 1/α ³ . The α ³ arithmetic element is obtained by connecting three stages of FIG. 3a in series, and the 1/α ³ arithmetic element is obtained by connecting three stages of FIG. 3b in series.

Both syndrome calculation means 5 and 6 calculate the syndromes S ₂ and S ₃ of equation (1)′ using the timing signal SYRAM in the same manner as described above, and
By using SYNDCL, calculations of equation (3) are performed, and S ₂ ' of 1/α ² to 1/α ⁶² and S 3 ' of 1/α ³ to 1/ _α ⁹³ can be calculated.

FIG. 4 is a block diagram showing the structure of the double error detection means 12. This double error detection means 12
is the output S ₁ ′+S′ ₂ (8 bits) from the adding means 8
is applied to the first stage, and 1/α arithmetic element 43 is connected in 7 stages in cascade, 1/α ⁸ arithmetic element 44, 1/α ¹⁶ arithmetic element 45, 1/α to which S ₁ ′+S′ ₂ is applied, respectively. ²⁴ arithmetic element 4
6, 1/α arithmetic elements 47, 48, 49 cascaded in seven stages after each of these arithmetic elements 44, 45, 46, and the output S ₂ '+S' ₃ (8 bits) from the adding means 9. 1α ² arithmetic element 50 which is applied to processing and connected in cascade in 7 stages, 1/α ¹⁶ arithmetic element 51, 1/α ³² arithmetic element 52, and 1/α ⁴⁸ arithmetic element to which S ₂ '+S' ₃ is applied respectively. 5 3, 1/α ² arithmetic elements 54, 55, and 56 cascaded in seven stages after each of these arithmetic elements 51, 52, and 53, and the output of each stage of arithmetic elements and S ₀ '+S ₁ ' Applied coincidence detection circuit 57, S ₀ ′+S ₁ ′, S ₁ ′+
A coincidence detection circuit 57' to which S ₂ ', S ₂ '+S ₃ ' is applied. Here, 1/α calculation elements 43, 47, 48, 49 are the elements shown in FIG. 3b, and 1/α ² calculation elements 50, 54, 55, 56 are shown in FIG. 3d. The 1/α ⁸ arithmetic element 44 is the element shown in FIG. That is, each bit b ₀ to b ₇ of the result obtained from the 1/α ⁿ calculation in the Galois field is the bit A, B, C, ...H (where A is the LSB and H) of the input 8-bit data.
is the MSB) is selectively calculated by the sum of modulus 2. FIG. 7 is a diagram showing the input/output relationship for configuring each arithmetic element used in FIG. 4. Therefore, 1/α ¹⁶ , 1/α ²⁴ , 1/α ³² , 1/
Based on FIG. 7, each of the arithmetic elements 45, 46, 51, 52, and 53 of α ⁴⁸ is also formed by an E-OR gate as in FIG. 6.

On the other hand, the coincidence detection circuits 57 _and 57 ^' , as shown in _FIG . and the E-OR gate 59 to which the output of each bit 1/α _2a of S ₀ ′+S 1 ′ is applied ^;
It is composed of a NOR gate 60 to which the outputs of gates 58 and 59 are applied, and detects that the above-mentioned equation (8) is satisfied. That is, the output a ₁ becomes "1" when i-j = 1, the output a ₂ becomes "1" when i-j = 2, and similarly the _i-
It becomes "1" corresponding to the value of j. Therefore, the syndrome calculation means 3, 4, 5, and 6 calculate 1, α, α ² ,
Each time the division of α ³ is executed, the double error detection means 12 determines whether equation (8) holds true or not, and if there is a double error, the j-th division is performed. When determining the result, one of a ₁ to ₃₁ will be “1”,
Double error detection and error location information ij are obtained.
The coincidence detection circuit 57' has an output _a0 of "1" when i-j=0, and when j=j, that is, a single error, error position information i=j is obtained.

By the way, as shown in FIG _. 4, blocks of cascade- _connected arithmetic elements _are
From the viewpoint of S ₃ ′, by connecting them in parallel, the delay until the output a ₃₁ is determined is reduced compared to the case where 31 stages of 1/α calculation element 43 and 1/α ² calculation element 50 are each connected in cascade. The time is shortened, and the determination can be completed within the timing period in which the syndrome calculation means 3, 4, 5, and 6 execute division by 1, α, ^α2 , and ^α3 once.

FIG. 8 is a circuit diagram of the error calculation means 31,
By the ROM 49 inputting the detection outputs a ₁ to a ₃₁ from the double error detection means 12 and the output of the ROM 49,
A from the lower bit of the 8-bit data of S ₀ ′ + S ₁ ′,
B, C, ...G, H) are selectively added,
It is comprised of a selective addition circuit 50 that creates each bit E _i-0 to _{E i-7} (8 bits in total) of the error component E _i . As mentioned above, the error calculation means 31 calculates the formula (9), and in this case, 1+α ^ij can be converted to α ^x , and the ROM 49 converts 1+α ^ij to α ^x , and It determines the configuration of each bit of the result when 8-bit data is divided by α ^x . For example, when ij = 1, 1 + α is converted to α ²⁵ , and each bit of the error component E _i obtained by dividing S ₀ ′ + S ₁ ′ by α ²⁵ is E _i-7 = A + B + C + D + E + F + G + H E _{i -6} = A+B+C+D+E+F+G E _i-5 = A+B+C+D+E+F E _i-4 = A+B+C+D+E E _i-3 = E+F+G+H E _i-2 = A+B+C E _i-1 = C+D+E+F+G+H E _i-0 = B+C+D+E+F+G+H. Therefore, the selective addition circuit 50 that creates each of E _i-7 to _{E i-0} is connected to the ROM in the AND gate 51.
Based on the signals output from 49, S ₀ ′+
The 8-bit data A to H of S ₁ ' are selected, and the E-OR gate 52 performs modulo 2 addition. Therefore,
Even without performing actual division, the error component E _i can be obtained in real time by applying the detection outputs a ₁ to a ₃₁ .

Next, by the circuit shown in FIG. 1, C ₁ and C ₂
The error detection and correction operations will be briefly explained with reference to FIG.

As shown in Figure 9, the processing period for one frame is
Configure the timing of T ₁ to T ₆ and each of T ₁ to _{T 6}
Consists of 49 timings from t ₀ to t ₄₈ . C ₁ error detection and correction is performed at T ₁ to T ₃ timing, and C ₂
Error detection and correction are performed at timings _T4 to _T6 . First, the syndrome calculation means 3, 4, 5, 6 and the D-FF of each section are reset by the clear pulse CINT generated at _t0 of timing _T1 . This timing T ₁ is the timing at which the syndromes S 0 , S 1 , S 2 , and S 3 are calculated by sequentially reading out the 32 symbols D ₃₁ to D ₀ recorded in the RAM 1, and is the timing at which _the syndromes S ₀ , S _{1 ,} S ₂ , and S ₃ are calculated. The timing signals SYRAM are distributed so that 32 timing signals are generated in the memory. Therefore, the 32nd timing signal
When SYRAM occurs, Sidonroam S ₀ ,
S ₁ , S ₂ , and S ₃ have finished calculating. Next, the timing
_T2 is the timing for error detection, and is distributed so that 32 timing signals SYNDCL are generated. Also, the timing T ₂
Due to the clear pulse SINT generated at timing t ₀ ,
The output of the AND gate 53 shown in FIG. 1 is generated and the counter 16 is preset to "0". Therefore, each time the timing signal SYNDCL occurs,
As the counter 16 counts up, the syndrome calculating means 3, 4, 5, 6 output 1,
Division of α, α ² and α ³ is performed once, and single error detection and double error detection are performed based on the result.
When 32 timing signals SYNDCL have been generated,
If there is a single error or double error, one of the errors j is held in the register 17, and the syndromes S ₀ , S ₁ , S ₂ , S ₃ are set to 1, α, α ² ,
The data S ₀ ′ when divided by α ³ j times is stored in register 20.
In addition, S ₀ ′+S ₁ ′ is held in the register 21, and the double error detection results a _{1 to 31} are held in the a register 13.
Furthermore, the detection result of no error, single error, double error, or uncorrectability is indicated to the correction control means 23 and the uncorrectability determination means 22. Timing T ₃ is the timing to perform correction, and T ₃
The error position i is determined by the control signal SEL during the timing of
The timing for selecting the symbol D _i at that address and the timing for writing the symbol D _i corrected by the addition means 34 to the same address of the RAM 1 again are divided, and the timing for reading and reading out the symbol D i that corrects the error position j in the same way is divided. A writing timing is provided. Therefore, at timing T ₃ ,
At timing _T2 , the above-described processing is performed based on the data held in registers 13, 20, and 21, and correction is performed using the results.

In the case of _C2 error detection and correction, there are 28 symbols _D27 to _D0 . Therefore, at timing _T4 , there are 28 timing signals SYRAM for reading symbols _D27 to _D0 and calculating syndromes _S0 , _S1 , _S2 , and _S3 . The clear pulse SINT generated at timing _t0 clears all the data held during _C1 error detection and correction, and then the 28 timing signals SYRAM clear _the C2
The syndromes S ₀ , S ₁ , S ₂ , and S ₃ are obtained. Clear pulse at timing t ₀ at timing T ₅
When SINT occurs, the counter 16 is preset to "4" by the output of the AND gate 54 in FIG.

Here, the meaning of presetting "4" will be explained. As mentioned above, in RAM1, there are disks such as address 0 1 2 3...30 31 symbol D ₀ D ₁ D ₂ D ₃ ...D ₃₀ D ₃₁ i, j values 31 30 29 28...1 0 Addresses are assigned in the order of symbols read from. However, as shown in equation (1), the exponent of α multiplied by the symbols D ₀ to D ₃₁ is
This is the opposite of the address, and the i and j determined by the circuit of FIG. 1 are the opposite of the actual address. Therefore,
As shown in FIG. 1, the actual address is obtained by inverting the 5-bit binary data representing i and j (2 ⁵ =32) using inverters 28 and 29. However, in case of _C2 error detection and correction, the symbols processed are at addresses 0-2
Since it is a symbol up to 7, the possible values of i and j are 0 to 27. Therefore, if the numerical values of i and j are inverted as they are, the difference will be "4" from the actual address, so "4" must be added before inversion. That is, an adder circuit for adding "4" is required, but if "4" is preset in the counter 16 that calculates j, the adder circuit is unnecessary and the same circuit can be used.

After "4" is preset in the counter 16,
Timing signal generated during timing T ₅
There are 28 SYNDCL signals, and error detection for C ₂ is performed using this signal in exactly the same manner as at timing T ₂ described above. Then, at timing _T6 , error correction of _C2 is performed by the same operation as timing _T3 .

(G) Effects of the Invention As described above, according to the present invention, the timing signal for reading symbols from the RAM and calculating syndromes and the syndromes S ₀ , S ₁ , S ₂ , and S ₃ are set to 1,
Since error detection can be achieved using timing signals divided by α, α ² and α ³ , the number of timing signals required for calculations is reduced. Further, there is no need for a ROM for logarithmic conversion or the like for directly performing error detection calculations, which has the advantage of simplifying the circuit configuration and reducing the number of elements. Furthermore, the error detection speed is increased, malfunctions are eliminated, and a highly reliable error detection circuit can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing a specific configuration of the syndrome calculation means shown in FIG. 1, and FIGS.
c, d are α, α ² , 1/α, 1/α ² circuit diagrams of operational elements;
FIG. 4 is a specific block diagram of the double error detection means shown in FIG. 1, FIG. 5 is a coincidence detection circuit diagram shown in FIG. 4, and ^FIG . Circuit diagram, Figure 7 is a diagram showing the input/output relationship for configuring the 1/α ^a calculation element, Figure 8 is a circuit diagram showing the configuration of the error calculation means, and Figure 9 shows the operation of Figure 1. FIG. 1...RAM, 2...Data bus, 3, 4,
5, 6...Syndrome calculation means, 7, 8, 9...
...Addition means, 10...Error zero detection means, 11...
...Single error detection means, 12...Double error detection means, 13...a register, 15...Counting means, 1
8...Latch pulse generation means, 20, 21...Register, 22...Correction impossibility determination means, 23...Correction control means, 26...Encoder, 27...Error position calculation means, 30, 33...Multiplexer,
28, 29...Inverter, 31...Error calculation means.

Claims (1)

[Claims] 1. In a data error detection circuit that detects errors in data based on Reed-Solomon codes, data that is input in synchronization with a clock signal that controls syndrome calculation is Syndromes S ₀ , S ₁ , S ² , and S ₃ are calculated by repeatedly adding the results of multiplying the calculation results by 1, α, α ₂ , α ³ (α is an 8th order primitive polynomial). At the same time, the calculated syndrome S ₀ ,
Syndrome calculation means that sequentially divides S ₁ , S ₂ , S ₃ by 1, α, α ² , α ³ and syndromes S ₀ , S ₁ , S ₂ , S ₃ output from the syndrome calculation means are all Based on the error zero detection means for detecting "0" and the division results S ₀ ′, S ₁ ′, S ₂ ′, and S ₃ ′ output from the syndrome calculation means for each division, an adding means for calculating S ₀ ′+S ₁ ′, S ₁ ′+S ₂ ′, and _{S 2} ′+S _{3 ′} ;
A single error detection means for detecting that S ₁ ′+S ₂ ′, S ₂ ′+S ₃ ′ are all “0”, and multiple stages of 1/α arithmetic elements connected in cascade after the 1/α ⁿ arithmetic element 1/α after the plurality of first arithmetic element blocks and 1/α ²ⁿ arithmetic elements
A plurality of ^second arithmetic element blocks in which two arithmetic elements are connected in cascade (n is an integer weighted for each block), the output of each stage of the first arithmetic element block, and each of the second arithmetic element blocks. A coincidence detection circuit detects coincidence between the output of the stage and S ₀ ′+S ₁ ′ outputted from the adding means, and the S ₁ ′+
By applying S ₂ ′, S ₂ ′+S ₃ ′ to the initial stage of the first arithmetic element block and the second arithmetic element block, respectively, based on the coincidence output of the coincidence detection circuit, S ₀ ′+S ₁ ′= double error detection means for detecting the error position difference a (a=i−j, i, j are error positions) such that S _{1 ′} +S 2 ′/α a =S 2 _′ +S ₃ ′/α ^{2a ;} counting means for counting clock signals for controlling the division of the syndrome calculation means and holding a numerical value j indicating an error position based on the detection output of the single error detection means; error position calculation means for calculating i from a output from the double detection means; and S ₀ ′+S ₁ ′ and the error position output from the addition means when the detection output of the single error detection means is generated. A data error detection circuit comprising: error calculation means for calculating an error component based on the output a from the detection means.