JPH05190777A - Bi-cmos device and formation method of its buried layer - Google Patents

Abstract

PURPOSE:To provide a Bi-CMOS device wherein its production cost is low, its electric characteristic is excellent and it has suppressed the generation of a digital noise by a method wherein a buried layer is formed without forming an epitaxial layer. CONSTITUTION:In a Bi-COMS device, N<-> buried layers 31, 32, 34, 35 which are formed by an ion implantation method are formed in a P-type semiconductor layer 11 at the lower-part side of, e.g. an NPN bipolar transistor 21 and a lateral PNP bipolar transistor 22 and at the lower-part side of a PMOS transistor 24 and an NMOS transistor 25 for a CMOS transistor 26.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to buried layers for Bi-CMOS devices.

[0002]

2. Description of the Related Art Bipolar transistor and complementary MOS
Bi with (CMOS) transistor formed on the same substrate
A CMOS device will be described with reference to FIG. In the figure, as an example, a CMOS transistor portion of a Bi-CMOS device having a retrograde structure is shown. As shown in the figure, an N-type epitaxial layer 72 is formed on the entire upper surface of the P-type silicon substrate 71. An N well region 74 and a P well region 75 are formed in the N type epitaxial layer 72 with an element isolation region 73 interposed therebetween. This N
An N ⁺ buried diffusion layer 76 and a P ⁺ buried diffusion layer 77 are formed below the well region 74 and the P well region 75, respectively. An NMOS transistor 78 having a back gate is formed in the N well region 74. Further, the P well region 75 has a P having a back gate.
A MOS transistor 79 is formed. Above NMO
A CMOS transistor 80 is formed by the S transistor 78 and the PMOS transistor 79.

An N ⁺ buried diffusion layer (not shown) is formed in the lower layer of the N type epitaxial layer 72 and the upper layer of the P type silicon substrate 71 connected thereto. Further, an NPN bipolar transistor (not shown) is formed on the N ⁺ buried diffusion layer.

[0004]

However, the above B
In the i-CMOS device, the manufacturing cost is high because the epitaxial layer is formed. Also, a so-called retrograde structure Bi- connecting the back gate (P well region) of the NMOS transistor and the P-type silicon substrate.
The CMOS device has excellent resistance to latch-up, but a through current that flows from the P well region to the P-type silicon substrate is generated during switching of the CMOS transistor, and this through current becomes digital noise that adversely affects the bipolar transistor. Further, in the Bi-CMOS process in which the epitaxial layer is not formed, the buried layer cannot be formed in the silicon substrate below the formation region of the bipolar transistor. Therefore, for example, in the NPN bipolar transistor, the saturation voltage Vce (sat) or the PNP bipolar transistor is formed. The characteristics of the current amplification factor h _{FE and the} like are deteriorated, and the current amplification factor h _FE of the parasitic PNP bipolar transistor is increased.

It is an object of the present invention to provide a buried layer of a Bi-CMOS device which is low in cost and excellent in electric performance, and a method of forming the buried layer.

[0006]

The present invention has been made to achieve the above object. That is, in a Bi-CMOS device in which a bipolar transistor and a complementary MOS transistor are formed on a semiconductor substrate of the first conductivity type, a lower side of the bipolar transistor and a complementary MO transistor are provided.
A buried layer of the second conductivity type formed by an ion implantation method is provided in the semiconductor substrate of the first conductivity type on the lower side of the S transistor.

As a method of forming a buried layer of a Bi-CMOS device, first, in a first step, the CMOS is formed in a formation region of a CMOS transistor of a semiconductor substrate of the first conductivity type.
The well region of the transistor is formed, and the well region of the bipolar transistor is formed in the formation region of the bipolar transistor on the semiconductor substrate of the first conductivity type. Next, in a second step, the bipolar transistor formation region and the CMOS are formed on the upper layer of the first conductivity type semiconductor substrate.
Same as the formation area of the NMOS transistor of the transistor
An element isolation region for isolating the formation region of the MOS transistor is formed. After that, in a third step, an impurity of the second conductivity type is introduced into the semiconductor substrate of the first conductivity type on the lower layer side of each well region by an ion implantation method, and then an impurity of the second conductivity type is diffused. A buried layer of the second conductivity type is formed by diffusing into a semiconductor substrate of the first conductivity type.

[0008]

In the Bi-CMOS device having the above structure, the CM
Since the buried layer of the second conductivity type is formed in the semiconductor substrate of the first conductivity type below the formation region of the OS transistor, the through current does not flow from the well region of the CMOS transistor to the semiconductor substrate of the first conductivity type. Therefore, noise due to the through current does not occur. Moreover, since the buried layer of the second conductivity type is formed in the semiconductor substrate of the first conductivity type below the formation region of the bipolar transistor, the saturation voltage Vce (sat) does not decrease in the NPN bipolar transistor, for example. Also there is no decrease in the current gain h _FE is a PNP bipolar transistor, further current amplification factor h _FE of the parasitic PNP bipolar transistor is lowered.

In the method of forming the buried layer of the Bi-CMOS device, the buried layer of the second conductivity type is formed by the ion implantation method, so that the manufacturing cost is reduced.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT An embodiment of the present invention will be described with reference to the schematic sectional view of FIG. As shown in the drawing, an element isolation region 12 is formed in an upper layer of a first conductivity type semiconductor substrate (hereinafter referred to as a P-type semiconductor substrate) 11. The P-type semiconductor substrate 11 is, for example, a P-type single crystal silicon substrate. The element isolation region 12 is formed of the LOCOS oxide film 13 or the LO
It comprises a COS oxide film 13 and a channel stopper P-well region 14. The element isolation region 12 separates the N well regions 15, 16, 17, 18 provided in the upper layer of the P type semiconductor substrate 11 from the P well region 19. An NPN bipolar transistor 21, a lateral PNP bipolar transistor 22, a diffusion resistor 23, and an NPN bipolar transistor 21 are provided on the upper layers of the N well regions 15, 16, 17, and 18, respectively.
A PMOS transistor 24 is formed. Further, in the upper layer of the P well region 19, the NMOS transistor 2
5 is formed. In addition, the PMOS transistor 2
4 and the above-mentioned NMOS transistor 25 form a CMOS
The transistor 26 is formed. As above, Bi-
The CMOS device 10 is configured.

Each of the N well regions 15, 16, 17, 1
8 and the P well region 19 on the lower surface side,
Second conductivity type buried layers (eg N ⁺ buried layer) 31, 3
2, 33, 34 and 35 are formed. Hereinafter, each buried layer of the second conductivity type is referred to as an N ⁺ buried layer.

In the Bi-CMOS device 10 having the above structure, since the N ⁺ buried layer 35 is formed on the lower side of the P well region 19 of the NMOS transistor 25, the P type semiconductor substrate 1 is formed from the P well region 19 of the NMOS transistor 25.
No through current will flow to the unit 1. Therefore, digital noise due to the through current is eliminated. Since the N ⁺ buried layers 31 and 32 are formed in the P-type semiconductor substrate 11 below the NPN bipolar transistor 21 and the lateral PNP bipolar transistor 22, for example, NP
In the N bipolar transistor 21, the saturation voltage Vce (s
at) does not decrease, and the lateral PNP bipolar transistor 22 does not decrease the current amplification factor h _FE .
Also, the current amplification factor h of the parasitic PNP bipolar transistor
_FE can be reduced.

Next, a method of forming the N ⁺ buried layers 31 to 35 will be described with reference to FIG. However, the N ⁺ buried layers 32 and 33 are omitted in the drawing. In the first step shown in FIG. 2A, a silicon oxide film 41 of, eg, 50 nm is formed on the upper layer of the first conductivity type semiconductor substrate (hereinafter referred to as P-type semiconductor substrate) 11 by, for example, a thermal oxidation method. To do. Then, a silicon nitride film 42 is formed on the upper surface of the silicon oxide film 41 by, for example, a normal chemical vapor deposition method, for example, 100
It is formed to a thickness of nm to 150 nm. Then, the portion indicated by the chain double-dashed line of the silicon nitride film 42 is removed by ordinary photolithography and etching, and the LOC
An OS oxidation mask 43 is formed. After that, an etching mask (not shown) formed by the above photolithography
To remove.

Then, as shown in FIG. 2B, the formation region 51 of the NPN bipolar transistor (21), the formation region (not shown) of the lateral PNP bipolar transistor (22), and the diffusion resistance are formed by ordinary photolithography. (23) forming region (not shown), the PMOS transistor (24) forming region 54 is provided with an ion implantation mask 44 provided with an opening on each region.
Form on top. The ion implantation mask 44 is formed of, for example, a resist. Then, by a normal ion implantation method, the LOCOS oxidation mask 4 made of the above silicon nitride film.
3 and the silicon oxide film 41, the P-type semiconductor substrate 1
For example, phosphorus (for example, P ⁺ ) as N-type impurities is ion-implanted into the substrate 1. Ion implantation conditions at this time are as follows.
For example, the implantation energy is 90 keV and the dose is 1
It is set to × 10 ¹³ pieces / cm ² .

After that, the ion implantation mask 44 is removed by, for example, an asher process and a wet process using sulfuric acid / hydrogen peroxide mixture. Then, as shown in (3) of FIG.
An ion implantation mask 45 having an opening formed on the formation region 55 of the NMOS transistor (25) is formed on the silicon oxide film 41 by ordinary photolithography. The ion implantation mask 45 is formed of, for example, a resist as described above. Then, by a normal ion implantation method, the LOCOS oxidation mask 4 made of the above silicon nitride film.
3 and the silicon oxide film 41, the P-type semiconductor substrate 1
1 in which, for example, boron (eg, B ⁺ ) as a P-type impurity
Is ion-implanted. As the ion implantation conditions at this time, for example, the implantation energy is set to 180 keV and the dose amount is set to 5 × 10 ¹² pieces / cm ² .

After that, the ion implantation mask 45 is removed by, for example, an asher process and a wet process using sulfuric acid / hydrogen peroxide mixture. Then, as shown in (4) of FIG.
By performing the diffusion process, the ion-implanted phosphorus in the P-type semiconductor substrate 11 is diffused, and the N-well regions 15 and 1 are formed.
8 is formed, and boric acid ion-implanted into the P-type semiconductor substrate 11 is diffused to form a P well region 19. Then, the normal LOCOS oxidation in the second step is performed to form the LOCOS oxide film 13 of the element isolation region made of silicon oxide on the upper layer of the P-type semiconductor substrate 11. After that, the LOCOS oxidation mask 43 (portion indicated by a chain double-dashed line) is removed by, for example, wet etching.

Then, in a third step shown in FIG. 2 (5), the lower layers of the N well regions 15 and 18 and the P well region 19 are passed through the silicon oxide film 41 by a normal ion implantation method. Phosphorus (for example, P ⁺ ) is ion-implanted into the P-type semiconductor substrate 11. The ion implantation conditions at this time are, for example, implantation energy of 2
MeV to 3 MeV, the dose amount is 1 × 10 ¹³ pieces / cm ² to
It is set to 1 × 10 ¹⁴ pieces / cm ² . The dose amount is preferably set to 5 × 10 ¹³ pieces / cm ² or less. When the implantation energy is about 2 MeV to 3 MeV, double-charged or triple-charged phosphorus is ion-implanted at about 1 MeV. Then, phosphorus is diffused into the P-type semiconductor substrate 11 by the diffusion process to form the N ⁺ buried layers 31, 34 and 35. The diffusion process is performed in a subsequent step (for example, a gate oxide film forming step or a gate po
This is performed in a step of applying heat such as a ly-Si film forming step).

In the above-mentioned forming method, the N ⁺ buried layers 31 and 3 are formed after the element isolation region 12 of the LOCOS oxide film is formed.
4, 35 are formed, but the N ⁺ buried layers 31, 34, 35 are formed.
It is also possible to perform the ion implantation for forming the film before the LOCOS oxidation. Although the description of the method for forming the N ⁺ buried layers (32) and (33) (see FIG. 1) is omitted in the above description, the N ⁺ buried layers (32) and (33) are the same as the N ⁺ buried layers. It can be formed simultaneously with 31, 34, and 35 and in the same manner. Further, the channel stopper P-well region (14) (see FIG. 1) can be formed simultaneously with the P-well region 19.

It should be noted that the N ⁺ buried layer 31 is subjected to the above processing.
1 to 35 (however, the description of the method of forming the N ⁺ buried layers 32 and 33 is omitted) is performed on the P-type semiconductor substrate 11 shown in FIG.
NPN bipolar transistor (21), lateral PNP bipolar transistor (22), diffusion resistance (23), PMOS transistor (24), NMOS described in
The transistor (25) and the like are formed by the usual manufacturing process already proposed. Therefore,
The manufacture of the above manufacturing process is omitted here.

According to the method for forming the buried layer of the Bi-CMOS device, since the N ⁺ buried layers 31 to 35 are formed by the ion implantation method and the thermal diffusion process, the conventional buried layer for forming the epitaxial layer is formed. Manufacturing cost is lower than the method.

[0021]

As described above, according to the first aspect of the invention, the Bi-CMO provided with the semiconductor substrate of the first conductivity type is provided.
Since the buried layer of the second conductivity type is formed in the semiconductor substrate of the first conductivity type below each transistor formation region in the S device, the well region of the NMOS transistor in the CMOS transistor may flow to the semiconductor substrate of the first conductivity type. The through current is blocked by the buried layer of the second conductivity type and stops flowing. Therefore, the generation of digital noise due to the through current is eliminated, and the electrical characteristics of the bipolar transistor can be improved. Further, according to the invention of claim 2, since the buried layer of the second conductivity type is formed by the ion implantation method, the manufacturing cost can be reduced.

[Brief description of drawings]

FIG. 1 is a schematic configuration sectional view of an example.

FIG. 2 is a process drawing of a method for forming a buried layer.

FIG. 3 is a schematic configuration sectional view of a conventional example.

[Explanation of symbols]

10 Bi-CMOS device 11 P-type semiconductor substrate 12 Element isolation region 15 N well region 16 N well region 17 N well region 18 N well region 19 P well region 21 NPN bipolar transistor 24 PMOS transistor 25 NMOS transistor 26 CMOS transistor 31 N ⁺ Buried layer 32 N ⁺ Buried layer 33 N ⁺ Buried layer 34 N ⁺ Buried layer 35 N ⁺ Buried layer 54 Forming region of PMOS transistor (24) 55 Forming region of NMOS transistor (25)

[Procedure amendment]

[Submission date] April 3, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] 0002

[Correction method] Change

[Correction content]

[0002]

2. Description of the Related Art Bipolar transistor and complementary MOS
Bi with (CMOS) transistor formed on the same substrate
A CMOS device will be described with reference to FIG. In the figure, as an example, a CMOS transistor portion of a Bi-CMOS device having a retrograde structure is shown. As shown in the figure, an N-type epitaxial layer 72 is formed on the entire upper surface of the P-type silicon substrate 71. An N well region 74 and a P well region 75 are formed in the N type epitaxial layer 72 with an element isolation region 73 interposed therebetween. This N
An N ⁺ buried diffusion layer 76 and a P ⁺ buried diffusion layer 77 are formed below the well region 74 and the P well region 75, respectively. A PMOS transistor 78 having a back gate is formed in the N well region 74. The P well region 75 has an N having a back gate.
A MOS transistor 79 is formed. Above PMO
A CMOS transistor 80 is formed by the S transistor 78 and the NMOS transistor 79.

[Procedure Amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0014

[Correction method] Change

[Correction content]

Then, as shown in FIG. 2B, the formation region 51 of the NPN bipolar transistor (21), the formation region (not shown) of the lateral PNP bipolar transistor (22), and the diffusion resistance are formed by ordinary photolithography. (23) forming region (not shown), the PMOS transistor (24) forming region 54 is provided with an ion implantation mask 44 provided with an opening on each region.
Form on top. The ion implantation mask 44 is formed of, for example, a resist. Then, by a normal ion implantation method, the LOCOS oxidation mask 4 made of the above silicon nitride film.
3 and the silicon oxide film 41, the P-type semiconductor substrate 1
For example, phosphorus (for example, P ⁺ ) as N-type impurities is ion-implanted into the substrate 1. Ion implantation conditions at this time are as follows.
For example, the implantation energy is set to 180 keV and the dose amount is set to 5 × 10 ¹² pieces / cm ² .

[Procedure 3]

[Document name to be amended] Statement

[Correction target item name] 0015

[Correction method] Change

[Correction content]

After that, the ion implantation mask 44 is removed by, for example, an asher process and a wet process using sulfuric acid / hydrogen peroxide mixture. Then, as shown in (3) of FIG.
An ion implantation mask 45 having an opening formed on the formation region 55 of the NMOS transistor (25) is formed on the silicon oxide film 41 by ordinary photolithography. The ion implantation mask 45 is formed of, for example, a resist as described above. Then, by a normal ion implantation method, the LOCOS oxidation mask 4 made of the above silicon nitride film.
3 and the silicon oxide film 41, the P-type semiconductor substrate 1
1 in which, for example, boron (eg, B ⁺ ) as a P-type impurity
Is ion-implanted. As the ion implantation conditions at this time, for example, the implantation energy is set to 90 keV and the dose amount is set to 1 × 10 ¹³ ions / cm ² .

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction content]

Then, in a third step shown in FIG. 2 (5), the lower layers of the N well regions 15 and 18 and the P well region 19 are passed through the silicon oxide film 41 by a normal ion implantation method. Phosphorus (for example, P ⁺ ) is ion-implanted into the P-type semiconductor substrate 11. The ion implantation condition at this time is, for example, an implantation energy of 1
MeV to 5 MeV, the dose amount is 1 × 10 ¹² pieces / cm ^2.
˜1 × 10 ¹⁵ pieces / cm ² is set. The dose amount is preferably set to 5 × 10 ¹³ pieces / cm ² or less. When the implantation energy is about 2 MeV to 3 MeV, double-charged or triple-charged phosphorus is ion-implanted at about 1 MeV. Then, phosphorus is diffused into the P-type semiconductor substrate 11 by a diffusion process,
The N ⁺ buried layers 31, 34 and 35 are formed. The diffusion process is performed in a subsequent step (for example, a step of applying heat such as a gate oxide film forming step or a gate poly-Si film forming step).

Claims (2)

[Claims] 1. A bipolar transistor and a complementary MOS
Forming a transistor on a semiconductor substrate of the first conductivity type B
In an i-CMOS device, the lower side of the bipolar transistor and the complementary MO
A second-conductivity-type buried layer formed by an ion implantation method is provided in the first-conductivity-type semiconductor substrate on the lower side of the S-transistor.
S device. 2. A bipolar transistor and a complementary MOS
Forming a transistor on a semiconductor substrate of the first conductivity type B
A method of forming a buried layer of an i-CMOS device, comprising forming a well region of a complementary MOS transistor in a formation region of a complementary MOS transistor of a semiconductor substrate of the first conductivity type, and forming a well region of the complementary MOS transistor. Forming a well region of the bipolar transistor in a bipolar transistor formation region of the semiconductor substrate, and forming the bipolar transistor formation region and the complementary MOS transistor in an upper layer of the semiconductor substrate of the first conductivity type. Complementary MOS with the formation region of the NMOS transistor
A second step of forming an element isolation region for isolating a PMOS transistor formation region of the transistor, and a second conductivity type in the semiconductor substrate of the first conductivity type under each well region by an ion implantation method. And a third step of forming a second conductivity type buried layer by diffusing the second conductivity type impurities into the first conductivity type semiconductor substrate by a diffusion process. A method for forming a buried layer of a characteristic Bi-CMOS device.