JP3277561B2 - Semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a region having a surface impurity concentration of 1 × 10 ¹⁹ / cm ³ or less. The semiconductor device of the present invention has an MO
An S transistor, a bipolar transistor, or a semiconductor device having a bipolar transistor and a MOS transistor (hereinafter, such a transistor is referred to as “BiCM
Various types of semiconductor devices such as an “OS transistor” may be used.

[0002]

2. Description of the Related Art Conventionally, in the process of manufacturing a semiconductor device, a means that has a relatively high possibility of relatively damaging an underlying substrate or the like is sometimes used. For example, RIE may damage the underlying semiconductor substrate. RIE is, for example, LDD
(Lightly Doped Drain) Used when forming a sidewall used to form a structure. As described above, in the manufacturing process of various semiconductor devices having the LDD structure in the CMOS portion, the sidewall R
The IE step is generally essential.

After the sidewall RIE step, in the case of a normal Si semiconductor manufacturing process, the Si substrate is exposed except for the LOCOS region and the poly-Si region. For this reason, there is a concern that damage may enter the Si substrate due to RIE.

[0004] The above problem becomes a problem in any process having a process before the RIE step. In the CMOS process, the region receiving the sidewall RIE is only the source / drain region and is a region doped with high-concentration impurities. Therefore, it can be said that the influence of the damage on the device characteristics is not so large. However, damage is not desirable.

On the other hand, in the BiCMOS process,
Since an NPN transistor, a PNP transistor, a resistor, and the like are formed in a region where the RIE for forming a sidewall is performed, h _FE in a low current region due to an increase in surface recombination current is obtained.
There is a problem that the RIE is reduced, and the influence of the damage at the time of RIE is great.

That is, in the conventional BiCMOS manufacturing process, the Si substrate is exposed as shown in FIG. 8 after the RIE step for forming the sidewall of the CMOS portion. The exposed portions are indicated by 2A to 2D. In this exposed part, RIE
Due to the Qss at the Si—SiO ₂ interface due to the damage, the change in the surface state, and the contamination due to the RIE process, the NPN transistor formed at the position corresponding to the exposed portion 2A has a low power due to an increase in recombination current. H _FE in the basin
And L formed at a position corresponding to the exposed portion 2C
Reduction in h _FE in the low current region also due to the increase of the recombination current in the PNP transistor, and characteristic variation due to deterioration of the surface state by RIE damage is disadvantageously increased. In FIG. 8, 1a1 to 1a3 are N-type buried layers (NBL), 1b1 to 1b4 are P-type buried layers, and 35 is R
IE indicates a sidewall to be formed, and an arrow indicates RIE that typically damages the sidewall.

The bipolar transistor is also a semiconductor device having a diffusion resistance. However, the invention is not limited to this. For a semiconductor device having a resistance formed by a diffusion region,
Due to the above-described RIE or the like, characteristic changes such as electric characteristic fluctuations may occur. For example, it is a commonly used technique to form an insulating film and perform RIE, not necessarily for forming a sidewall, and thereby, a diffusion resistance value is increased.
May change. It also has a high resistance to diffusion resistance.
Of the interlayer film used in the wiring process
The resistance value changes due to the stress applied by the membrane
There is a problem, and it is desired to reduce such stress.

[0008]

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems of the prior art, and to prevent a problem such as characteristic deterioration from occurring due to damage represented by RIE (for forming a sidewall or the like). It is intended to provide a device.

[0009]

Means for Solving the Problems Each invention according to the present application is:
The above object has been achieved by the following constitutions.

[0010] The invention of claim 1 of the present application is a bipolar transistor .
A half including a transistor and a MOS transistor on a substrate
A conductor device, wherein two or more resistance values different from each other are provided on the substrate.
Forming a diffusion resistance region by ion implantation.
In the resistance region, the surface impurity concentration is 1 × 10 ¹⁹ / cm ³
The following regions are defined as resistance regions other than the gate resistance,
The upper layer of the resistance region other than the gate resistor is covered with a silicon-based material.
The semiconductor device is characterized in that
The purpose is achieved.

The invention according to claim 2 of the present application is directed to a silicon-based material.
The material is polysilicon, and the polysilicon is a MOS transistor.
At the same time as polysilicon for forming the transistor gate electrode material.
2. The method according to claim 1, wherein the element is formed.
Which achieves the above object.
It is.

The invention according to claim 3 of the present application is directed to a silicon-based material.
The material is a refractory metal silicide,
Reside is for forming gate electrode material of MOS transistor
Characterized by being formed simultaneously with polysilicon
2. The semiconductor device according to claim 1, wherein
The above object is achieved.

[0013]

According to the prior art, the exposed portion of the substrate is damaged by RIE or the like, and the electrical characteristics are degraded. On the other hand, in the invention of the present application, the substrate is made of a silicon-based material. Is protected, so this problem is solved. For example, by subsequent ion implantation (for example, source / drain ion implantation of a CMOS portion), a portion that is not protected by the silicon-based material becomes an impurity concentration region equivalent to, for example, the source / drain region. The impurity concentration is a low concentration impurity region (the surface impurity is 1 × 10
¹⁹ / cm ³ or less), and this portion is selectively protected.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below. However, needless to say, the present invention is not limited by the following examples.

Embodiment 1 In this embodiment, the present invention is applied to a BiCMOS transistor and its manufacturing process.

FIG. 1 shows a semiconductor device (BiCMOS transistor) of this embodiment. This semiconductor device is a semiconductor
After the end of the device manufacturing process, the MOS transistors
Have on a plate, formed on the same substrate by ion implantation
Semiconductor device having two or more diffusion resistance regions having different resistance values
A location, as shown in FIG. 1, a semiconductor device having a diffusion resistance 7, a region of high resistance value of the resistor main body
Is a region having a surface impurity concentration of 1 × 10 ¹⁹ / cm ³ or less covered with silicon-based materials 3a and 3b.

More specifically, this embodiment relates to a semiconductor device having bipolar transistors 4c and 4d, and a MOS transistor is provided after the semiconductor device manufacturing process is completed.
Data on the same substrate, and ion implantation on the same substrate
Has two or more diffused resistance regions with different resistance values formed
Semiconductor device, wherein the resistance value of the diffusion resistance region is
The surface impurity concentration of the high region is 1 × 10 ¹⁹ or less The region is selectively covered with silicon-based materials 3a to 3d.

In this embodiment, the silicon-based materials 3a to 3a
3d is polysilicon, and polysilicon 8a,
8b constitutes a gate electrode material of the MOS transistors 4a and 4b. The same effect can be obtained when the silicon-based material is a high-melting-point metal silicide.

The manufacturing process of the BiCMOS transistor according to the present embodiment will be described below with reference to FIGS.

In accordance with a general BiCMOS process flow, steps up to gate oxidation are performed. Thereby, the structure of FIG. 2 is obtained. In the figure, 4a 'is a PMOS formation region and 4b' is an NMO
S formation region, 4c 'is NPN formation region, 4d' is LPN
This is a P formation region. 1a1 to 1a3 are N-type buried layers, 1b
1 to 1b4 are P-type buried layers. 2 is a P-type substrate, 23 is an N-type epitaxy layer, 24 is an N-well, 25 is a P-well,
27 is an N-type plug; 28 is a locos region for element isolation;
Reference numeral 9 denotes an insulating film (SiO ₂ ) formed by gate oxidation.

[0021] Thereafter, the selective ion implantation of boron as indicated by I ₁ within the base region of the NPN transistor which is patterned as a mask a photoresist 30 (see FIG. 3). For example, 35 keV1 × 10 ¹⁴ pieces / cm ²
Ion implantation is performed to a degree. Next, the resist is stripped.
Similarly, ion implantation is also selectively performed on the high resistance region. Thus, the structure shown in FIG. 3 is obtained. In the figure, 31 is a base formation region.

Next, about 400 nm of poly-Si is deposited as a silicon-based material by, for example, a low pressure CVD method. Phosphorus (P) is added to the formed poly-Si
₃ is introduced by a Prede method or by diffusion from a PSG-CVD film.

Next, the formed poly-Si is converted into a PMOS gate poly-Si8a, an NMOS gate poly-Si8b, poly-Si3c between the collector and the emitter of the LPNP transistor, poly-Si3d between the emitter and the graft base of the NPN transistor, and The photoresist is removed by selectively etching the poly-Si by RIE while leaving the photoresist selectively only in the high-resistance portion forming region 7. Thereby, poly Si is selectively left. Thus, the structure shown in FIG. 4 is obtained.

Next, in order to form an n ⁻ layer in the NMOS region,
Phosphorus (P) ions are implanted at about 35 keV and about 3.5 × 10 ¹³ / cm ^2, and boron (B) is implanted into the PMOS region with BF ₂ ^{+ at} 50 keV 1.5 × 10 ¹³ / cm ₂ to form a P ⁻ layer. ^Implant about ² ions. Thereby, the structure of FIG. 5 is obtained. In the figure, 33 is a P-LDD, and 34 is an n-LDD region.

Next, in order to form a sidewall, SiO 2
_{The two} films are deposited by about 300 nm, for example, by the TEOSCVD method. Thereafter, the SiO ₂ film is etched by RIE to form sidewalls 35 on the side walls of the gate poly Si 8a, 8b. At this time, in the conventional example, while the substrate Si is exposed in the bipolar element formation region,
In this embodiment, it is selectively protected by 3a to 3d of poly-Si. The part where Si is exposed is CMOS
The same high-concentration impurities as the source / drain of the portion are formed. As a result, the structure shown in FIG. 6 is obtained.

Here, poly Si 8a, 8b, 3a-3d
Is exposed to poly-Si, and the poly-Si 8a,
8b, 3a to 3d, the Si is exposed on the active region which is not protected, so that the SiO ₂ film serving as a buffer layer at the time of the next source / drain ion implantation is changed to, for example, T
Estimate about 20 nm by EOSCVD. And C
In order to densify the VD film, a heat treatment at about 850 ° C. is performed.

Thereafter, the PMOS source / drain 36
a, BF ₂ ⁺ , 50 keV, 5 × 1 on the NPN graft base 36 b and the LPNP emitter / collector 36 c
About ¹⁵ ions / cm ² are implanted, and As is implanted into the NMOS source / drain 37a, the NPN emitter / collectors 37b, 37c, and the LPNP base 37d.
It is introduced by ion implantation at about 70 keV and about 5 × 10 ¹⁵ / cm ² .

Then, according to a general process flow,
A flow film 38 such as a BPSG film is deposited to a thickness of about 500 nm, reflow is performed, and a wiring process is performed. A base electrode 5B, a collector electrode 5C, a collector electrode 6c of the LPNP 4d, an emitter electrode 6E, and a base electrode 6B are formed. Thus, the structure shown in FIG. 1 is obtained. Further, overpassivation is performed as appropriate.

According to this embodiment, since only the region having a low surface concentration is covered with the silicon-based material 3a to 3d such as poly-Si, the surface recombination current caused by the damage of the RIE for forming the sidewall in the MOS region is suppressed. _HFE in the bottom current region can be prevented. Therefore, the countermeasure against the RIE damage for forming the sidewall can be performed without any additional process. Also, according to the present embodiment,
The emitter and the external base region can be formed by self-alignment using the poly Sis 3a to 3d.

Embodiment 2 In the embodiment 1, the diffusion resistor formed by ion implantation is used.
That is, the regions having a low surface concentration are selectively formed in the poly Si layers 3a to 3d.
To protect the substrate from being damaged during the RIE for forming the sidewalls. However, the technique of the present invention can be applied even when there is no RIE step. This is because, by covering with poly-Si or the like, fluctuations in the surface state can be suppressed, and film stress accompanying the wiring process can be reduced with the poly-Si or the like. In particular, it is effective to relieve the stress by using poly-Si or the like, because in a semiconductor device having a diffusion resistance, a resistance value is prevented from fluctuating due to a piezo effect caused by the stress.

This embodiment utilizes this, and the semiconductor device of the present embodiment is shown in FIG. In FIG. 7, 2 is a substrate, a diffused resistor formed by ion implantation in the substrate 2
The present invention was applied to the high resistance region 7 among them . 28 is locos, and 9e to 9g are wirings.

[0032]

According to the present invention, the resistance formed by ion implantation can be improved against damage that may be caused by various means typified by RIE for forming sidewalls.
High resistance area of two or more diffusion resistance areas with different values
Area where the surface impurity concentration is 1 × 10 ¹⁹ / cm ³ or less
By selectively protecting the region, it is possible to avoid problems such as characteristic deterioration.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a configuration of a semiconductor device (BiCMOS transistor) according to a first embodiment.

FIG. 2 is a cross-sectional view showing a step of Example 1 (1).

FIG. 3 is a sectional view showing a step of the first embodiment (2).

FIG. 4 is a sectional view showing a step of the first embodiment (3).

FIG. 5 is a sectional view showing a step of the first embodiment (4).

FIG. 6 is a sectional view showing a step of the first embodiment (5).

FIG. 7 is a cross-sectional view illustrating a diffusion resistance structure according to a second embodiment.

FIG. 8 is a sectional view showing a conventional technique.

[Explanation of symbols]

 7 Diffusion resistor 3a-3d polysilicon 35 sidewall

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-4-37163 (JP, A) JP-A-2-199868 (JP, A) JP-A-3-198372 (JP, A) Yoichi Akasaka and 3 others , Latest Version VLSI Process Data Handbook, Japan, Science Forum Co., Ltd., March 31, 1990, pages 231-235, supervised by Junichi Nishizawa, VLSI General Encyclopedia, Japan, Science Forum Co., Ltd., March 31, 1988 Date, p. 534 (58) Fields investigated (Int. Cl. ⁷ , DB name) H01L 21/8249 H01L 21/822 H01L 27/04 H01L 27/06

Claims (3)

(57) [Claims] 1. A bipolar transistor and a MOS transistor.
A semiconductor device comprising a transistor on a substrate, wherein the substrate
Ion implantation of two or more diffusion resistance regions with different resistance values on top
And a surface impurity concentration in the diffusion resistance region.
The degree is 1 × 10 ¹⁹ / The area of cm ³ or less other than the gate resistance
Above the resistance region other than the gate resistance
A semiconductor device, wherein a layer is covered with a silicon-based material . 2. The semiconductor device according to claim 1, wherein the silicon-based material is polysilicon, and the polysilicon is formed simultaneously with the polysilicon for forming a gate electrode material of the MOS transistor. 3. The method according to claim 1, wherein the silicon-based material is a refractory metal silicide, and the refractory metal silicide is formed simultaneously with the polysilicon for forming the gate electrode material of the MOS transistor. 3. The semiconductor device according to claim 1.