JPH05189201A - Counter device - Google Patents

Abstract

PURPOSE:To obtain a counter device which can calculate the appearing frequency of the value of input data with simple circuit constitution by individually addition-processing an arbitrary appearing frequency value which is selected in accordance with a value corresponding to input data. CONSTITUTION:When code data of two bits is inputted to a terminal 101, input data is converted into four signal lines 123-126 in a decoder 102. Namely, it is converted into the four signal lines 123-126 in accordance with the value of input data. Namely, one of four outputs becomes high by the value of input data, and other three outputs become low. One among the signal lines 123-126 becoming four inputs is selected in a selector 107 in accordance with the level of the signal lines 123-126, and it is outputted to an adder 108. When input data of two bits is valid, a high level is inputted to a terminal 109 and therefore one is added in the output value of the selector 107 in the adder 108. Only a D-type flip flop (DEF-CEN) outputting the frequency value selected in the selector 107 updates the value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a counter device for counting the appearance frequency of data.

[0002]

2. Description of the Related Art Conventionally, a counter device for counting the appearance frequency of each piece of data of n-bit information has a decoder for decoding 2 ⁿ or less n-bit signals, and each signal output from the decoder. It is composed of a plurality of counters that independently perform a count operation and a count enable control circuit that performs a count operation only when n-bit input data is valid.

FIG. 8 is a circuit block diagram for explaining the configuration of a conventional counter device, which corresponds to the case of 2 bits (n = 2).

In the figure, 801 is a terminal for inputting 2-bit data, 802 is a terminal for inputting a control signal indicating that the 2-bit input data is valid, 803 is a terminal for inputting a clock, and 804 is a counter. A terminal for inputting a clear signal, 805 is a decoder for fully decoding the input 2-bit data, 806 to 809 are AND circuits for controlling the enable signal of the counter, 810 to 81
3 is an m-bit counter with an enable terminal, 814
˜817 are m-bit output terminals for outputting the count results of the m-bit counters 810-813, respectively.

In the configuration thus configured, first, the counter clear signal is first applied to the terminal 804, and the four counters 810 to 813 are all cleared to zero. Next, 2-bit data is input to the terminal 801 and decoded by the decoder 805. Decoder 80
As shown in FIG. 9, 5 is composed of gates G1 to G4. Among the four outputs E0 to E3, only one becomes HIGH according to the value of the 2-bit input data, and the other three.
One is LOW. The output of the decoder 805 is input to one terminal of the 2-input AND circuits 806 to 809, and the 2-bit data valid signal input to the terminal 802 is input to the other input terminal. When the signal is LOW, that is, when 2-bit data is not valid, AN
Since the outputs of the D circuits 806 to 809 are all masked to LOW, even if a clock is applied to the terminal 803 in this state, none of the counters 810 to 813 count up. When 2-bit data is valid, terminal 80
Since the input signal of 2 is HIGH, AND circuits 806 to 8
The output of 09 becomes the same as the output of the decoder 805, and
Only one of the two outputs is HIGH. Therefore, when the enable signal of only one of the four counters 810 to 813 becomes HIGH and a clock is applied to the terminal 803 in this state, only that counter performs the count-up operation.

As described above, the appearance frequency of valid 2-bit data can be counted.

[0007]

Since the conventional counter device is constructed as shown in FIG. 8, it is necessary to prepare counters having the same function for the number of outputs of the decoder, which results in a large circuit scale. was there. Also,
If a conventional counter device is used to obtain a mode value (data having the highest frequency of appearance), there is a problem that the scale of the additional circuit also increases accordingly.

The present invention has been made in order to solve the above-mentioned problems, and a simple addition process is performed by individually adding arbitrary appearance frequency values selected according to values corresponding to input data. An object of the present invention is to obtain a counter device capable of counting the frequency of appearance of the value of input data with a circuit configuration.

[0009]

A counter device according to the present invention corresponds to input data from a plurality of frequency value holding means for holding the frequency of appearance of each value of input data. It has selection means for selecting a frequency value and addition means for adding 1 to the frequency value selected by this selection means.

[0010]

According to the present invention, the adding means adds 1 to the frequency value output from one frequency value holding means selected by the selecting means in accordance with each value of the input data, and the corresponding frequency value holding means is added. The updated frequency value is held, and the appearance frequency can be counted for each value of the input data with a simple configuration.

[0011]

【Example】

[First Embodiment] FIG. 1 is a block diagram for explaining the arrangement of a counter device according to the first embodiment of the present invention.

In the figure, 101 is a terminal for inputting 2-bit code data, 102 is a decoder for decoding the input data and converting it into four signals, and 103 to 106.
Is a D-type flip-flop (DFF-CEN) with clock enable control of m bits each functioning as a frequency value holding means for holding a frequency value, 107 is an m-bit 4-input 1-output selector which is a selecting means, 108 Is m
It is an adder that performs 1-bit and 1-bit addition processing, and functions as the addition means of this embodiment. 109 is a terminal for inputting a control signal indicating that the 2-bit data input from the terminal 101 is valid, 110 is a terminal for inputting a clock, and 111 is a terminal for inputting a signal for clearing all frequency values to zero. Is.

In the counter device thus constructed, the clear signal is first applied to the terminal 111, and the clear signal is applied to the terminal 111.
The two DFF-CENs 103-106 are all cleared to zero. The four DFF-CENs 103 to 106 are D-type flip-flops having a holding function and perform the same operation as a normal D-type flip-flop when a clock enable terminal (hereinafter abbreviated as CEN terminal) is at a high level. When the CEN terminal is at the LOW level, the input data is not taken in and the previous output data is continuously held even if the clock is applied. Equivalently, it can be represented by the circuit shown in FIG.

FIG. 2 is a circuit block diagram showing an example of an equivalent circuit of the counter device shown in FIG.

In the figure, 201 is a data input terminal, 2
02 is the above-mentioned CEN terminal, 203 is a clock input terminal,
Reference numeral 204 is a data output terminal, 205 is a normal D-type flip-flop (abbreviated as DFF), 206 is a selector, and 207
Is a clear signal input terminal. When the input signal of the CEN terminal 202 is LOW level, the output data of the DFF 205 becomes the input data of the DFF through the selector 206. Therefore, even if the clock is applied from the terminal 203, the value of the output data does not change. is there.

Now, the four DFF-CENs shown in FIG.
When 103 to 106 are cleared and the frequency values are all set to zero, 2-bit code data is input to the terminal 101. The input data is received by the decoder 102.
It is converted into four signal lines 123 to 126. Decoder 1
The configuration of 02 is almost the same as that of the decoder shown in FIG. 9, and only one of the four outputs is HI depending on the value of the input data.
It becomes GH and the other three become LOW level.

For example, when the 2-bit input data is "00", the signal line 123 in FIG. 1 becomes HIGH and the signal lines 124 to 126 become LOW. Input data is "0
The signal line 12 for each of "1", "10", and "11"
4-126 become HIGH respectively. In the selector 107, the signal lines 113 which become four input signals according to the levels of the signal lines 123 to 126 corresponding to the output signals of the decoder.
1 to 116 are selected and output to the adder 108. Input data “00”, “01”, “10” “1”
The signal lines 113 to 116 are selected for "1".
When 2-bit input data is valid, H
Since the IGH level is input, the adder 108 adds “1” to the output value of the selector 107. On the contrary, when the 2-bit input data is not valid, the input level of the terminal 109 becomes LOW, so that the adder 108 does not perform addition and the value output from the selector 107 is the value output from the adder 10.
8 is passed as it is, and the value is output. That is,
In short, it means that the frequency value corresponding to the 2-bit input data is selected by the selector 107 and "1" is added to the frequency value. Only the DFF-CEN that outputs the frequency value selected by the selector 107 updates the value, and the other DFF-CEN updates the value so that it retains the previous value. Only the CEN terminal of the DFF-CEN. A clock is input from the terminal 110 in a state where the level is HIGH and the other DFF-CEN levels are LOW. Even when the 2-bit input data is not valid, that is, when the signal input from the terminal 109 is at the LOW level, the frequency value selection and the frequency value update operation in DFF-CEN are performed, but the updated value is the same. Since it exists (because "1" is not added by the adder 108), it does not pose a problem. As described above, the appearance frequency of each 2-bit input data can be counted. [Second Embodiment] FIG. 3 is a block diagram illustrating the structure of a counter device according to a second embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals.

In the figure, 301 is a D-type flip-flop (DFF) for delaying 2-bit input data by 1 clock, and 302 is output data (2 bits) of DFF 301 from 2-bit data input from a terminal 101.
, A m-bit DFF for holding the frequency value for each 2-bit input data, and 107, 310 to 312 signal lines indicating the frequency value according to the output of the decoder 102. A selector for selecting a predetermined value from 113 to 116.

This embodiment is substantially the same as the first embodiment in that the appearance frequency for each code of 2-bit input data is counted, but only the specific DFF having a frequency value immediately after the update (the book The embodiment is slightly different in that it is output from the DFF 303).

The operation of this embodiment will be described below with reference to FIG.

First, a clear signal is first applied to the terminal 111, and the DFFs 303 to 306 and the DFF 301 are all cleared to zero. Next, the first 2-bit input data is input to the terminal 101. The input data is input to the subtractor 302, where the output value of the DFF 301 is subtracted, but since the output value is “0”, practically nothing is subtracted, and the value 2 input to the terminal 101 is input. The bit data is directly output from the subtractor 302 and input to the decoder 102. The decoder 102 decodes the input 2-bit data into four signals and outputs them to the selectors 107, 310 to 312. Decoder 102
Selectors 107, 31 when the 2-bit input of is "00"
The outputs of 0 to 312 are signal lines 113, 114 and 1 respectively.
15 and 116, and the same outputs when the 2-bit input is “01” are the signal lines 114, 115, 116 and 113. Hereinafter, each time the value of the 2-bit input of the decoder 102 increases by one, the four selectors 107, 310-3 are selected.
There is a relationship in which the 12 outputs are shifted one by one. The outputs of the selectors 310 to 312 are the same as those of the DFFs 304 to 3
06, the output value of each selector 107, 310 to 312 after the application of the clock is the corresponding DFF3.
It is held in 03-306.

On the other hand, for the signal selected by the selector 107, exactly the same processing as that described in the first embodiment is performed by the adder 108 and held by the DFF 303. Four
Since the contents held in the two DFFs 303 to 306 are shifted according to the value of 2-bit data input from the terminal 101, a process of returning the amount shifted by a certain data input after one clock is newly added in the present embodiment. Will be needed.

For example, when a 2-bit input “00” is used as a reference, the output of the DFF is 3 as a whole at “11” input.
Shift two (this is the positive direction). In order to restore this after one clock, three shifts must be made in the negative direction after one clock. Actually, one clock later, new 2-bit data is input to the terminal 101, so a new shift (this shift amount is S) is generated based on this data, and the total is "S-3". Must be done one clock later. The blocks for calculating this shift amount are the DFF 301 and the subtractor 302. By the way, in the calculation of "S-3", when the shift amount S is smaller than "3", the calculation result becomes negative. For example, when S = 2, S-3
= -1, and a process of shifting one in the minus direction is required. However, a shift of "1" in the minus direction is equivalent to a shift of "3" in the plus direction, so that the calculation result is "3", that is, 2
It suffices if the value “11” is output as a bit code. Such an operation can be realized by an operation of only the lower 2 bits ignoring borrow.

As described above, the appearance frequency value of each code of 2-bit input data is counted while being shifted among the DFFs 303 to 306. In the present embodiment, the selector 107 and the selectors 310 to 310.
The decoder 102 can be omitted by changing the configuration of 312. That is, a 2-input / 1-output selector is
This is because the binary code before decoding can be used as it is as the control signal in the case of using three selectors of one input and one output. [Third Embodiment] FIG. 4 is a block diagram for explaining the configuration of a counter device showing a third embodiment of the present invention. The same parts as those in FIG. This corresponds to the case of a device for detecting the mode in statistics, that is, the mode.

In the figure, 401 is DFF-CEN,
The maximum frequency value is held and the value is output to the comparator 404. Reference numeral 402 denotes a DFF-CEN, which holds a mode and outputs the mode via a terminal 403.

When a clear signal is applied from the terminal 111 and all frequency values are cleared to zero, the DFF-CE
N401 is also cleared to zero at the same time. At this point, the output of DFF-CEN 401 is already equal to the maximum frequency value (zero). Be sure to adder 1 to count up the frequency value
Since it is performed at 08, the output of the adder 108 is constantly monitored, and if the maximum value is held, the held value always matches the maximum frequency value. Therefore, the adder 108
Output, that is, the DFF-CEN40 which is the maximum value of the frequency value for the latest input data and the past frequency value.
If the output of the adder 108 is larger, the comparator 404 outputs a HIGH level, the output of the adder 108 is output to the DFF-CEN 401, and the 2-bit input data at that time is output to the DFF. -Import to CEN402. As a result, the maximum frequency value and the mode are updated. On the contrary, if the output of the adder 108 is smaller, the comparator 404 outputs the LOW level, and the past maximum frequency value (which is also the current maximum frequency value) and the mode are continuously maintained. Further, when the output of the adder 108 is equal to the past maximum frequency value, the output level of the comparator 404 is HI.
GH or LOW may be used, but if HIGH is set to be output, the data having the same appearance frequency is given priority to the one that appears last. In such a case, the mode may be detected with the configuration shown in FIG.

FIG. 5 is a block diagram for explaining another configuration of the counter device shown in FIG. 4, and the same components as those in FIG. 4 are designated by the same reference numerals.

In the figure, 501 is a coincidence detector, and the input of the adder 108 is one input.

In the counter device configured as described above, the maximum frequency value can be detected by referring to the output of the adder 108, but by referring to the input instead of the output of the adder 108. Also the maximum frequency of detection is possible. However, in principle, the input value of the adder 108 cannot be larger than the output of the DFF-CEN 401, which is the maximum frequency value in the past, and the maximum value of the input value is equal to the output value of the DFF-CEN 401. Then, when the values are equal, the maximum frequency value is updated. Because the input of the adder 108 and the DFF-CEN
The fact that the output of 401 is equal means that the adder 10
8 is sometimes larger than the output of the DFF-CEN 401 (the input of the terminal 109 is HIG.
If it is H, it will be incremented by one, but if the input is LOW, it will remain the same). Therefore, the adder 108
Is compared with the output of DFF-CEN401, and if their values match, C of DFF-CNN401 and 402
The EN terminal is set to HIGH level to update the maximum frequency value and the mode.

The coincidence detector 501 outputs a HIGH level when the two values completely coincide with each other.
Since the bit data coincidence detector is composed of EX.NOR1 to 4 and an AND gate AND as shown in FIG. 6, for example, the circuit scale is much smaller and the delay is smaller than that of an ordinary comparator.

In the above embodiments, the input data is all 2 bits, but the input data is 1 bit and the write address and the read address of the memory are made to correspond to each other, so that the random access memory is of the first-in-first-out type. It can also be used as an address generator when used with a memory (FIFO memory).
Hereinafter, the example will be described. For convenience of explanation, the operation will be described as an address generator from the beginning.
The essence is a counter device. [Fourth Embodiment] FIG. 7 is a block diagram for explaining the arrangement of a counter device according to the fourth embodiment of the present invention.

In the figure, 701 is a terminal for inputting a control signal for selecting a write address and a read address, 702 is a control signal input terminal for counting up the address, 703 is a clock input terminal, and 704 is an address. Clear input terminal, 705
706 is an m-bit DFF that holds a write address and a read address, 707 and 708 are m-bit 2-input 1-output selectors, and 709 is the selector 707.
An adder for adding the m-bit address output from the terminal to the 1-bit signal input from the terminal 702, 710 is a 1-bit DFF that delays the signal input from the terminal 701 by 1 clock, and 711 is an exclusive OR element (EXOR gate) and 720 are m-bit address output terminals.

In the above structure, first, the terminal 70
4, the clear signal is applied to DFFs 705, 706, 7
10 is cleared. At this point, the DFF holds the write address and the DFF 706 holds the read address. Here, in order to generate an address for writing data to the FIFO memory, first, LOW (meaning selection of a write address) is applied to the terminal 701, and the terminal 70
Input HIGH to 2. This causes the exclusive OR element 711 to output a LOW level, which causes the selector 707 to output the output of the DFF 705 to the selector 708.
Then, the output of the DFF 706 is selected. In this case, the output of both selectors 708 is zero. Selector 70
The output of 8 is sent to the DFF 706, and the output of the selector 707 is added with “1” by the adder 709.
Sent to 05. Here, when a clock is applied from the clock input terminal 703, the DFFs 705, 706, 710
Each captures the data, and each is "1",
"0" and "0" are output. The output "1" of the DFF 705 is output to the address output terminal 720, which is used as a write address. Next, just before FI
A read address for reading the data written in the FO memory is generated. In this case, HIGH is input to both the terminal 701 and the control signal input terminal 702. As a result, the exclusive OR element 711 outputs HIGH, which causes the selector 707 to output the DFF 706.
The output of the DFF 705 is selected by the selector 708.
The output of the DFF 706 is a read address whose value is "0", and when it is output from the selector 707, "1" is added by the adder 709 and the result is sent to the DFF 705. Here, when a clock is applied, a read address having a value of “1” is output from the control signal input terminal 702 through the DFF 705. At this time, the write address is output from the DFF 706. Therefore, the output of the write address and the output of the read address are exchanged one clock before. Further, if the write address is to be output from the terminal again after one clock, the input of the terminal 701 is set to LOW. As a result, an operation is performed with respect to the HIGH level output from the DFF 710, the exclusive OR element 711 outputs the HIGH level, the addresses are exchanged, and the write address is output from the address output terminal 720 after the clock is applied. Is output.
At that time, if the input of the control signal input terminal 702 is set to the HIGH level, the write address is from 1 to 2
However, if the input is LOW level, the address value remains "1".

As described above, the address for using the random access memory as the FIFO memory can be efficiently generated. Although the adder 709 is provided between the selector output and the DFF input in this embodiment, it may be provided between the DFF output and the selector input. At that time, the count-up signal of the address input from the control signal input terminal 702 is delayed by one clock in the DFF and then input to the adder 709. As a result, in the present embodiment, writing and reading were started from the address value "1", but it is possible to start from the address value "0".

[0035]

As described above, according to the present invention, the adding means adds 1 to the frequency value output from one frequency value holding means selected by the selecting means according to each value of the input data. Since the updated frequency value is held in the frequency value holding means, the appearance frequency can be counted for each value of the input data with a simple configuration. Therefore, the counter mechanism applicable to various uses can be greatly simplified, and the mode having the maximum frequency value can be detected with a few additional circuits.

[Brief description of drawings]

FIG. 1 is a block diagram illustrating a configuration of a counter device according to a first embodiment of the present invention.

FIG. 2 is a circuit block diagram showing an example of an equivalent circuit of the counter device shown in FIG.

FIG. 3 is a block diagram illustrating a configuration of a counter device according to a second embodiment of the present invention.

FIG. 4 is a block diagram illustrating a configuration of a counter device according to a third embodiment of the present invention.

5 is a block diagram illustrating another configuration of the counter device shown in FIG.

6 is a circuit block diagram showing an example of the coincidence detector shown in FIG.

FIG. 7 is a block diagram illustrating a configuration of a counter device according to a fourth embodiment of the present invention.

FIG. 8 is a circuit block diagram illustrating a configuration of a conventional counter device.

9 is a circuit block diagram showing an example of the decoder shown in FIG.

[Explanation of symbols]

 102 Decoder 103 DFF-CEN 104 DFF-CEN 105 DFF-CEN 106 DFF-CEN 107 Selector 108 Adder

Claims (1)

[Claims] 1. A plurality of frequency value holding means for holding the appearance frequency of each value of input data, a selection means for selecting a frequency value corresponding to the input data from each frequency value holding means, and this selection. A counter device comprising: an addition unit that adds 1 to the frequency value selected by the unit.