JPH05188925A - System and device for data input - Google Patents

Abstract

PURPOSE:To provide the data input device and a character generation device which are suitable for IC-implementation. CONSTITUTION:This device is provided with an FIFO 2 temporarily stored with input data, an FIFO controller 1A which controls it, and an arithmetic processing part 3 which reads the data out of the FIFO 2 and performs arithmetic processing; and an input request for data from the FIFO controller 1A and an input request for data from the arithmetic processing part 3 are ANDed to make an input request for data. Consequently, the arithmetic processing means 3 needs not be placed in a wait state and efficient data input and high- speed arithmetic processing are provided in the character generating device.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a character / graphics generator in the field of computer graphics, and more particularly to data in a character / graphics generator for converting contour data of a character / graphic represented in a vector format into raster format data. Input device.

[0002]

2. Description of the Related Art There is a method of converting an outline font into a dot font as a method of outputting characters of a plurality of character sizes and characters such as rotation and italics. The outline font is the coordinates of points on the outline of a character. Use this outline font as a character font
The coordinate conversion operation called affine transformation is performed according to the designated output size in the OM or the external storage device, and in order to beautifully output the curved line of the character, the coordinate is converted into the coordinate on the curved line by the curve interpolation and then output. In addition, a straight line is drawn between the coordinate points that have undergone coordinate conversion to generate the outline of the character,
There is one that fills the inside and outputs.

FIG. 3 shows a Japanese Patent Application No. 2 filed by the applicant previously.
No. 19052, “Character generator”, character generation L for performing a series of processes for converting the coordinate data forming the outline font data into bitmap data.
This is a system configuration example using the SI and outline font processor 15.

A system bus 17 including an address bus, a data bus and a control bus includes a CPU 12 and a DMAC.
13, a font ROM 14, and an outline font processor 15 are connected. Here, the CPU interface 16 in the outline font processor 15 has a FIFO 2 for inputting font data, and the outline font data is transferred from the font ROM 14 to the FIFO 2 by the DMAC 13 or the CPU 12. The outline font processor 15 sequentially performs arithmetic processing on the data input to the FIFO 2.

[0005]

In the above-described conventional character generator, as shown in FIG. 7, the outline font data 4 is temporarily stored in FIFO 2 and the outline font data 4 is read from the FIFO 2 to obtain the outline font data. The arithmetic processing unit 3 for executing the expansion processing and the FIF
Outline font data 4 depending on the free status of O 2.
Of the FIFO controller 1B for requesting the input of the FIFO and controlling the writing and reading of the FIFO 2.

The FIFO controller 1B sends a DR to the DMAC 13 when the empty state of the FIFO 2 becomes completely empty.
The EQ signal 21 is activated and the outline font data 4 is requested to be input. FIFO controller 1B
Receives the DACK signal 22 from the DMAC 13 to enable the FIFO
Write the outline font data 4 into 2.
Reference numeral 19 is a write address of the FIFO 2.

The arithmetic processing unit 3 includes a FIFO controller 1B.
, The READ signal 25 is activated, and if it is readable, the outline font data 4 is read.
20 is a read address of the FIFO 2. If the data cannot be read, the R_BUSY signal 26 becomes active and the arithmetic processing unit 3 enters a waiting state.

The structure of the input outline font data 4 is shown in FIG. The outline font data 4 is composed of coordinate data x and y representing coordinate points on the outline of the character and flag data F indicating attributes of the coordinate points and a series of coordinate point groups.

The operation of the FIFO 2 will be described with reference to FIG. The FIFO 2 has a write address 19 and a read address 20, both of which are in the same address position in the initial state of FIG. FIG. 5B shows how the outline font data 18 is written, and the data F, x0, y0, F, x1 are FIFO2.
Write address 19 indicates the address to be written next. In FIG. 5C, the data is written in all the areas of FIFO 2, and the FIFO is written after the writing is completed.
2 shows the state in which the data F, x0, and y0 have been read.

Next, FIG. 6 shows a processing flow of the arithmetic processing unit 3 for reading the outline font data 4 from the FIFO 2. The arithmetic processing unit 3 executes outline font expansion processing including affine transformation.
When the coordinate data x and y are input, the arithmetic processing becomes possible, and the next outline font data 4 is not read from the FIFO 2 until the arithmetic processing is completed. In the flow chart, the outline font data 4 is read from the FIFO 2 at 6 and it is determined whether it is flag data or coordinate data. If it is the coordinate data, the outline font data 4 is read from the FIFO 2 at 7 and x, y The arithmetic processing 11 is executed when the data are collected. If it is flag data, if the flag data does not indicate the end, the outline font data 4 is read from the FIFO 2 at 8 and 9, and the arithmetic processing 11 is executed when the x and y data are complete. ..

FIGS. 5A to 5E show a pattern in which the outline font data 18 shown in FIG. 4 is written in the FIFO2, which is a readable FIFO.
Focusing on the pattern when the remaining amount of 2 becomes 3 words, any one of (a) to (e) is obtained. Next FIFO 2
When the arithmetic processing unit reads the outline font data 4 from the FIFO 2 without writing the outline font data 4 to the FIFO 2, the remaining 1 of the FIFO 2
At the time of reading the word, in the case of (a) and (c),
The arithmetic processing unit can execute arithmetic processing because the x and y data are aligned.
Since the data of 1 is not prepared, the next outline font data 4 is written in the FIFO 2, and the arithmetic processing unit is in a waiting state until the x and y data are read.
However, in order to avoid the above waiting state, the FIFO controller 1B requests the input of outline font data 4 before the FIFO 2 is exhausted, and the FIFO
Although the outline font data 4 can be written to O, the efficiency of writing the outline font data 4 to the FIFO decreases. That is, in order to improve the data writing efficiency on the side of writing the outline font data 4 to the FIFO, it is necessary to write the outline font data 4 once for each number of stages of the FIFO.
Causes a wait state on the side reading 4. On the contrary, in order not to cause the waiting state, the writing efficiency of the outline font data 4 is lowered.
This is a problem in a system that cannot have a large number of O stages. Therefore, after the arithmetic processing unit reads out a series of outline font data 4 required for arithmetic processing from the FIFO 2,
It is necessary to request the input of the outline font data 4 to FO 2 and to maximize the free space of FIFO 2. Writing to the FIFO 2 is performed during the arithmetic processing, and thus the throughput of the entire system does not decrease.

An object of the present invention is to use a limited data input FIFO having a relatively small number of stages to increase the maximum data write efficiency on the write side of the FIFO,
It is an object of the present invention to provide a data input method and a device thereof that do not cause a waiting state on the read side of the FO.

Another object of the present invention is to provide a data input method and an apparatus therefor suitable for LSI implementation.

[0014]

In order to achieve the above object, a data input device according to the present invention comprises a FIFO for temporarily storing input data, and an arithmetic operation for sequentially reading data from the FIFO and performing arithmetic processing. Processing unit and FIFO
Has a FIFO controller that requests data input depending on the vacant state of the FIFO and controls writing and reading of the FIFO, and inputs data by the logical product of the data input request from the FIFO controller and the data input request from the arithmetic processing unit. It is a request.

In the data input device, the data input method is a data input request condition from the arithmetic processing unit, in which the arithmetic processing unit reads out a series of data necessary for arithmetic processing from the FIFO and then requests data input. Is.

In the data input device, the data input method requests data input when the remaining amount of valid data read from the FIFO is n words or less as a data input request condition from the FIFO controller. is there.

[0017]

According to the above-mentioned means, the data write request is made to the data input FIFO by requesting the data input by the logical product of the data input request from the FIFO controller and the data input request from the arithmetic processing unit. In
The data input for the maximum number of FIFO stages can be written to the FIFO by one DMA transfer, and further, on the side reading the data from the FIFO, a series of data necessary for the arithmetic processing can be read without fail. There is no need to put the processing unit in a waiting state, and it is expected that highly efficient data input and calculation processing can be speeded up.

Further, the above means does not increase the circuit scale of the FIFO controller and the arithmetic processing section,
It can be achieved with a small change.

Further, in a system which cannot have a large number of stages of FIFO, the FIFO is effectively used and the throughput of the entire system is improved, so that it is suitable for LSI implementation.

[0020]

EXAMPLES Examples of the present invention will be described in detail below.

FIG. 1 shows a block diagram relating to outline font data input of a character generator to which the present invention is applied. It should be noted that the present device is not limited to this, and may be a single element integrated into an LSI as a microcomputer peripheral device or a systemized device.
Reference numeral 2 is a FIFO for temporarily storing the input outline font data 4. The number of stages of FIFO 2 is 8 words as shown in FIG. 1A is a FIFO controller, and when the readable outline font data 4 in FIFO 2 becomes 2 words or less,
Activates the DREQ1 signal 23 and requests the input of outline font data 4 to FIFO 2. 3 is
This is an arithmetic processing unit for converting the outline font data 4 into dot font data by performing arithmetic processing such as affine transformation, Bezier curve interpolation, line generation, painting, and BitBLT. Reference numeral 19 is a write address of FIFO 2, and 20 is a read address.

Further, the block configuration described above may be replaced with the FIFO 2 and the FIFO controller 1A by a memory 28 and a memory controller 27 as shown in FIG. Further, the memory 28 and the memory controller 27 may be a register file and a register file controller.

Here, the condition that the arithmetic processing unit 3 can execute the arithmetic processing is that the outline font data 4 necessary for the affine transformation, which is the first arithmetic operation, is read from the FIFO 2. Affine transformation is expressed by the following arithmetic expression,

[0024]

[Mathematical formula-see original document] x '= ax + by + e (expression of affine transformation) y' = cx + dy + f where a, b, c, d, e, f: affine matrix data The coordinate conversion is performed. Therefore, the arithmetic processing unit
3 starts the arithmetic processing when the coordinate data x and y are read from the FIFO 2, and the FIFO 2 continues until the arithmetic processing ends.
Does not read data from. That is, the arithmetic processing unit 3
Activates the DREQ2 signal 24 after reading the coordinate data y and requests the input of the outline font data 4 to the FIFO 2. Furthermore, the DREQ1 signal 23 from the FIFO controller 1A and the DRE1 from the arithmetic processing unit
By taking the logical product 5 of the Q2 signal 24 and setting it as the DREQ signal 21, the DMAC 13 is actually requested to input the outline font data 4 to the FIFO 2.

In FIG. 2, the arithmetic processing unit 3 displays the DREQ2 signal.
The processing flow until activating 24 and requesting input of outline font data 4 to FIFO 2 is shown. In 6, outline font data from FIFO 2
Lead 4 It is determined whether the read outline font data 4 is flag data or coordinate data. If the read outline font data 4 is coordinate data, the outline font data 4 is read from the FIFO 2 at 7 and after the x and y data are complete, 10
Activates the DREQ2 signal 24 and requests the input of outline font data 4 to the FIFO2. After that, the arithmetic processing 11 is executed. If it is flag data, the flag data is outline font data 18
If it does not indicate the end of, the outline font data 4 is read from the FIFO 2 at 8 and 9, and the DREQ2 signal 24 is activated at 10 after the data x and y are completed, and the outline font data 4 to the FIFO 2 is read.
Request input. After that, the arithmetic processing 11 is executed.

On the other hand, FIGS. 5A to 5E show patterns in which the outline font data 18 shown in FIG. 4 is written in the FIFO 2, as described above, and can be read. Focusing on the pattern when the remaining amount of FIFO 2 becomes 3 words, it becomes any one of (a) to (e). Therefore, the arithmetic processing unit 3 activates the DREQ2 signal 24 after reading the data y.
In the cases of (a) and (c), when the remaining amount of readable FIFO 2 is 0 word, that is, when the FIFO 2 is completely empty, the FIFO controller 1A outputs the DREQ1 signal 23.
Is activated, and as a result, the DREQ signal 21 becomes active, requesting the DMAC 13 to input the outline font data 4 to the FIFO 2. Therefore,
The arithmetic processing unit 3 can execute arithmetic processing, and the next input of the outline font data 4 to the FIFO 2 can write 8 words of data corresponding to the number of stages of the FIFO 2 at a time while executing the arithmetic processing. .. Also, (b)
In the case of (e), the remaining amount of readable FIFO 2 is 1
When the word is reached, the FIFO controller 1A sends the DR
The EQ1 signal 23 is activated, and as a result, the DREQ signal 21 is activated, and the DMAC 13 is activated by the FIF.
Requests input of outline font data 4 to O 2. Therefore, the arithmetic processing unit 3 can execute the arithmetic processing, and the next input of the outline font data 4 to the FIFO 2 can write 7 words of data at one time during the execution of the arithmetic processing. In the case of (d), when the remaining amount of readable FIFO 2 becomes 2 words, the FIFO controller 1A activates the DREQ1 signal 23, and as a result, the DREQ signal 21 becomes active and the DMAC 13 is activated. On the other hand, it requests the input of outline font data 4 to FIFO 2. Therefore, the arithmetic processing unit 3 can execute arithmetic processing, and the next FI
The input of the outline font data 4 to the FO 2 can write 6 words of data at a time while executing the arithmetic processing.

From the above, the FIFO controller 1A activates the DREQ1 signal 23 when the remaining readable FIFO 2 becomes 2 words or less.
It can be applied to all the cases of FIGS. That is, the arithmetic processing unit 3 can execute the arithmetic processing without waiting by reading a series of outline font data 4 necessary for the arithmetic processing from the FIFO 2, and the outline font data 4 In the input of, data of 6 words at the maximum can be written at once from the maximum of 8 words of the number of stages of FIFO 2 during execution of the arithmetic processing.

[0028]

In the prior art, the FIFO controller requests input of data to the FIFO due to the free state of the FIFO for data input, and particularly when the number of stages of the FIFO cannot be large, the efficiency of writing data to the FIFO is improved. When the FIFO became empty in order to raise the data, data was being written, so a waiting state was caused in the arithmetic processing unit that reads data from the FIFO and performs arithmetic processing.

On the other hand, according to the present invention, on the write side of the FIFO, it is possible to write the data for the maximum number of stages of the FIFO at a time, and on the read side of the FIFO, the series of data necessary for the arithmetic processing must be used. Since the data can be read, highly efficient data input and high-speed arithmetic processing can be realized without putting the arithmetic processing unit in a waiting state.

[Brief description of drawings]

FIG. 1 is a block diagram of a data input device.

FIG. 2 is a flowchart of an arithmetic processing unit.

FIG. 3 is a system configuration diagram of an outline font processor.

FIG. 4 is an explanatory diagram of outline font data.

FIG. 5 is an explanatory diagram of a font input FIFO.

FIG. 6 is a flowchart of a conventional arithmetic processing unit.

FIG. 7 is a block diagram of a conventional data input device.

FIG. 8 is a block diagram of a data input device.

[Explanation of symbols]

1A ... FIFO controller, 2 ... FIFO, 3 ... Arithmetic processing unit, 4 ... Outline font data, 5 ... AND
Gate, 12 ... CPU, 13 ... DMAC, 14 ... Font ROM, 15 ... Outline font processor, 1
6 ... CPU interface.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Kazuko Hasegawa, Kazuko Hasegawa, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa, Ltd., Microelectronics Device Development Laboratory, Hitachi, Ltd. (72) Hiroshi Wada, 292 Yoshida-cho, Totsuka-ku, Yokohama, Kanagawa House number Hitachi, Ltd. Microelectronics Device Development Laboratory (72) Inventor Takashi Miyamoto 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stock company Hitachi Ltd. Musashi factory

Claims (3)

[Claims] 1. A storage element for temporarily storing input data, an arithmetic processing section for sequentially reading data from the storage element and performing arithmetic processing, and a storage element which requests data input depending on an empty state of the storage element and stores the data. In a device including a storage element control unit that controls writing and reading of elements, it is possible to request data input by a logical product of a data input request from the storage element control unit and a data input request from the arithmetic processing unit. Characteristic data input device. 2. The data input method according to claim 1, wherein, as a data input request condition from the arithmetic processing unit, the data processing is performed after the arithmetic processing unit reads out a series of data necessary for arithmetic processing from the storage element. A data input method characterized by requiring input. 3. The data input method according to claim 1, wherein the data input request condition of the storage element control unit is such that when the remaining amount of valid data read from the storage element is n words or less. A data input method characterized by requiring input.