JP3238202B2 - Character / graphic generating apparatus and information processing apparatus - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to character / graphic data in dot format (hereinafter referred to as bitmap data) from contour information of character / graphic represented in vector format (hereinafter referred to as vector data). , And outputs the bitmap data by an output engine such as a laser printer (hereinafter, referred to as LP) or a thermal transfer printer (hereinafter, referred to as TTP).

[0002]

2. Description of the Related Art Conventionally, in a character / graphics generator,
Bitmap data is generated from the vector data, stored in a built-in memory, and the bitmap data stored in the built-in memory is transferred to the outside.

At this time, enlargement, reduction,
Coordinate conversion such as italic and rotation can be performed. In such a case, coordinate values (X, Y) and coordinate conversion parameters a, b, and c given from a central processing unit (hereinafter referred to as CPU) can be obtained. From c, d, tx, and ty, X '= a
X + bY + tx and Y '= cX + dY + ty are calculated to perform coordinate conversion. here,
X ′ and Y ′ are X and Y coordinate values after coordinate conversion. A, b, c, d, tx, and ty are elements of a 3 × 3 coordinate transformation matrix, where a is a 1 row and 1 column element, b is a 1 row and 2 column element, and c is a 2 row and 1 column element , D is a 2-row, 2-column element, tx is a 3-row, 1-column element, and ty is a 3-row, 2-column element.

To generate bitmap data having a size larger than the capacity of the built-in memory, the vector data is divided into several areas, and bitmap data is generated for each vector data in each area. Has been transferred to.

At this time, the area is divided by the CPU,
Data transfer unit from internal memory only in X direction (for example,
(In units of words) or in arbitrary integer units (in units of bits) in both the X and Y directions.

Further, when transferring bitmap data stored in the built-in memory to the outside, the address update is transferred while simply incrementing the address. In general, the transfer destination is an external memory. After being transferred to the external memory, the data is further transferred to the output engine by the CPU.

[0007]

In the above prior art, since the coordinate conversion is always performed by performing an operation of X '= aX + bY + tx, Y' = cX + dY + ty, an address assignment different from the address assignment of the built-in memory is taken. There has been a problem that the range of application is narrow because the application to a wide range of output engines is not considered.

For example, the address assignment of the built-in memory and the address assignment of the LP used as the output engine are as shown in FIG. 5, and the address assignment of the TTP used as the output engine is as shown in FIG. If the LP is used as an output engine, X ′ = aX + bY + tx, Y ′ = cX +
By performing coordinate conversion by performing an operation of dY + ty, LP bitmap data as shown in FIG. 5 can be generated. However, when TTP is used as an output engine, X ′ = aX + bY + tx, Y '
= CX + dY + ty, the coordinates must be converted, and then the data must be converted into TTP bitmap data as shown in FIG. 4 by software processing or a dedicated LSI.

In the above prior art, the bitmap data stored in the built-in memory is transferred to the outside while incrementing the address. Therefore, the address assigned to the output engine is different from that of the built-in memory. There has been a problem that application is not considered in a wide range, and the application range is narrow.

For example, in addition to the LP address assignment shown in FIG. 5, there is also an LP address assignment shown in FIG.

Therefore, when an LP having an address assignment as shown in FIG. 5 is used as an output engine, the output is the same as the address assignment of the built-in memory, so that the LP is stored in the built-in memory while incrementing the address. Bitmap data may be transferred, but when an LP having an address assignment as shown in FIG. 6 is used as an output engine, bitmap data stored in a built-in memory is transferred while incrementing the address. For this purpose, the address allocation of the built-in memory must be performed as shown in FIG.

According to the above-mentioned prior art, when dividing vector data into several regions, an arbitrary integer unit (bit unit) other than a data transfer unit (for example, a word unit) from the built-in memory is used in both the X and Y directions. When the bitmap data stored in the internal memory is transferred,
No consideration is given to the formation of a blank portion in which no data is generated in a word, and there is a problem that some processing is required to remove the blank portion.

As described above, in the prior art, the character / graphic generator must be designed differently in accordance with the address assignment of the output engine, and in the information processing apparatus equipped with one character / graphic generator, , Could not be applied to various output engines.

An object of the present invention is to provide without increasing the circuit significantly, the information processing apparatus you can conduct applicable coordinate transformation to a variety of output engine.

Another object of the present invention is to provide an information processing apparatus capable of performing area division applicable to various output engines without significantly increasing the number of circuits.

It is a further object of the present invention to provide a character / graphics generating apparatus and an information processing apparatus capable of performing data transfer applicable to various output engines without significantly increasing the number of circuits. is there.

[0017] To solve one of the above objects, the present invention
In one aspect, a character / graphics generator and a central processing unit
Device (hereinafter referred to as CPU) and one or more output engines
And an information processing device comprising:
Information according to the address assignment of the output engine used
Information providing means for providing the
For example, the characters and graphics generator, the contour information of the characters and graphics represented in vector form (hereinafter, referred to as vector data)
Coordinate conversion means for performing coordinate conversion, and generating means for generating dot-format character / graphic data from the vector data subjected to the coordinate conversion by the coordinate conversion means ,
The coordinate conversion means is provided with a coordinate conversion function of performing any one of two or more types of coordinate conversion on the vector data using a coordinate conversion parameter given from the outside, and provided by the information providing means. It was based on the information, and characterized by having a coordinate transformation selection function to select either one of the two or more coordinate transformation
An information processing apparatus is provided.

[0018]

[0019]

[0020]

[0021]

[0022]

[0023]

[0024]

[0025]

[0026]

[0027]

According to the information processing apparatus of one embodiment of the present invention,
The information providing means of the central processing unit
The information corresponding to the address assignment of the power engine
・ Coordinates of the character / graphic generator given to the graphic generator
The coordinate transformation selection function of the transformation means is controlled by the information provision means.
Based on the information given, two or more types of coordinate transformation
Select one of them.

[0028]

[0029]

[0030]

[0031]

[0032]

[0033]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a configuration diagram of an information processing apparatus to which the character / graphic generation apparatus of the present invention is applied.

In FIG. 1, reference numeral 1 denotes a CPU for controlling the entire information processing apparatus; 2, a font ROM for storing vector data; 3, an external memory for storing bitmap data; An output engine 5 for displaying is a character / graphic generating device for performing a character / graphic generating process.

The CPU 1 transfers the vector data stored in the font ROM 2 to the character / graphics generating device 5, and the character / graphics generating device 5 generates bitmap data from the vector data and transfers it to the external memory 3. I do.
Then, the CPU 1 transfers the bitmap data on the external memory 3 to the output engine 4 to perform printing / display.

FIG. 2 is a block diagram of the character / figure generator 5 of the present embodiment.

In FIG. 2, reference numeral 201 denotes a CPU interface circuit for controlling an interface with the CPU 1, which exchanges vector data, bitmap data, and addresses by using a data bus and an address bus, and also outputs a chip select signal (CSN). ), Register read /
Write signal (R / WN), data complete signal (D
The start / stop of each circuit is controlled by exchanging signals such as CN), an interrupt request signal (IRQN), a data request signal (DREQN), and a data request permission signal (DACKN).

Reference numeral 202 denotes a font input FIFO for storing the vector data transferred from the CPU 1;
Is a coordinate conversion circuit for performing coordinate conversion on the vector data stored in the font input FIFO 202; 204, a FIFO-A for storing the data after the coordinate conversion;
A curve interpolation circuit for performing curve interpolation on the data stored in the FIFO-A 204, a FIFO-B 206 for storing the data subjected to the curve interpolation, and a reference numeral 207, a straight line between two points of the data stored in the FIFO-B 206. A contour generation circuit for generating contours of characters and figures by generating them, a built-in memory 208 for storing contours of characters and figures and bitmap data in which the insides of the contours are filled in, and 209 a built-in memory 2
A filling / transfer circuit that fills the inside of the outline stored in 08 and transfers the bitmap data whose inside of the outline is filled to the external memory 3.

Reference numeral 210 denotes a coordinate conversion control unit for controlling the coordinate conversion circuit 203;
A coordinate conversion mode register 212 for setting a value specifying a coordinate conversion method to be performed by 03, a coordinate conversion execution unit (hereinafter, referred to as a coordinate conversion EU) 212 for performing a coordinate conversion operation, and 213 a solid color / transfer Circuit 209
A transfer mode register 214 for setting a value specifying a data transfer method performed by the fill / transfer circuit 209, and a fill / transfer executor 215 for performing a fill operation and a transfer operation. Application unit (hereinafter referred to as “fill / transfer EU”)
Called. ).

The font input FIFOs 202, FI
The FO-A 204 and the FIFO-B 206 adopt a first-in first-out method.

In this embodiment, the output engine 4 is L
In order to apply to either or both of the case where P is the output engine 4 and the case where the output engine 4 is the TTP, the coordinate conversion circuit 203 uses the LP coordinate conversion method and the TTP
Although two types of coordinate conversion methods, ie, two types of coordinate conversion methods, are used, the present invention is not limited thereto, and two or more types of coordinate conversion methods may be used.

Further, as for the LP, there are cases where an address is assigned to increment the address in the X direction and an address is assigned to increment the address in the Y direction.
Filling and transferring circuit 20
Reference numeral 9 denotes an address updating method at the time of data transfer when an address assignment for incrementing an address in the X direction is performed, and an address updating method at the time of data transfer when an address assignment for incrementing the address in the Y direction is adopted. However, the present invention is not limited to this, and may have two or more types of address updating methods.

Next, the procedure for generating the character / graphic data by the character / graphic generating apparatus 5 of this embodiment will be described.

The CPU 1 converts the vector data stored in the font ROM 2 into a font input FIFO 202
And sets a value corresponding to the address assignment of the output engine 4 in the coordinate conversion mode register 211 and the transfer mode register 214. Note that if the font input FIFO 202 is full (full state), the CPU 1
Wait until space is available.

The coordinate conversion circuit 203 operates in accordance with the value of the coordinate conversion mode register 211.
10 and the coordinate transformation EU212, the font input R
The vector data stored in the OM 202 is subjected to coordinate conversion such as enlargement, reduction, italic, rotation, etc., using a 3 × 3 coordinate conversion matrix. The converted data is stored in the FIFO-A 204. Note that the coordinate conversion circuit 203 uses a FIFO-
If A204 is in the Full state, the process waits until a space is created.

The curve interpolation circuit 205 has a FIFO-A20
4 stores data in the coordinate values of the data, the data obtained by performing the curve interpolation are stored in a FIFO.
-Store in B206. Note that the curve interpolation circuit 205
If the FIFO-B 206 is in the Full state, the operation waits until a space is available.

As a curve interpolation algorithm performed by the curve interpolation circuit 205, a Bezier curve, a spline curve, an arc, and the like are known. However, the curve interpolation circuit 205 may be replaced according to the adopted algorithm. Is also easy to deal with.

The contour generation circuit 207 is a FIFO-B2
If the data is stored in the data 06, a straight line is generated between two points of the data, and the outline of the character / graphic is drawn in the built-in memory 208.

The filling / transfer circuit 209 generates bitmap data by filling the inside of the outline drawn on the internal memory 208. After filling,
In accordance with the value of the transfer mode register 214, the filling / transfer control unit 213 and the filling / transfer EU21
5, the bitmap data generated on the internal memory 208 is transferred to the external memory 3.

Thus, the character / graphic data in the dot format is stored in the external memory 3, and the CPU 1 transfers the data stored in the external memory 3 to the output engine 4 to perform printing / display.

In this embodiment, the transfer of the bitmap data drawn on the built-in memory 208 is performed according to the CP.
Although the processing is performed via the U interface circuit 201, a dedicated memory interface circuit may be used.

FIG. 3 is a diagram showing changes in data until the character / graphics generating device 5 generates bitmap data from vector data.

In FIG. 3, reference numeral 301 denotes a font ROM 2
, 302 is data after coordinate conversion is performed on the data 301 by the coordinate conversion circuit 203, 303 is data 30 by the curve interpolation circuit 205.
2 is the data after the curve interpolation is performed, 304 is the data after the contour of the data 303 is generated by the contour generation circuit 207, and 305 is the data after the inside of the data 304 is filled by the filling / transfer circuit 209. Data 306 is data after the data 305 has been transferred to the external memory 3 by the filling / transfer circuit 209.

Next, the operation of the coordinate conversion circuit 203 will be described.

FIG. 4 is a diagram showing an example of the address assignment of the external memory 3 when the TTP is used as the output engine 4, and FIG. 5 shows the address of the external memory 3 when the LP is used as the output engine 4. It is a figure showing the example of allocation.

4 and 5, the address assignment of the external memory 3 is as shown in the figure, and is the same as the address assignment of TTP and LP. The address assignment of the built-in memory 208 in the character / graphic generator 5 is the same as the address assignment of the external memory 3 shown in FIG.

In the conventional coordinate conversion circuit, X ′ = aX + bY + tx, X ′ = aX + bY + tx, for the set coordinate conversion parameters a, b, c, d, tx, ty and coordinate value (X, Y).
The coordinate transformation is performed by performing an operation of Y '= cX + dY + ty. That is, since the conventional coordinate conversion circuit has only one type of coordinate conversion method, the LP and TT having different address assignments respectively are used.
Although it was impossible to apply to both P and P, in this embodiment, the coordinate conversion circuit 203 has two types of coordinate conversion methods, a coordinate conversion method for LP and a coordinate conversion method for TTP. This makes it possible to apply to both LP and TTP.

First, a coordinate conversion method for LP will be described with reference to FIGS.

The address assignment of the LP, that is, the address assignment of the external memory 3 is as shown in FIG. 5, and the address assignment of the internal memory 208 is the same as the address assignment of the external memory 3. ing.

Therefore, as shown in FIG. 7, first, a 3 × 3 coordinate conversion matrix 7
X ′ = aX + bY + t
Data 703 of x, Y '= cX + dY + ty is obtained. The data 703 can be further subjected to curve interpolation, contour generation, and filling processing, and finally, LP bitmap data 704 can be generated in the built-in memory 208. Accordingly, when the bitmap data 704 generated on the internal memory 208 is transferred to the external memory 3 in the order of addresses, printing in LP can be performed.

Next, a coordinate conversion method for TTP will be described.
This will be described with reference to FIGS.

The address assignment of the TTP, that is, the address assignment of the external memory 3 is as shown in FIG. 4, and the address assignment of the internal memory 208 is different from the address assignment of the external memory 3. ing.

In order to generate bitmap data for TTP using the conventional coordinate conversion circuit, first, as shown in FIG.
Using the × 3 coordinate conversion matrix 802, the same coordinate conversion as the coordinate conversion required to generate the bitmap data for LP is performed. Then, the data 80 after the coordinate transformation
3 performs curve interpolation, contour generation, and filling, and once
Bitmap data 804 for assigning addresses for P
Occurs. After that, software processing or dedicated LS
Using I, bit map data 805 for address assignment for TTP is generated. Thus, conventionally, TT
In order to generate bitmap data for P, bitmap data for LP is generated once, and then bitmap data for TTP is generated using software processing or a dedicated LSI. It took a long time.

Therefore, in this embodiment, as shown in FIG. 9, first, vector data 901 in the upper left coordinate system is
Using the 3 × 3 coordinate conversion matrix 902, exactly the same coordinate conversion as that required to generate bitmap data for LP is performed. Then, the data 9 after the coordinate conversion
03, by performing a coordinate transformation using a 3 × 3 coordinate transformation matrix 905, the data 903 is rotated 90 degrees to obtain data 906. After that, the data 906 is subjected to coordinate transformation using a 3 × 3 coordinate transformation matrix 907, whereby the data 906 is mirror-inverted with respect to the Y axis, and the data 908 is converted.
Get. This data 908 is further subjected to curve interpolation, contour generation, and filling processing.
08, without changing the address allocation of the bit map data 90 for the TTP so as to match the address allocation of the TTP.
9 can be generated on the internal memory 208. Therefore, when the bitmap data 909 generated on the internal memory 208 is transferred to the external memory 3 in address order,
Since the data 910 is obtained, printing using TTP becomes possible.

However, in this method, it is necessary to perform the same three coordinate transformations as LP, that is, 90-degree rotation processing and Y-axis mirror inversion processing. If not calculated and set, no bitmap data for TTP is generated.

Therefore, in the present embodiment, the coordinate conversion is usually made X ′ = aX + bY + tx, Y ′ = cX + dY + ty.
cX + dY + ty, Y ′ = aX + bY + tx, so that the data 908 can be obtained immediately.

Next, a specific circuit configuration and operation of the coordinate conversion circuit 203 will be described with reference to FIG.

In FIG. 10, reference numeral 210 denotes a coordinate conversion circuit 2
03 is a coordinate conversion control unit that controls the entire
It is often composed of circuits such as an LA (Programmable Logic Array), a microprogram, and a state machine.
The coordinate conversion control unit 210 generates various control signals and controls various calculations necessary for coordinate conversion.

Reference numeral 211 denotes a coordinate conversion mode register for setting a value specifying a coordinate conversion method performed by the coordinate conversion circuit 203, and is constituted by a flip-flop.

Reference numeral 212 denotes a coordinate transformation E for performing a coordinate transformation operation.
U, register files 1001 and 1002, a multiplier 1003, a latch A1004, a latch B100
5, latch C1009 and selectors 1006, 1007
And an adder / subtractor 1008.

If the output engine 4 is LP, the CPU 1 sets “0” in the coordinate conversion mode register 211,
If the output engine 4 is TTP, “1” is set to the coordinate conversion mode register 211. Further, the CPU 1
The coordinate values X and Y are set in the register file 1001 from the U bus through the coordinate conversion local bus A, and the elements a, b, and 3 × 3 of the 3 × 3 coordinate conversion matrix are set in the register file 1002.
Set c, d, tx, ty.

The coordinate conversion control section 210 sequentially generates control signals for calculations necessary for coordinate conversion according to the value of the coordinate conversion mode register 211.

First, if the value of the coordinate conversion mode register 211 is “0”, X set in the register file 1001 is output to the multiplier 1 through the coordinate conversion local bus A.
003, and sends a set in the register file 1002 to the multiplier 1003 through the coordinate transformation local bus B. Multiplier 1003 calculates a × X, and stores the calculation result in latch A 1004.

Next, Y set in the register file 1001 is sent to the multiplier 1002 through the coordinate conversion local bus A, and b set in the register file 1002 is sent to the multiplier 100 through the coordinate conversion local bus B. Send to 1003. The multiplier 1003 calculates b × Y, and stores the calculation result in the latch B1005.

Next, the data stored in the latch A 1004 is passed through the selector 1006 to the adder / subtractor 1008.
And the data stored in the latch B 1005 is sent to the adder / subtractor 1008 through the selector 1007. The adder / subtractor 1008 calculates aX + bY, and stores the calculation result in the latch C1009.

Next, the data stored in the latch C 1009 is transferred to the coordinate conversion local bus A and the selector 1006.
And the tx set in the register file 1002 is sent to the adder / subtractor 1008 through the coordinate transformation local bus B and the selector 1007.
Send to The adder / subtractor 1008 calculates aX + bY + tx, and stores the calculation result in the latch C1009.

At this point, since the data stored in the latch C1009 is X '(= aX + bY + tx), the coordinate conversion control section 210 stores this data X' in the FIFO-A 204 through the coordinate conversion local bus A. . If the FIFO-A 204 is in the full state, the wait is continued as it is until a space is created.

Next, as described above, when the data stored in the latch C1009 becomes Y '(= cX + dY + ty), the coordinate conversion control unit 210 causes the data Y'
To the FIFO-A20 through the coordinate transformation local bus A.
4 is stored. If the FIFO-A 204 is in the full state, the wait is continued as it is until a space is created.

On the other hand, if the value of the coordinate conversion mode register 211 is “1”, X set in the register file 1001 is output to the multiplier 1 through the coordinate conversion local bus A.
003, and sends c set in the register file 1002 to the multiplier 1003 through the coordinate transformation local bus B. Multiplier 1003 calculates c × X, and stores the calculation result in latch A 1004.

Next, Y set in the register file 1001 is sent to the multiplier 1003 through the coordinate conversion local bus A, and d set in the register file 1002 is sent to the multiplier 100 through the coordinate conversion local bus B. Send to 1003. The multiplier 1003 calculates d × Y, and stores the calculation result in the latch B 1005.

Next, the data stored in the latch A 1004 is passed through the selector 1006 to the adder / subtractor 1008.
And the data stored in the latch B 1005 is sent to the adder / subtractor 1008 through the selector 1007. The adder / subtractor 1008 calculates cX + dY, and stores the calculation result in the latch C1009.

Next, the data stored in the latch C 1009 is transferred to the coordinate conversion local bus A and the selector 1006.
And the ty set in the register file 1002 is passed through the coordinate conversion local bus B and the selector 1007 to the adder / subtractor 1008.
Send to The adder / subtractor 1008 calculates cX + dY + ty, and stores the calculation result in the latch C1009.

At this point, since the data stored in the latch C1009 is X '(= cX + dY + ty), the coordinate conversion control section 210 stores the data X' in the FIFO-A 204 through the coordinate conversion local bus A. . If the FIFO-A 204 is in the full state, the wait is continued as it is until a space is created.

Next, as described above, when the data stored in the latch C1009 becomes Y '(= aX + bY + tx), the coordinate conversion control unit 210 causes the data Y'
To the FIFO-A20 through the coordinate transformation local bus A.
4 is stored. If the FIFO-A 204 is in the full state, the wait is continued as it is until a space is created.

The above-described circuit configuration of the coordinate conversion circuit 203 is merely an example, and it goes without saying that the present invention can be applied to other circuit configurations.

FIG. 11 is a flowchart summarizing the operation of the coordinate conversion circuit 203 in a simple algorithm.

In the coordinate conversion mode register 211, CP
According to U1, if the output engine 4 is LP, L
“0”, which is a value that specifies the coordinate conversion method for P, is set. If the output engine 4 is TTP, “1”, which is a value that specifies the coordinate conversion method for TTP, is set.

Therefore, the coordinate conversion circuit 203 first determines the value set in the coordinate conversion mode register 211 (step 1101). Coordinate conversion mode register 211
If the value set to “0” is “0”, it means that the coordinate conversion for LP is performed, and the coordinate conversion is performed by X ′ = aX + bY + t
x, Y ′ = cX + dY + ty (step 11
02), X ′ and Y ′ are stored in the FIFO-A 204 (step 1104). The coordinate conversion mode register 21
If the value set to 1 is not “0”, the coordinate conversion for TTP is performed, so that the coordinate conversion is X ′ = cX + d
This is performed as Y + ty, Y '= aX + bY + tx (step 1103), and X' and Y 'are stored in the FIFO-A 204 (step 1104). After the operation of step 1104, the process returns to step 1101.

By performing steps 1101 to 1104, both the coordinate conversion data for LP and the coordinate conversion data for TTP can be generated. Here, a, b, c, d, tx, and ty are coordinate conversion parameters provided by the CPU 1.

In this case, the coordinate conversion mode register 2
If the value set to 11 is "0", coordinate conversion for LP is performed, and if not "0", coordinate conversion for TTP is performed. Needless to say.

In this embodiment, the coordinate conversion circuit 203 picks up the coordinate conversion parameters (elements of the 3 × 3 coordinate conversion matrix) set by the CPU 1 so as to match the specified coordinate conversion method. The CPU 1 only needs to set parameters in the same manner as in the related art. However, the CPU 1 sets the coordinate conversion parameters according to the address assignment of the output engine 4 by itself. Embodiments are also conceivable. In this case, the coordinate conversion circuit 203 actually performs only one type of operation as in the related art, but the CPU 1 sets the coordinate conversion parameters so as to match the coordinate conversion method according to the address assignment of the output engine 4. As a result, the coordinate conversion circuit 203 performs two types of coordinate conversion.

Hereinafter, such an embodiment will be described with reference to FIG.
This will be described with reference to FIG.

FIG. 12 is a flowchart showing the algorithm of the coordinate conversion parameter setting operation of the CPU 1 and the operation of the coordinate conversion circuit 203.

In this embodiment, a value indicating the print mode is set in the internal register of the CPU 1 in accordance with the output engine 4. If “0” is set and the output engine 4 is TTP, “1” is set.

Therefore, the CPU 1 sets the print mode to “0”.
If it is (step 1201), the element of the 3 × 3 coordinate transformation matrix for LP is set (step 1202). Specifically, 1 row and 1 column element is a, 1 row and 2 column element is b, 1 row and 3 column element is tx, 2 row and 1 column element is c, 2 row and 2 column element is d, 2 row and 3 column element Is ty, 3 rows and 1 column element, 3 rows and 2 column element are 0, 3
Set the row 3 column element as 1.

Conversely, if the print mode is "1" (step 1201), the elements of the 3 * 3 coordinate conversion matrix for TTP are set (step 1203). Specifically, the 1-row and 1-column element is c, the 1-row and 2-column element is d, and the 1-row and 3 column element is ty, 2
Row 1 column element is a, 2 row and 2 column element is b, 2 row and 3 column element is t
x, 3 rows and 1 column element, 3 rows and 2 column element are set as 0, and 3 row and 3 column element are set as 1.

Next, the coordinate conversion circuit 203 calculates the coordinate values X,
Y is received (step 1204), and the set 3 × 3
Coordinate conversion is performed according to the elements of the coordinate conversion matrix (step 1205). Finally, X 'and Y' are converted to FIFO-A204.
(Step 1206).

Thus, even if the coordinate conversion circuit 203 can perform only one type of coordinate conversion, two types of coordinate conversion results can be obtained.
That is, it is possible to obtain the data after the coordinate conversion for LP and TTP.

If the print mode is “0”, the elements of the 3 × 3 coordinate conversion matrix for LP are set. If the print mode is not “0”, the 3 × 3 coordinate conversion matrix for TTP is set. Is set, but it goes without saying that the reverse may be set.

Here, the print mode may be specified by software for controlling the operation of the output engine 4, or may be specified directly by the user using an input device such as a keyboard. If the number of output engines 4 is limited to one, the print mode may be fixed to one.

Next, a method of dividing an area when a character or a figure is divided will be described in detail with reference to FIGS.

FIG. 13 is an explanatory view showing a conventional area dividing method, and FIG. 14 is an explanatory view showing an area dividing method of the present embodiment.

In the conventional area dividing method, the area is divided only in the X direction in units of data transfer (word units) from the built-in memory 208, or in the X and Y directions in any arbitrary unit (bit unit). Therefore, for example, as shown in FIG. 13, if the area is divided in a unit other than a multiple of 16 (a unit other than a word unit) in the X direction, X _min is not a multiple of 16, but the internal memory 208 External memory 3
Since the unit of data transfer to the word is a word unit, a blank portion where no data is generated is generated on the left side of the word including X _min . Here, X _min is the minimum value of the area in the X direction, X _max is the maximum value of the area in the X direction, Y _min is the minimum value of the area in the Y direction, and Y _max is the value of the area in the Y direction. This is the minimum value.

Therefore, in this embodiment, the area is divided so that no blank portion is generated.

FIG. 14A is an explanatory diagram showing an LP area dividing method.

In this case, since the area division in the X direction is performed in multiples of 16 (word units) and the area division in the Y direction is performed in integer units, no blank portion is generated in the word. In addition, since the area division in the Y direction is performed in integer units, the area division method has a relatively high degree of freedom.

FIG. 14B is an explanatory diagram showing a TTP area dividing method.

In this case, since the area division in the X direction is performed in integer units and the area division in the Y direction is performed in multiples of 16 (word units), no blank portion is generated in the word. Also, since the area division in the X direction is performed in integer units,
The method of dividing the area also has a relatively high degree of freedom.

Here, the data transfer unit from the built-in memory 208 to the external memory 3 is a word. However, even if it is a byte, the area is divided by a multiple of 8 (byte unit). It goes without saying that it is possible.

Next, the operation of the filling / transfer circuit 209 will be described.

The address assignment of the LP may be as shown in FIG. 6 in addition to that shown in FIG. FIG. 5 shows an address assignment for incrementing the address in the X direction, and FIG. 6 shows an address assignment for incrementing the address in the Y direction.

FIG. 5 shows an example of address assignment L
P, that is, when LP having the same address assignment as the internal memory 208 is used as the output engine 4, when transferring the bitmap data generated on the internal memory 208 to the external memory 3, May be transferred while incrementing the address. However, the LP having the address assignment shown in FIG.
8 is used as the output engine 4, when the bitmap data generated on the internal memory 208 is transferred to the external memory 3, it is not necessary to simply increment the address. Not applicable.

Therefore, it is necessary to switch the address updating method at the time of transfer depending on which address is allocated by the LP.

Next, a specific circuit configuration and operation of the filling / transfer circuit 209 will be described with reference to FIG.

In FIG. 15, reference numeral 213 denotes a filling / transfer control unit for controlling the entire filling / transfer circuit 209, which is often constituted by a circuit such as a PLA, a microprogram, or a state machine. The filling / transfer control unit 213 generates various control signals and controls various operations required for filling / transfer.

Reference numeral 214 denotes a transfer mode register for setting a value specifying a transfer method performed by the filling / transfer circuit 209, and is constituted by a flip-flop.

Reference numeral 215 denotes a filling / transfer EU for performing a filling operation and a transfer operation.
, Register CWN1502, and register CLN150
3, register AD1 (1504), and register AD2
(1505), register AD3 (1506), selector 1507, adder / subtractor 1508, latch 1509,
And filling logic 1510.

The register 1501 is a register for storing a value indicating whether the operation result of the adder / subtractor 1508 is "0", and is constituted by a flip-flop. AD1 (1504) is a register for supplying an address for accessing the built-in memory 208.
AD2 (1505) and AD3 (1506) are temporary registers.

First, the operation of filling the inside of the bitmap data generated on the internal memory 208 will be described.

The CPU 1 sets “0” in the transfer mode register 214 if the address assignment of the external memory 3 has been made such that the LP increments the address in the X direction as shown in FIG. And FIG.
As shown in (1), if the address is assigned to increment the address in the Y direction, "1" is set. Further, the CPU 1 sets the number of words (CWN) in the horizontal direction of the character / graphic in the CWN 1502 through the filling / transfer bus A from the CPU bus, and sets the number of vertical lines (CWN) in the character / graphic in the CLN 1503 and AD3 (1506). C
LN), AD1 (1504) and AD2 (15
05) is set to “0”.

The filling / transfer control unit 213 includes:
Control signals for the calculations necessary for filling the inside of the outline of the character / graphic generated by the outline generation circuit 207 are sequentially generated on the internal memory 208. Specifically, AD1 (1
The data in the built-in memory 208 is read by using the value of 504) (incremented) as an address, and transferred to the painting logic 1510 through the painting transfer bus A. The painting logic 1510 paints the inside of the received data and draws it again in the built-in memory 208. The circuit configuration and operation of the filling logic 1510 are described in detail in Japanese Patent Application Laid-Open No. 3-214368, and a detailed description thereof will be omitted here.

Next, the operation of transferring the bitmap data generated on the internal memory 208 to the external memory 3 will be described in detail with reference to the flowchart of FIG.

Here, it is assumed that the address assignment of the bitmap data generated on the internal memory 208 is the same as the address assignment shown in FIG.

The transfer mode register 214 contains the CPU 1
Accordingly, if the LP has an address assignment for incrementing the address in the X direction, "0" which is a value designating the corresponding data transfer method is set,
If the LP has assigned an address for incrementing the address in the Y direction, “1”, which is a value designating the corresponding data transfer method, is set. In the CWN 1502, the number of words (CWN) in the horizontal direction of the character / graphic is set, and in the CLN 1503, the number of lines (CLN) in the vertical direction of the character / graphic is set.

In FIG. 16, the painting / transfer circuit 20
9 first, AD1 (1504) and AD2 (1505)
Is reset, and the value of CLN 1503 (the number of lines (CLN) in the vertical direction of characters and figures) is set in AD3 (1506) (step 1601).

Subsequently, when the memory read signal output from the CPU 1 becomes active (step 1602),
The value of AD1 (1504) is used as an address in the internal memory 20.
8 is read and transferred to the external memory 3 through the fill transfer bus A (step 1603).
If the memory read signal output from the CPU 1 is non-active (step 1602), the wait is performed as it is.

Next, if the value of the transfer mode register 214 is "0" (step 1604), it means that the address has been allocated to increment the address in the X direction, so that the value of AD1 (1504) is incremented. (Step 1605). Specifically, AD1 (15
04) is added and subtracted through the transfer bus A.
508, "1" is sent to the adder / subtractor 1508 through the selector 1507, and the result of the addition is stored in the latch 1509 by the adder / subtractor 1508.
9 through the transfer bus A
1 (1504).

If the value of the transfer mode register 214 is not "0" (step 1604), it means that the address is assigned so that the address is incremented in the Y direction, so that the CWN 1502 is assigned to the AD1 (1504).
(The number of horizontal words (CWN) of characters / graphics) is added (step 1606). Specifically, the value of AD1 (1504) is sent to the adder / subtractor 1508 through the fill / transfer bus A, and the value of CWN 1502 is sent to the adder / subtractor 1508 through the fill / transfer bus B and the selector 1507. The result of the addition is latched 150
9 and the value stored in the latch 1509 is set to AD1 (1504) through the fill / transfer bus A.

Next, the value of AD3 (1506) is decremented (step 1607). Specifically, AD3 (1
The value of 506) is sent to the adder / subtractor 1508 through the fill / transfer bus A, and “1” is sent to the adder / subtractor 1508 through the selector 1507. The result of subtracting the latter from the former by the adder / subtractor 1508 is stored in the latch 1509. That is, the value stored in 1509 is set to AD3 (1506) through the painting / transfer bus A.

As a result of decrementing the value of AD3 (1506), if the value of AD3 (1506) becomes "0" (step 1608), that is, the value output from adder / subtractor 1509 becomes "0". If this is the case, a value indicating that fact is set in the register 1501. If the value of the register 1501 is “0”, the filling / transfer control unit 213 sequentially generates control signals necessary for performing the processing of steps 1609 to 1611.

That is, first, the value of AD2 (1505) is incremented (step 1609). Specifically, the value AD2 (1505) is sent to the adder / subtractor 1508 through the transfer / transfer bus A, and "1" is set to the selector 150
7 to the adder / subtractor 1508,
Thus, the result of adding the two is stored in the latch 1509, and the value stored in the latch 1509 is set in the AD2 (1505) through the fill / transfer bus A.

Next, the value of AD2 (1505) is changed to AD1 (1).
504) (step 1610). Specifically, the value of AD2 (1505) is set to AD1 (1504) through the paint / transfer bus A.

Next, the value of CLN 1503 (the number of lines in the vertical direction (CLN)) is set to AD3 (1506) (step 1611). More specifically, the value of CLN 1503 is set to AD3 (1506) through the paint / transfer bus A.

In step 1608, AD3
If the value of (1506) is not “0”, step 1611
When the processing of step 1605 is completed, or when the processing of step 1605 is completed, the operation from step 1602 is repeated.

By performing steps 1601 to 1611, if the LP has assigned an address for incrementing the address in the X direction, and
In either case, the internal memory 2 is assigned an address that increments the address in the Y direction.
Bitmap data generated on the address 08 can be transferred according to the address assignment of the LP.

When the TTP is used as the output engine 4, the bitmap data generated on the internal memory 208 can be transferred to the external memory 3 while incrementing the address. CPU
For 1, the value of the transfer mode register 214 may be set to "0", similarly to the LP having the address assignment shown in FIG.

Here, the transfer mode register 21
If the value of 4 is "0", it is assumed that the LP has assigned an address to increment the address in the X direction,
If it is not "0", it is assumed that the LP has assigned an address for incrementing the address in the Y direction, but it goes without saying that the LP may be reversed.

Although the unit of data transfer from the built-in memory 208 to the external memory 3 is a word here, it goes without saying that a byte can be applied if the number of horizontal words is the number of horizontal bytes. Nor.

Further, the CPU 1 sets the transfer mode register 21
4 is set to “0” or “1” when the software that controls the operation of the output engine 4 specifies, or the user directly specifies using an input device such as a keyboard. There are cases. If the number of output engines 4 is limited to one, the transfer mode register 2
The value of 14 may be fixed to one type.

Further, the above-described filling / transfer circuit 209
The above circuit configuration is merely an example, and it goes without saying that the present invention can be applied to other circuit configurations.

In this embodiment, the case where the character / graphics generating device 5 transfers the bitmap data generated on the internal memory 208 to the external memory 3 by devising a method of updating the transfer address is described. As mentioned, CPU1
However, an embodiment is conceivable in which the bitmap data transferred to the external memory 3 is transferred to the output engine 4 by devising a method of updating the transfer address. In this case, the character / graphics generating device 5 transfers the bitmap data generated on the internal memory 208 to the external memory 3 while simply incrementing the address.

In the following, such an embodiment will be described with reference to FIG.
This will be described with reference to FIG.

In this embodiment, the CPU 1 uses an address updating method at the time of data transfer when an address is assigned to increment an address in the X direction, and an address is assigned to increment an address in the Y direction. In this case, two types of address updating methods, ie, an address updating method at the time of data transfer, are provided. Therefore, the filling / transfer circuit 209 only needs to transfer the bitmap data generated on the internal memory 208 to the external memory 3 while incrementing the address, so that the transfer mode register 214 becomes unnecessary.

FIG. 17 shows a case where the LP having the address assignment shown in FIG.
9 is a flowchart illustrating an algorithm of a data transfer operation of U1.

Here, AR1, AR2 and AR3 are CPUs.
1, the values of the number of horizontal words and the number of vertical lines in the external memory 3 are also set in the registers inside the CPU 1.

In FIG. 17, the CPU 1 first sets the AR
1, AR2 is reset, and the number of horizontal words in the external memory 3 is set in AR3 (step 1701). Next, AR
The bitmap data stored in the external memory 3 is transferred to the output engine 4 using the value of 1 as an address (step 1702).

FIG. 5 shows the address allocation L
When P is used as the output engine 4, the bitmap data stored in the external memory 3
Address assignment that increments in the direction is required. When the character / graphics generator 5 generates bitmap data for address assignment for incrementing the address in the X direction, the CPU 1 transfers the bitmap data stored in the external memory 3 while simply incrementing the address. Then you can transfer it correctly. However, when the character / graphics generator 5 generates bitmap data for address assignment for incrementing the address in the Y direction, the CPU 1
It is not possible to correctly transfer the bitmap data stored in the file by simply incrementing the address.

Then, if the address assignment of the bitmap data stored in the external memory 3 is the same as the required address assignment (step 17).
03), AR1 is incremented (step 170)
4) The operation from step 1702 is repeated. That is, the address is transferred while simply incrementing the address.

On the other hand, if the address assignment of the data stored in the external memory 3 is different from the required address assignment (step 1703), for example, Y
If the address is to be incremented in the direction, the data cannot be correctly transferred by simply incrementing the address. Therefore, the number of vertical lines of the external memory 3 is added to AR1 (step 1705). Next, AR3 is decremented (step 1706). If the value of AR3 becomes "0" (step 1707), AR2 is incremented (step 1708), and the value of AR2 is put into AR1 (step 1709). The number of horizontal words in the external memory 3 is entered in AR3 (step 1710), and step 170 is performed.
The operation from step 2 is repeated.

By performing Steps 1701 to 1710, even if the address allocation of the bitmap data stored in the external memory 3 and the required address allocation are the same or different, the output engine 4 Bitmap data can be transferred in an order according to the address allocation of the bitmap data.

FIG. 18 shows a case where the LP having the address allocation shown in FIG.
9 is a flowchart illustrating an algorithm of a data transfer operation of U1.

Here, AR1, AR2 and AR3 are CPUs.
1, the values of the number of horizontal words and the number of vertical lines in the external memory 3 are also set in the registers inside the CPU 1.

In FIG. 18, the CPU 1 first sets the AR
1 and AR2 are reset, and the number of vertical lines of the external memory 3 is set in AR3 (step 1801). Next, AR
The bitmap data stored in the external memory 3 is transferred to the output engine 4 using the value of 1 as an address (step 1802).

The address allocation shown in FIG.
When P is used as the output engine 4, the bitmap data stored in the external memory 3
Address assignment that increments in the direction is required. When the character / graphics generating device 5 generates bitmap data of address assignment for incrementing the address in the Y direction, the CPU 1 transfers the bitmap data stored in the external memory 3 while simply incrementing the address. Then you can transfer it correctly. However, when the character / graphics generator 5 generates bitmap data for address assignment for incrementing the address in the X direction, the CPU 1
It is not possible to correctly transfer the bitmap data stored in the file by simply incrementing the address.

Therefore, if the address assignment of the bitmap data stored in the external memory 3 is the same as the required address assignment (step 18).
03), AR1 is incremented (step 180)
4) The operation from step 1802 is repeated. That is, the address is transferred while simply incrementing the address.

On the other hand, if the address assignment of the data stored in the external memory 3 is different from the required address assignment (step 1803), for example, X
If the address is to be incremented in the direction, the data cannot be transferred correctly only by incrementing the address. Therefore, the number of horizontal words of the external memory 3 is added to AR1 (step 1805). Next, AR3 is decremented (step 1806). If the value of AR3 becomes "0" (step 1807), AR2 is incremented (step 1808), and the value of AR2 is put into AR1 (step 1809). The number of vertical lines in the external memory 3 is entered in AR3 (Step 1810), and Step 180
The operation from step 2 is repeated.

By performing Steps 1801 to 1810, the output engine 4 can be operated regardless of whether the address allocation of the bitmap data stored in the external memory 3 is the same or different. Bitmap data can be transferred in an order according to the address allocation of the bitmap data.

As described above, the CPU 1 has the address updating method shown in FIG. 17 and the address updating method shown in FIG. 18, and the output engine 4 outputs the LP assigned the address shown in FIG. In the case where the bit map data is used as the output engine 4, the bit map data stored in the external memory 3 is transferred to the output engine 4 by the address updating method shown in FIG. 17, and the LP assigned the address shown in FIG. In the case where the bitmap data is used as the bitmap data 4, the bitmap data stored in the external memory 3 is transferred to the output engine 4 by the address updating method shown in FIG.

When the TTP is used as the output engine 4, the CPU 1 stores the data in the external memory 3 by the address updating method shown in FIG. 17, similarly to the LP having the address allocation shown in FIG. The bitmap data may be transferred to the output engine 4.

Here, the CPU 1 determines which address update method to use when transferring is specified by software for controlling the operation of the output engine 4 or
There are cases where the user directly designates using an input device such as a keyboard. If the number of output engines 4 is limited to one, the address updating method may be fixed to one type.

Further, in any of the address updating methods, the character / graphics generating device 5 generates bitmap data for address assignment for incrementing the address in the X direction, or the bit for address assignment for incrementing in the Y direction. The CPU 1 may determine whether or not to generate map data when software that controls the operation of the output engine 4 specifies, or when the user directly specifies using a keyboard or other input device. .

As described above, according to the above embodiment, one character / graphics generating device 5 can be applied to various output engines 4.

As a method of application, there are a case where only one of LP and TTP is used, and a case where it is used for both LP and TTP.

If the CPU 1 is to be used exclusively for LP or TTP, the CPU 1 determines the type of the output engine 4 when printing, and uses a value corresponding to the type of the output engine 4 as a coordinate. The setting may be made in the conversion mode register 210 and the transfer mode register 214, or after determining the type of the output engine 4, a 3 × 3 coordinate conversion matrix element corresponding to the type of the output engine 4 may be set. The bitmap data stored in the external memory 3 is transferred to the output engine 4 by an address updating method according to the type of the output engine 4.

When using for both LP and TTP, when giving a print instruction, the user selects and instructs one of LP and TTP from a keyboard or the like. Then, the CPU 1 determines the type of the output engine 4 that is instructed to be selected, and sets a value corresponding to the type of the output engine 4 in the coordinate conversion mode register 210 and the transfer mode register 214, or After the type of the output engine 4 is determined, a 3 × 3 coordinate conversion matrix element corresponding to the type of the output engine 4 is set, or stored in the external memory 3 by an address updating method corresponding to the type of the output engine 4. Is transferred to the output engine 4.

In the above embodiment, the output engine 4 and the external memory 3 are separated from each other. However, the output engine 4 and the external memory 3 may be integrated and regarded as one output device. In such a case, the filling / transfer circuit 209 directly transfers the bitmap data generated on the internal memory 208 to the output device.

The information processing apparatus according to the present embodiment is integrated with a printer.
Word processors and personal computers,
Can be actually commercialized as a printing device.
In such a case, the transfer destination of the filling / transfer circuit is
The output engine used. In addition, external memory
Provide one or more types of output engines
With a simple configuration, a printer-separated type word processor or
As a personal computer or printing device,
Can be commercialized. In such a case,
The transfer destination of the crushing / transfer circuit is an external memory, and C
PU is bitmap data stored in external memory
To the output engine used. Although the above embodiment has been described with reference to the case where the output engine 4 is a printer such as an LP or TTP, the present invention is also applicable to a case where the output engine 4 is a display.

[0169]

As described above, according to the present invention,
Since the coordinate conversion according to the address assignment of the output engine can be performed, there is an effect that the present invention can be applied to output engines having various address assignments.

When the area is divided, the area can be divided into data transfer units in only one of the X direction and the Y direction in accordance with the address assignment of the output engine. There is also an effect that division according to the address assignment of the output engine can be performed without creating a blank portion in the data.

Further, when the generated bitmap data is transferred, the address can be updated in accordance with the address assignment of the output engine, so that there is an effect that the present invention can be applied to an output engine having a different address assignment.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of an information processing apparatus to which a character / graphic generation apparatus according to the present invention is applied.

FIG. 2 is a configuration diagram of a character / figure generator according to the present embodiment.

FIG. 3 is an explanatory diagram showing a change in data in a character / graphic generation process.

FIG. 4 is an explanatory diagram showing an example of address assignment of an external memory when TTP is used as an output engine.

FIG. 5 is an explanatory diagram showing an example of address assignment of an external memory when an LP is used as an output engine.

FIG. 6 is an explanatory diagram showing an example of address assignment of an external memory when an LP is used as an output engine.

FIG. 7 is an explanatory diagram showing a coordinate conversion method for LP in the embodiment.

FIG. 8 is an explanatory diagram showing a conventional TTP data generation method.

FIG. 9 is an explanatory diagram showing a TTP data generation method in the embodiment.

FIG. 10 is a configuration diagram of a coordinate conversion circuit according to the present embodiment.

FIG. 11 is a flowchart showing the algorithm of the operation of the coordinate conversion circuit.

FIG. 12 is a flowchart showing an algorithm of a coordinate conversion parameter setting operation of a CPU and an operation of a coordinate conversion circuit.

FIG. 13 is an explanatory diagram showing a conventional area dividing method.

FIG. 14 is an explanatory diagram showing an area dividing method according to the present invention.

FIG. 15 is a configuration diagram of a filling / transfer circuit according to the present embodiment.

FIG. 16 is a flowchart showing an algorithm of a data transfer operation of the filling and transfer circuit.

FIG. 17 is a flowchart showing an algorithm of a data transfer operation of the CPU.

FIG. 18 is a flowchart showing an algorithm of a data transfer operation of the CPU.

[Explanation of symbols]

1 CPU, 2 font ROM, 3 external memory,
4 output engine, 5 character / graphic generator, 208
Built-in memory, 201 ... CPU interface circuit, 20
2 ... Font input FIFO, 203 ... Coordinate conversion circuit, 2
04: FIFO-A, 205: Curve interpolation circuit, 206:
FIFO-B, 207: contour generating circuit, 208: built-in memory, 209: filling / transferring circuit, 210: coordinate conversion control unit, 211: coordinate conversion mode register
212: Coordinate conversion EU, 213: Fill / transfer control unit, 214: Transfer mode register, 215: Fill / transfer EU, 1001, 1002: Register file, 1003: Multiplier, 1004: Latch A, 1005
... Latch B, 1006, 1007 ... Selector, 1008
... addition / subtraction unit, 1009 ... latch C, 1501 ... register, 1502 ... register CWN, 1503 ... register C
LN, 1504 Register AD1, 1505 Register AD2, 1506 Register AD3, 1507 Selector, 1508 Adder / subtractor, 1509 Latch, 1510
… Fill logic.

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kazuko Hasegawa 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture Inside Hitachi, Ltd. Microelectronics Equipment Development Laboratory (72) Inventor Shinji Wakisaka Yoshida, Totsuka-ku, Yokohama-shi, Kanagawa Prefecture 292 Hitachi, Ltd. Microelectronics Equipment Development Laboratory, Hitachi, Ltd. (72) Inventor Tsuneo Sato 5-2-1, Josuihonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Design and Development Center (56) References JP 4-255897 (JP, A) JP-A-2-191993 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) G09G 5/20-5/24 G06F 3/09-3 / 12 B41J 3/00-5/00

Claims (9)

(57) [Claims] 1. A character / graphics generator and a central processing unit
(Hereinafter referred to as CPU) and one or more output engines
An information processing apparatus comprising: a CPU that outputs information corresponding to an address assignment of an output engine to be used;
Information providing means for providing the
For example, the characters and graphics generator, the contour information of the characters and graphics represented in vector form (hereinafter,
It includes a coordinate transforming means for performing coordinate conversion referred to as vector data), a generating means for generating character and graphics data of a dot format from vector data coordinate transformation is performed by the coordinate transformation means, and said coordinate transforming means using the coordinate transformation parameter given from the outside, to the vector data, a coordinate transformation function for one type of the two or more coordinate transformation, based on the information given by said information providing means And a coordinate conversion selecting function for selecting any one of the two or more types of coordinate conversion . 2. The information processing apparatus according to claim 1, wherein the coordinate conversion function of said character / graphics generating device is a coordinate conversion parameter given from the outside. By using (X and Y are coordinate values before coordinate conversion, and X 'and Y' are coordinate values after coordinate conversion). A coordinate conversion parameter given from outside ] By using (X, Y is the coordinate values of the coordinates before transformation, X ', Y' are the coordinates after the coordinate transformation.) The information processing apparatus characterized by comprising, in the case of performing conversion of. 3. The outline of a character or graphic represented in a vector format.
One type of coordinate transformation for information (hereinafter referred to as vector data)
Coordinate conversion means for performing the coordinate conversion
Converted vector data into dot-format characters and figures
Character / graphic generation with generating means for generating shape data
Device, a central processing unit (hereinafter, referred to as a CPU), and one or more types of output engines. The CPU has coordinates according to the address assignment of the output engine used.
Coordinates that give conversion parameters to the above character / graphic generator
Information characterized by comprising conversion parameter assigning means
Processing equipment. 4. An information processing apparatus according to claim 3, wherein said coordinate conversion means includes an externally provided coordinate conversion parameter.
Meter [Equation 5] By using (X and Y are coordinate values before coordinate conversion, and X ′ and Y ′ are coordinates
This is the coordinate value after the target conversion. ), And the coordinate conversion parameter assigning means : And the coordinate transformation parameter given by An information processing apparatus characterized by including a case where a coordinate conversion parameter is given . 5. The outline of a character or graphic represented in a vector format.
A point that performs coordinate transformation on information (hereinafter referred to as vector data)
The coordinate conversion is performed by the target conversion means and the coordinate conversion means.
Dot-format character / graphic data from extracted vector data
(Hereinafter referred to as bitmap data)
And the bitmap data generated by the generation means are stored
And a bit map stored in the storage means.
Transfer means for transferring external data to an external device.
A graphic processing device , a central processing unit (hereinafter referred to as a CPU), and one or more types of output engines, wherein the generating means has a storage capacity larger than the storage capacity of the storage means.
When generating bitmap data of different sizes,
For each vector data divided into
When the CPU is provided with a function of generating the vector data , the CPU outputs the vector data for each data transfer unit of the transfer means.
Area division, which divides data into regions in the horizontal direction, and
Area division that divides vector data into regions in the vertical direction
Area where one of the two types of area division is performed
Depending on the dividing means and the address assignment of the output engine used,
Select one of the two types of area division
An information processing apparatus comprising: an area division selecting unit . 6. An outline of a character or graphic represented in a vector format.
A point that performs coordinate transformation on information (hereinafter referred to as vector data)
A target conversion means, coordinate transformation is performed by the coordinate transformation means Bekutorude
Data to dot-format character / graphic data (hereinafter, bit
Generating means for generating referred to as map data), and stores the bitmap data in which the generating means is generated
Storage means, and the bitmap data stored in the storage means to the outside.
And a transfer means for transferring said transfer means, to transfer the bit map data stored in said storage means
One of two or more address updates
Based on information provided from outside and an address update function for performing
Address to select any one of address update
Characters / graphics characterized by having a function of updating
Generator. 7. A character / graphic generator according to claim 6, a central processing unit (hereinafter referred to as a CPU), and one or more output engines , wherein said CPU is an output engine to be used. Information according to the address assignment of
Information providing means for providing the
For example, the address update selection function, based on the information given by said information providing means, the upper
One of two or more types of address update
An information processing apparatus characterized by selecting. 8. A contour of a character or graphic represented in a vector format.
A point that performs coordinate transformation on information (hereinafter referred to as vector data)
The coordinate conversion is performed by the target conversion means and the coordinate conversion means.
Dot-format character / graphic data from extracted vector data
(Hereinafter referred to as bitmap data )
And the bitmap data generated by the generation means are stored
And a bit map stored in the storage means.
Transfer means for transferring external data to an external device.
And the figure generating device, a central processing unit (hereinafter referred to as CPU) and the external memory, provided with one or more output engine, the said transfer means, bitmap stored in said storage means
Transferred to the external memory, and the CPU transmits the bit map stored in the external memory.
Transfer of backup data to the output engine used
Means for transferring the bitmap data stored in the external memory.
One of two or more address updates when sending
Depending on the address update function that performs one type and the address assignment of the output engine used,
One of two or more types of address update
An information processing apparatus comprising: an address update selection function for selecting . 9. The method of claim 1, 2, 3, 4, 5, 7, or 8
An information processing apparatus according to any one of the preceding claims , wherein a receiving means for receiving designation of an output engine to be used.
An information processing apparatus comprising: