JPH05188923A - Image display device - Google Patents

Abstract

PURPOSE:To improve the quality of various displays accompanying area specification. CONSTITUTION:A CPU 1 sets a display start address, the number of horizontal characters, the number of vertical characters, etc., for a display control circuit 6 and a timing generator 7. The display control circuit 6 outputs a graphic code from a GC.RAM 3 according to the frame synchronizing signal of the timing generator 7 and also outputs display data from a CC.RAM 4 to load them in a composing circuit 11. The two kind of data loaded in the composing circuit 11 are shifted by the previously set number of bits by the CPU1, logically put together after painting-out processing, and then transferred as display data to a display part.

Description

Detailed Description of the Invention

[0001]

The present invention relates to a CRT (cathode ray tube) and L
The present invention relates to an image display device applied to a CD (liquid crystal display device) or the like.

[0002]

2. Description of the Related Art Conventionally, in a graphic display device for displaying characters or patterns on a display device such as a CRT or LCD, an arbitrary portion (area) of a display screen is selected,
The following method can be exemplified as a method for performing a special process on the approximate area, for example, erasing the display data or replacing the display data with another display data.

(1) Counting values n1 and n of the number of display lines in the vertical direction of the screen starting from the frame synchronization signal
2 is used, and in the horizontal direction, a rectangular area as shown in FIG. 6 is designated by using the divided signals based on the count values n3 and n4 of the display data (characters) (Japanese Patent Laid-Open No. Hei 2).
-176695 publication).

(2) Using the frame sync signal as a starting point, the divided signal based on the count values t1, t2, t3, and t4 of the timer is used for each of the vertical direction and the horizontal direction of the screen and the above (1) is used. Similarly, a rectangular area as shown in FIG. 6 is designated (JP-A-2-176695).

(3) Window start of each horizontal line
A memory for setting a (specified area start) position and a window width is provided, and an area having an arbitrary shape as shown in FIG. 7 is specified based on the data (Japanese Utility Model Laid-Open No. 63-27954).

(4) Image data per pixel address,
There are a plurality of frame memories each having a storage area for the mask information or the priority display information, and a plurality of graphic images are combined and displayed according to the priority display information and the mask information (JP-A-2-146092).

(5) In addition to the image data storage area (frame memory), a width data storage area based on the number of pixels in the horizontal direction is provided to perform a shadowing process as shown in FIG. No. 226297).

(6) In a character display system using a character generator, mask information, priority display information, etc. are provided as attributes for each character.

(7) Providing a plurality of means for deriving the display data, and prohibiting the deriving of other display data so as to display only one display data in accordance with a predetermined priority order, the designated area is displayed. It is replaced with other display data (Japanese Patent Laid-Open No. 2-293792).

[0010]

The above-mentioned conventional methods have the following problems, respectively.

That is, according to the methods (1) and (2), only a rectangular area can be designated, so that the area cannot be designated by a graphic including a curve. In the method of (3), it is necessary to provide a memory for setting the start position and width of the designated area for each horizontal line, and if the number of horizontal lines and the number of designated areas increase,
The memory capacity also increases, and the scale of hardware also increases. With the method (4), the area can be specified on a pixel-by-pixel basis, which provides the greatest degree of freedom as an area specification method. However, since each pixel has mask information and priority display information, the memory capacity becomes enormous. The scale of hardware becomes larger than the method of (3). In the method (5), since there is only one type of horizontal width designation, there is no degree of freedom in region designation, and it can be applied only to applications such as shadowing processing. In the method (6), since the area is specified on a character-by-character basis, the area cannot be specified by a graphic including a curve, as in the methods (1) and (2). The method (7) is an effective method in the case of color display, and in the case of monochrome display, it becomes the same as the display in which a plurality of display data are simply OR-synthesized.
In other words, if there is only one combination of display data that indicates the inside of the specified area and the display data that indicates the outside of the specified area (in the case of monochrome display), there is only the effect of erasing the inside of the area or the replacement of the data, and a display such as fill composition is not possible. I can't do it. In other words, it can be expressed only as a silhouette.

An object of the present invention is to provide an image display device capable of favorably performing various types of display accompanied by area designation.

[0013]

To achieve the above object, the present invention provides an image display device for reading image data as parallel data from a parallel data input / output frame memory and sequentially transferring the data to a display device. Means for continuously moving the display data in the horizontal direction by a predetermined number of dots by shifting the display data in synchronization with the display timing, and means for synthesizing and displaying a plurality of display data having different horizontal movement amounts. And a combination indicating that the character is related to a certain area in the attribute data set for each character,
And a combination indicating the end of the area, and by a signal obtained by the means for decoding the two attributes, an arbitrary area of the display screen is selected in synchronization with the display cycle, and the desired processing is performed on the area. It is characterized in that it is configured so that the area can be designated even when a plurality of display data having different horizontal shift amounts are combined and displayed.

[0014]

According to the above-mentioned means, the display data is shifted in synchronization with the display timing to continuously move the display data in the horizontal direction by the predetermined number of dots, and the display operation is synchronized with the display operation. Select any part (area) of the display screen, and perform special processing such as erasing or filling (replacement) on that area continuously in synchronization with the display cycle. Even when a plurality of display data with different shift amounts are combined and displayed, the display operation using the area designation function can be accurately realized.

[0015]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing the construction of the main part of an embodiment of the present invention, and the display part is not shown.

In FIG. 1, a CPU 1 is a central processing unit for controlling not only the display section but also the entire apparatus, and is a ROM.
(Read-only memory) Execute the program stored in 2. In the ROM 2, a graphic code (pattern data) for graphic display is stored in addition to the program. GC. RAM (random access memory for graphic code) 3 and CC. RA
M (random access memory for character code) 4
Are the upper bytes (D8) of the CPU data bus 5, respectively.
.. D15) and the lower byte (D0 to D7) connected to the frame buffer (video RAM), the CPU 1 also uses these two RAMs 3 and 4 as a work area and a stack area.

The display control circuit 6 has a function of repeating a regular display operation asynchronously with the CPU 1 in accordance with a timing signal generated by the timing generator 7. Therefore, access to the RAMs 3 and 4 has priority in the display control circuit 6, and when the CPU 1 rewrites display data or accesses the work area or the stack area, the display control circuit 6 is in a non-access timing. The timing generator 7 controls it as described above (cycle steal access control).

Further, 8 in the figure is GC. RAM (read-only memory for character generator), 11 is a synthesis circuit which will be described in detail later, 12 is a display address bus for graphics, 13 is a display address bus for characters, 14 and 15 are latches, 18 and 19 are multiplexers. , 20 are bus drivers.

In the present embodiment, the graphic display and the character display are superimposed and displayed, and the following display operations are carried out respectively.

(I) Graphic display The display control circuit 6 mainly comprises a display address generator. The CPU 1 sets the display start address, the number of characters in the horizontal direction, the number of characters in the vertical direction, etc. in the display control circuit 6. Those set values are also sent to the timing generator 7, and the timing generator 7 generates various synchronizing signals for display according to the set values. The CPU 1 sends the graphic code from the ROM 2 to the GC. Transfer to a predetermined address of the frame buffer in RAM3. In the case of graphic display, GC. The data written in the RAM 3 becomes the display data as it is. The display control circuit 6 outputs the graphic display addresses (GA0 to GA14) on the graphic display address bus 12 according to the frame synchronization signal generated by the timing generator 7. The data (graphic code) according to the address is GC. It is output from the RAM 3 and loaded into the synthesis circuit 11.

(II) Character display The CPU 1 sets the display start address, the number of horizontal characters, the number of vertical characters, etc. in the display control circuit 6. Those set values are also sent to the timing generator 7, and the timing generator 7 is set according to those set values.
Generates various sync signals for display. CPU1
The character code is CC. RAM4
Transfer to a predetermined address of the frame buffer inside. The display control circuit 6 outputs a character display address (CA0-CA14) on the character display address bus 13 and a raster address (RA0-RA2) synchronously according to the frame synchronization signal generated by the timing generator 7. Although a 16-bit wide character code is used in this embodiment, CC. Since the RAM 4 has an 8-bit data input / output, the display control circuit 6 increments the address so that the lower 8 bits and the upper 8 bits are continuously read when reading a character code for one character, and It is latched by the lower latch 14 and the upper latch 15. Of the 16-bit character code, 3 bits are provided as attribute data that specifies the attribute of the character, and the remaining 13 bits are CG. It is set in the RAM 8. At the same time, the raster addresses (RA0 to RA2) are set, and the data (display data) according to those codes and the raster address is CC. It is output from the RAM 4 and loaded into the synthesis circuit 11.

The two types of data loaded in the synthesis circuit 11 as described above are preset by the CPU 1.
After being shifted by the number of bits, the filling processing described below is performed, and then the logical sum synthesis is performed. The display data thus obtained is transferred to a display unit (not shown). In the case of a display device using a CRT, parallel-to-serial conversion is necessary, and a line scan type dot matrix L is used.
When a CD is used, it may be necessary to separately output the above 4 bits and the lower 4 bits, but since it is irrelevant to this case, the description is omitted.

FIG. 2 is a circuit showing a concrete configuration of the combining circuit of FIG. SR (Parallel in Serial out
Shift registers) 25, 26 and SP. SR (serial in parallel out shift register) 23, 24, 35, 40, data latches 42, 43, 44, and graphic data erasing circuit 45
And an OR combination circuit 46, and a plurality of flip-flop circuits and logic circuits. In addition, other 21 ~ in the figure
The reference numeral 41 indicates signals and the like described in the timing charts of FIGS. 3 (a) and 3 (b) described later.

3 (a) and 3 (b) are timing charts relating to the basic display operation of this embodiment.
There are 3 kinds of clock pulse of 2, CLK3, CLK
1 is a basic clock, 1 cycle of CLK3 (horizontal direction)
Is the display timing for one display data (1 byte), and one cycle of CLK2 is the display timing for one dot. The FLM (first line marker) is a timing pulse indicating a division of the screen. When the FLM is output from the timing generator 7, the display control circuit 6 outputs the display start address and fetches the first display data, and sequentially. Repeat the display operation.

In this embodiment, the memory access is performed by the cycle steal as described above. While the CLK3 is low, the CPU 1 can access it, and while the CLK3 is high, the display control circuit 6 is assigned a period for reading display data. Switching of each address is performed by multiplexers 18 and 19. The display address is GC. RAM3 and CC. It is set in the RAM 4 and the graphic code and the character code are output respectively. In the case of a graphic code, the data is set in the synthesizing circuit 11 as it is, but the character code is CG. ROM8
Raster address that is set to
Display data according to (RA0 to 2) is sent to the synthesis circuit 11.

CG. ROM8 or GC. The display data output from RAM3 is P at the falling edge of CLK3.
S. It is loaded into SR25 and 26. The shift clocks 27 and 28 synchronized with CLK1 are PS. SR25, 26 and SP. SR2
3 and 24, the display data is shifted by 8 dots in accordance with the shift clocks 27 and 28, and SP. SR2
Shift to 3, 24. These display data are latched in the data latches 42 and 43 at the timing according to the respective shift amounts, and the data synthesized by the logical sum synthesis circuit 46 becomes the video output. The above operation is merely a logical sum synthesis display of the graphic display and the character display.

Here, an example of the area-filled filled display will be described with reference to FIGS. 4 (a) to 4 (d). This example is a combination of monochrome display, and when combining the square figure of FIG. 4 (a) and the circular figure of FIG. 4 (b), the display by the conventional OR combination is shown in FIG. 4), the black portion of both figures is displayed, and it is not possible to fill a square figure with an area surrounded by a circular figure as shown in FIG. 4C.

Next, the operation of the present embodiment for performing the display as shown in FIG. 4 (c) will be specifically described. That is, an operation will be described in the case of a fill composite display with an arbitrary pattern shape for character display, in which the horizontal shift amount of the display data on the filled side and the display data on the filled side are different. The 3-bit attribute data in the character code includes paste ON29 and paste END30, which are data for designating the filled composite display area. When the circular figure shown in Fig. 4 (b) is pasted on the figure in Fig. 4 (a) for composite display (Fig. 4 (c)), the sticking is a hardware method. It suffices to erase the display data of the designated area on the side to be controlled (“0” in this embodiment) and display the display data and the circular figure by logical sum synthesis display.
In this embodiment, the above operation is sequentially performed in synchronization with the display timing. Normally (whether it is a CRT or LCD), the display data is sent horizontally by one line from left to right on the screen, and the entire screen is displayed by sequentially displaying the display lines from top to bottom. Therefore, the filling operation (start and end) is repeated for each line to realize the fill composite display according to the two-dimensional area designation. The operation when the diamond-shaped figure shown in FIG. 5A is pasted (pasted) on the graphic display using the filled composite display will be described.

First, the operation will be described focusing on the display line L1. The diamond-shaped figure is 19 as shown in Fig. 5 (b).
It is composed of characters. The characters related to the filled composite display area on the line L1 which is currently being noticed are ,. Attributes of each character
(Attribute data) is set as follows.

[0031]

[Table 1]

Since the paste ON 29 and the paste END 30 of the character on the left side of the display line L1 are both OFF, the erase signal 31 of the graphic data is hi.
The state of gh is maintained, and the graphic data is not erased but is displayed by logical sum synthesis.

FIG. 3A shows how the character starts to be filled. Since the attribute data is included in the upper byte of the character code latch data, paste ON29 is high at the timing shown in the figure.
become. In response, paste ON-1D2 33,
It goes high at the falling edge of CLK3. On the other hand, the serial character data 34 is
Since high is 3 dots (L1 in FIG. 5A), it becomes high at the timing shown in the figure. Paste ON-1D
At the rising edge of AND of 33 and serial character data 34, the erase signal 31 becomes low, and when it is input, SP. The output of SR35 is F8h (11111000) when the character shift data latch A21 rises.
become. Therefore, SP. The output of SR23 (shifted parallel character data) is latched by the data latch 42, and at the same time SP. The output data of SR35 is latched by the data latch 44 and becomes the erased data 41. On the other hand, the graphic data is shifted and latched in the data latch 43 in accordance with the timings of the shift clock B28 and the shift data latch B22. Since the graphic data after the shift is erased by the graphic data erasing circuit 45 according to the content of the erase data 41, 3 dots are erased. Therefore, the logical sum composite display data is data in which diamond-shaped figures are pasted.

In the above character, the erase signal 31 which has become low in the character continues to remain low, so that all the parallel graphic data after the shift are erased.

In the character, paste ON29 is high
Paste END30 becomes high while maintaining h
(Fig. 3 (b)). Since the serial character data 34 has 3 dots of high after 2 dots of low and 3 dots of low (L1 of FIG. 5 (a)), the serial character data 34 is once high at the timing as shown in FIG. 3 (b). And then l
become ow. NAN of paste ON-1D2 33 and paste END-1D36 and serial character data 34
At the rising edge of D (falling edge of AND), the erase signal 31 becomes h
Since it becomes high, 5 dots are erased from the left (on the screen) of the parallel graphic data after the shift. Therefore,
The logical sum composition display data is data in which only diamond-shaped figures are pasted.

Next, the operation will be described by paying attention to the display line L2. The character related to the filled composite display area on the line L2, which is currently focused, is the same as L1.
, And the attributes of each character (attribute data) cannot be set differently for each line, and are set in the same manner as above.

The movement of the character on the display line L2 is the same as that on the display line L1.

In the character, the serial character data 34 is the pattern (00011110) (L in FIG. 5B).
2) So, once it goes high, it goes low again. However, since the paste END30 is low, the erase signal 31 continues to be low. Therefore, the serial graphic data 35 are all erased.

The motion of the character is similar to that of the display line L1.

As can be seen from the operation of line L2, paste ON29 is high and paste E is in the designated area.
For a character whose ND30 is low, the filling operation is not completed with any display data.

On the contrary, even if the paste END30 is low, if the paste ON29 is low, the filling is stopped from that character.

In the above description of the operation, an example has been shown in which the graphic data is erased in the designated area to perform the fill display (paste display). However, the process of replacing with another display data instead of the erase is also performed in the circuit. It is possible by changing the configuration.

Further, although the graphic display and the character display are combined in this embodiment, the same effect can be obtained by combining the character display and the character display.

[0044]

As described above, according to the present invention,
Since it is possible to accurately realize a composite display of a plurality of display data having different horizontal shift amounts, it is possible to provide an image display device with high display quality.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a main part of an embodiment of an image display device according to the present invention.

FIG. 2 is a circuit diagram showing a specific configuration of a synthesis circuit shown in FIG.

FIG. 3 is a timing chart according to the operation of this embodiment.

FIG. 4 is an explanatory diagram of a filled display.

FIG. 5 is an explanatory diagram related to the operation of filled display according to the present embodiment.

FIG. 6 is an explanatory diagram of a conventional area designation display.

FIG. 7 is an explanatory diagram of a conventional area designation display.

FIG. 8 is an explanatory diagram of a conventional area designation display.

[Explanation of symbols]

1 ... CPU, 2 ... ROM, 3 ... GC. RAM, 4
... CC. RAM, 6 ... Display control circuit, 7 ... Timing generator, 8 ... CG. ROM, 11 ... Combining circuit, 14, 15 ... Latch, 18, 19 ... Multiplexer,
20 ... Bus driver.

Claims (1)

[Claims] 1. An image display device that reads image data as parallel data from a parallel data input / output type frame memory and sequentially transfers the data to a display device by continuously shifting the display data in synchronization with display timing. Means for moving the display data in the horizontal direction by a predetermined number of dots, a means for synthesizing and displaying a plurality of display data having different horizontal movement amounts, and a character in the attribute data set for each character. A combination indicating that is related to a certain area,
And a combination indicating the end of the area, and by a signal obtained by the means for decoding the two attributes, an arbitrary area of the display screen is selected in synchronization with the display cycle, and the desired processing is performed on the area. An image display device, comprising means for continuously performing the operation of performing the operation, and configured so that an area can be designated even when a plurality of display data having different horizontal shift amounts are combined and displayed.