JPH05183000A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH05183000A JPH05183000A JP3356760A JP35676091A JPH05183000A JP H05183000 A JPH05183000 A JP H05183000A JP 3356760 A JP3356760 A JP 3356760A JP 35676091 A JP35676091 A JP 35676091A JP H05183000 A JPH05183000 A JP H05183000A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- chip
- glass
- sealed
- insulating substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3135—Double encapsulation or coating and encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
- H01L2224/85909—Post-treatment of the connector or wire bonding area
- H01L2224/8592—Applying permanent coating, e.g. protective coating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体素子等を封止
した半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor element and the like sealed therein.
【０００２】[0002]
【従来の技術】一般にＩＣチップなどの半導体素子は、
外界雰囲気からの保護，電気的絶縁，更には実装時の取
り扱いを容易にするため、封止される。従来、封止には
種々の方法が知られているが、安価で作業性のよいプラ
スチック封止がよく利用されている。2. Description of the Related Art Generally, semiconductor elements such as IC chips are
It is sealed for protection from the external atmosphere, electrical insulation, and easy handling during mounting. Conventionally, various methods are known for sealing, but an inexpensive and easy-to-work plastic sealing is often used.
【０００３】次に従来のプラスチック封止を行った半導
体装置の構成例について説明する。図８に示す半導体装
置は、セラミックパッケージ101 にＩＣチップ102 をダ
イボンドにより接着し、ボンディングワイヤ103 で接続
を行った後、セラミックパッケージ101 の開口部にセラ
ミック蓋104 をエポキシ樹脂105 で接着し封止して構成
したものである。Next, an example of the structure of a conventional semiconductor device which is sealed with plastic will be described. In the semiconductor device shown in FIG. 8, the IC chip 102 is bonded to the ceramic package 101 by die bonding, the bonding wire 103 is used for connection, and then the ceramic lid 104 is bonded to the opening of the ceramic package 101 with epoxy resin 105 for sealing. It has been configured.
【０００４】図９に示す半導体装置は、同じくセラミッ
クパッケージ101 に光電素子チップ106 をダイボンドに
より接着し、ボンディングワイヤ103 により接続を行
い、光電素子チップ106 上にガラス，石英，サファイヤ
等からなる光透過板又はカラーフィルタ107 を貼り付け
た後、パッケージ101 の開口部に光透過板108 をエポキ
シ樹脂105 で接着し封止したものである。In the semiconductor device shown in FIG. 9, a photoelectric element chip 106 is similarly bonded to a ceramic package 101 by die-bonding and connected by a bonding wire 103, and a light transmitting member made of glass, quartz, sapphire, etc. is formed on the photoelectric element chip 106. After the plate or the color filter 107 is attached, the light transmitting plate 108 is adhered to the opening of the package 101 with the epoxy resin 105 and sealed.
【０００５】図10に示した半導体装置は、絶縁基板111
にＩＣチップ102 を載置し、ボンディングワイヤ103 に
より接続を行った後、エポキシ樹脂，フェノール樹脂，
シリコーン樹脂等の封止樹脂112 を塗布して封止したも
のである。図11に示した半導体装置は、絶縁基板111 に
ＩＣチップ102 及び封止済みＩＣ又は周辺回路部品113
を載置し、ボンディングワイヤ103 により接続を行った
のち、必要な部分に封止樹脂112 を塗布又は浸漬して封
止したものである。The semiconductor device shown in FIG. 10 has an insulating substrate 111.
After mounting the IC chip 102 on the substrate and connecting it with the bonding wire 103, epoxy resin, phenol resin,
A sealing resin 112 such as a silicone resin is applied and sealed. The semiconductor device shown in FIG. 11 has an insulating substrate 111, an IC chip 102, and a sealed IC or peripheral circuit component 113.
Is placed and connected by the bonding wire 103, and then the sealing resin 112 is applied or dipped in a necessary portion to seal the portion.
【０００６】図12及び図13に示した半導体装置は、絶縁
基板111 にＩＣチップ102 をフェースダウンボンディン
グにより接続したのち、封止樹脂112 を塗布して封止し
たものである。なお114 はバンプである。図14に示した
半導体装置は、リードフレーム121 にＩＣチップ102 を
載置し、ボンディングワイヤ103 により接続したのち、
周辺部をエポキシ樹脂等のモールド樹脂122 でトランス
ファーモールドを行い封止したものである。The semiconductor device shown in FIGS. 12 and 13 is one in which an IC chip 102 is connected to an insulating substrate 111 by face-down bonding and then a sealing resin 112 is applied and sealed. Note that 114 is a bump. In the semiconductor device shown in FIG. 14, after mounting the IC chip 102 on the lead frame 121 and connecting them with the bonding wires 103,
The peripheral part is sealed by transfer molding with a mold resin 122 such as epoxy resin.
【０００７】なお上記図10〜図13に示した構成の半導体
装置においては、耐湿性向上のために、プラスチックで
封止を行った後に、更にワックスなどに浸漬し表面に含
浸させることが行われている。In the semiconductor device having the structure shown in FIGS. 10 to 13, in order to improve the moisture resistance, the surface of the semiconductor device is further dipped in wax or the like after being sealed with plastic. ing.
【０００８】[0008]
【発明が解決しようとする課題】ところで、プラスチッ
クによる封止は安価で作業性がよく、しかも自由度が他
の封止方法に比べて高い。しかし、その反面、水分の侵
入などによる耐湿性は、ガラス封止に比べて劣るという
欠点があった。またプラスチック封止部の表面にワック
スを含浸させて耐湿性を向上させても、ガラス封止に比
べると劣る上、高温高湿下での使用においては、ワック
ス含浸では全く効果をもたないという問題点があった。By the way, the plastic sealing is inexpensive and has good workability, and the degree of freedom is higher than that of other sealing methods. However, on the other hand, there is a drawback that the moisture resistance due to the penetration of water is inferior to that of glass sealing. In addition, even if the surface of the plastic sealing part is impregnated with wax to improve the moisture resistance, it is inferior to that of glass sealing, and the wax impregnation has no effect when used under high temperature and high humidity. There was a problem.
【０００９】本発明は、従来のプラスチック封止を行っ
た半導体装置における上記問題点を解消するためになさ
れたもので、耐湿性の向上が容易に実現可能な半導体装
置を提供することを目的とする。The present invention has been made to solve the above-mentioned problems in a conventional semiconductor device having a plastic encapsulation, and an object thereof is to provide a semiconductor device in which the improvement of moisture resistance can be easily realized. To do.
【００１０】[0010]
【課題を解決するための手段及び作用】上記問題点を解
決するため、本発明は、半導体素子又は半導体素子と周
辺回路素子とを基体に接続しプラスチックで封止した半
導体装置において、前記プラスチック封止部及びその周
辺の外表面に常温液状ガラスを塗布又は浸漬して形成し
たガラス層を設けるものである。In order to solve the above problems, the present invention provides a semiconductor device in which a semiconductor element or a semiconductor element and a peripheral circuit element are connected to a base body and sealed with a plastic, wherein the plastic seal is used. A glass layer formed by applying or immersing normal temperature liquid glass on the outer surface of the stop and its periphery is provided.
【００１１】このようにプラスチック封止部及びその周
辺の外表面に常温液状ガラスを塗布又は浸漬して形成し
たガラス層を設けているので、従来300 ℃以上の高温度
下でしかできなかったガラス封止が200 ℃以下の低温度
下で可能となり、プラスチック封止時の温度以上にする
ことなく、耐湿性が良く気密性の優れた半導体装置を容
易に実現することができる。As described above, since the glass layer formed by coating or immersing the normal temperature liquid glass on the outer surface of the plastic sealing portion and its surroundings is provided, the glass which can be formed only at a high temperature of 300 ° C. or higher. The encapsulation can be performed at a low temperature of 200 ° C. or less, and a semiconductor device having excellent moisture resistance and excellent airtightness can be easily realized without increasing the temperature above the plastic encapsulation.
【００１２】[0012]
【実施例】次に実施例について説明する。図１は、本発
明に係る半導体装置の第１実施例を示す断面図であり、
この実施例はＩＣチップをセラミックパッケージに封止
したものに本発明を適用したものである。図１におい
て、１はセラミックパッケージで、該パッケージ１にＩ
Ｃチップ２をダイボンドにより接着し、Al，Au等のボン
ディングワイヤ３により接続を行ったのち、パッケージ
１の開口部にセラミック蓋４をエポキシ系樹脂等の封止
樹脂５で接着する。次いで封止樹脂５の外表面及びその
周辺部、並びにセラミック蓋４の表面等、耐湿性を向上
させるため必要な部分に、常温液状ガラスを塗布し200
℃以下で硬化させてガラス層６を形成し、気密封止の半
導体装置を構成する。EXAMPLES Next, examples will be described. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention,
In this embodiment, the present invention is applied to an IC chip sealed in a ceramic package. In FIG. 1, reference numeral 1 is a ceramic package,
After the C chip 2 is bonded by die bonding and connected by the bonding wire 3 of Al, Au or the like, the ceramic lid 4 is bonded to the opening of the package 1 with the sealing resin 5 such as epoxy resin. Next, the normal temperature liquid glass is applied to the outer surface of the sealing resin 5 and its peripheral portion, the surface of the ceramic lid 4, and the like, which are necessary for improving the moisture resistance, and then 200
The glass layer 6 is formed by curing at a temperature equal to or lower than 0 ° C. to form a hermetically sealed semiconductor device.
【００１３】図２は、第２実施例を示す断面図で、光電
素子をセラミックパッケージに封止したものに本発明を
適用したものである。第１実施例と同様に、セラミック
パッケージ１に光電素子７をダイボンドにより接着し、
ボンディングワイヤ３により接続を行い、光電素子７上
にガラス，石英，サファイヤ等の光透過板又はカラーフ
ィルタ８を貼り付けたのち、保護用透光性板９をパッケ
ージ１の開口部にエポキシ系樹脂等の封止樹脂５で接着
し封止硬化する。次いで封止樹脂５の外表面及びその周
辺部に、常温液状ガラスを塗布し硬化させてガラス層６
を形成し、気密封止の半導体装置を構成する。FIG. 2 is a sectional view showing the second embodiment, in which the present invention is applied to a photoelectric package sealed in a ceramic package. Like the first embodiment, the photoelectric element 7 is bonded to the ceramic package 1 by die bonding,
After connecting with the bonding wire 3 and pasting the light transmitting plate such as glass, quartz, sapphire or the color filter 8 on the photoelectric element 7, the protective light transmitting plate 9 is attached to the opening of the package 1 with epoxy resin. And the like, and is sealed and cured. Next, the normal temperature liquid glass is applied to the outer surface of the sealing resin 5 and its peripheral portion and cured to form the glass layer 6
To form a hermetically sealed semiconductor device.
【００１４】図３は、第３実施例を示す断面図で、この
実施例はＩＣチップを絶縁基板に封止したものに本発明
を適用したものである。図３において、11は絶縁基板
で、該絶縁基板11にＩＣチップ２をダイボンドにより接
着し、ボンディングワイヤ３で接続を行ったのち、エポ
キシ系樹脂，フェノール系樹脂，アクリル系樹脂等の封
止樹脂５をＩＣチップ２及びボンディングワイヤ３を覆
うように塗布し硬化する。次いで封止樹脂５の表面及び
その周辺部に、常温液状ガラスを塗布し硬化させてガラ
ス層６を形成し、気密封止の半導体装置を構成する。FIG. 3 is a sectional view showing a third embodiment. In this embodiment, the present invention is applied to an IC chip sealed on an insulating substrate. In FIG. 3, reference numeral 11 denotes an insulating substrate. The IC chip 2 is adhered to the insulating substrate 11 by die-bonding, and the bonding wire 3 is used for connection, and then a sealing resin such as epoxy resin, phenol resin, acrylic resin, or the like. 5 is applied so as to cover the IC chip 2 and the bonding wire 3 and is cured. Next, a normal temperature liquid glass is applied to the surface of the sealing resin 5 and its peripheral portion and cured to form a glass layer 6, thereby forming a hermetically sealed semiconductor device.
【００１５】図４は、第４実施例を示す断面図で、ＩＣ
チップ２のほかに他の回路素子を一体に基板に載置した
モジュール基板に本発明を適用したものである。すなわ
ち絶縁基板11上にＩＣチップ２及び封止済みＩＣ又は周
辺回路部品21を載置して、ボンディングワイヤ３で接続
したのち、エポキシ系樹脂等の封止樹脂５をＩＣチップ
２，周辺回路部品21，絶縁基板11の端面及び下面に塗布
又は浸漬し硬化させて封止する。次いで封止樹脂５の外
表面に、常温液状ガラスを塗布し硬化させてガラス層６
を形成する。FIG. 4 is a sectional view showing a fourth embodiment of the IC.
The present invention is applied to a module board in which other circuit elements besides the chip 2 are integrally mounted on the board. That is, after mounting the IC chip 2 and the sealed IC or peripheral circuit component 21 on the insulating substrate 11 and connecting them with the bonding wire 3, the sealing resin 5 such as epoxy resin is applied to the IC chip 2 and the peripheral circuit component. 21. The end surface and the lower surface of the insulating substrate 11 are coated or dipped and cured to seal. Then, liquid glass at room temperature is applied to the outer surface of the sealing resin 5 and cured to form the glass layer 6
To form.
【００１６】図５は、第５実施例を示す断面図で、フリ
ップチップ方式の半導体装置に本発明を適用したもので
ある。図５において、31はフリップチップ方式のＩＣチ
ップで、該ＩＣチップ31を絶縁基板32にバンプ33を介し
てフェースダウンボンディングにより接続したのち、Ｉ
Ｃチップ31の周囲及びその接続部分に、エポキシ系樹脂
等の封止樹脂５を塗布し硬化させる。次いで封止樹脂５
の表面及びその周辺部に、常温液状ガラスを塗布又は浸
漬し硬化させてガラス層６を形成し、気密封止の半導体
装置を構成する。なおこの実施例においては、絶縁基板
32として透光性基板を用いることもできる。FIG. 5 is a sectional view showing a fifth embodiment, in which the present invention is applied to a flip-chip type semiconductor device. In FIG. 5, reference numeral 31 is a flip-chip type IC chip, which is connected to the insulating substrate 32 through bumps 33 by face-down bonding and then I
A sealing resin 5 such as an epoxy resin is applied to the periphery of the C chip 31 and its connecting portion and cured. Next, sealing resin 5
A normal temperature liquid glass is applied or dipped on the surface and the peripheral portion thereof to be cured to form a glass layer 6, thereby forming a hermetically sealed semiconductor device. In addition, in this embodiment, the insulating substrate
A transparent substrate may be used as 32.
【００１７】図６は、第６実施例を示す断面図で、ＴＡ
Ｂ方式によりＩＣチップを絶縁基板にフェースダウンボ
ンディングで接続し封止したものに本発明を適用したも
のである。図６において、41は絶縁基板で、該絶縁基板
41上のインナーリードとＩＣチップ31をバンプ33を介し
てフェースダウンボンディングにより接続したのち、Ｉ
Ｃチップ31の周囲，絶縁基板41の接続部分の両面に、エ
ポキシ系樹脂等の封止樹脂５を塗布し硬化させる。次い
で封止樹脂５の表面及びその周辺部に、常温液状ガラス
を塗布又は浸漬し硬化させてガラス層６を形成し、気密
封止の半導体装置を構成する。FIG. 6 is a sectional view showing a sixth embodiment, TA
The present invention is applied to an IC chip connected to an insulating substrate by face-down bonding and sealed by the method B. In FIG. 6, reference numeral 41 designates an insulating substrate.
After the inner leads on 41 and the IC chip 31 are connected via the bumps 33 by face down bonding, I
A sealing resin 5 such as an epoxy resin is applied and cured on both sides of the C chip 31 and the connection portion of the insulating substrate 41. Next, a normal temperature liquid glass is applied or dipped on the surface of the sealing resin 5 and its peripheral portion to be cured to form a glass layer 6, thereby forming a hermetically sealed semiconductor device.
【００１８】図７は、第７実施例を示す断面図で、この
実施例はリードフレームを用いたモールド封止方式の半
導体装置に本発明を適用したものである。図７におい
て、51はリードフレームで、該リードフレーム51上にＩ
Ｃチップ２をダイボンドにより接着し、リードフレーム
51上のリード配線部とボンディングワイヤ３で接続した
のち、ＩＣチップ２，ボンディングワイヤ３及びリード
フレーム51の下面を囲むように、エポキシ系樹脂等のモ
ールド樹脂52でトランスファーモールドし封止する。次
いでモールド樹脂52の表面及びその周辺部に、常温液状
ガラスを塗布又は浸漬し硬化させてガラス層６を形成
し、気密封止の半導体装置を構成する。FIG. 7 is a sectional view showing a seventh embodiment. This embodiment applies the present invention to a mold-sealing type semiconductor device using a lead frame. In FIG. 7, reference numeral 51 is a lead frame, and I is provided on the lead frame 51.
C chip 2 is bonded by die-bonding and lead frame
After connecting the lead wiring portion on 51 with the bonding wire 3, the IC chip 2, the bonding wire 3 and the lower surface of the lead frame 51 are transfer-molded and sealed with a molding resin 52 such as an epoxy resin so as to surround the lower surface. Next, the normal temperature liquid glass is applied or dipped on the surface of the mold resin 52 and its peripheral portion to be cured to form the glass layer 6, thereby forming a hermetically sealed semiconductor device.
【００１９】上記各実施例において、遮光，着色が必要
な場合、ガラス層を形成するための常温液状ガラスに着
色顔料を混合したものを用いてもよく、これにより気密
性及び遮光性の高い封止が得られる。In each of the above embodiments, when light shielding and coloring are required, a mixture of a normal temperature liquid glass for forming a glass layer and a coloring pigment may be used, whereby a seal having high airtightness and light shielding property may be used. You can get a stop.
【００２０】[0020]
【発明の効果】以上実施例に基づいて説明したように、
本発明によれば、プラスチック封止部及びその周辺の外
表面に常温液状ガラスの塗布等で形成したガラス層を設
けているので、プラスチック封止時の温度以上にするこ
となく、耐湿性が良く気密性の優れた半導体装置の封止
を容易に実現することができる。As described above on the basis of the embodiments,
According to the present invention, since the glass layer formed by applying the normal temperature liquid glass or the like is provided on the outer surface of the plastic sealing portion and the periphery thereof, the humidity resistance is improved without increasing the temperature at the time of plastic sealing or higher. It is possible to easily realize the sealing of the semiconductor device having excellent airtightness.
【図１】本発明に係る半導体装置の第１実施例を示す断
面図である。FIG. 1 is a sectional view showing a first embodiment of a semiconductor device according to the present invention.
【図２】第２実施例を示す断面図である。FIG. 2 is a sectional view showing a second embodiment.
【図３】第３実施例を示す断面図である。FIG. 3 is a sectional view showing a third embodiment.
【図４】第４実施例を示す断面図である。FIG. 4 is a sectional view showing a fourth embodiment.
【図５】第５実施例を示す断面図である。FIG. 5 is a sectional view showing a fifth embodiment.
【図６】第６実施例を示す断面図である。FIG. 6 is a sectional view showing a sixth embodiment.
【図７】第７実施例を示す断面図である。FIG. 7 is a sectional view showing a seventh embodiment.
【図８】従来の半導体装置の構成例を示す断面図であ
る。FIG. 8 is a cross-sectional view showing a configuration example of a conventional semiconductor device.
【図９】従来の半導体装置の他の構成例を示す断面図で
ある。FIG. 9 is a cross-sectional view showing another configuration example of a conventional semiconductor device.
【図10】従来の半導体装置の他の構成例を示す断面図で
ある。FIG. 10 is a cross-sectional view showing another configuration example of the conventional semiconductor device.
【図11】従来の半導体装置の他の構成例を示す断面図で
ある。FIG. 11 is a cross-sectional view showing another configuration example of the conventional semiconductor device.
【図12】従来の半導体装置の他の構成例を示す断面図で
ある。FIG. 12 is a cross-sectional view showing another configuration example of the conventional semiconductor device.
【図13】従来の半導体装置の他の構成例を示す断面図で
ある。FIG. 13 is a cross-sectional view showing another configuration example of the conventional semiconductor device.
【図14】従来の半導体装置の他の構成例を示す断面図で
ある。FIG. 14 is a cross-sectional view showing another configuration example of the conventional semiconductor device.
１ セラミックパッケージ ２ ＩＣチップ ３ ボンディングワイヤ ４ セラミック蓋 ５ 封止樹脂 ６ ガラス層 ７ 光電素子 ８ 光透過板又はカラーフィルタ ９ 保護用透光性板 11 絶縁基板 21 周辺回路部品 31 ＩＣチップ 32 絶縁基板 33 バンプ 41 絶縁基板 51 リードフレーム 52 モールド樹脂 1 Ceramic Package 2 IC Chip 3 Bonding Wire 4 Ceramic Lid 5 Sealing Resin 6 Glass Layer 7 Photoelectric Element 8 Light Transmission Plate or Color Filter 9 Protective Light Transmission Plate 11 Insulation Board 21 Peripheral Circuit Parts 31 IC Chip 32 Insulation Board 33 Bump 41 Insulating substrate 51 Lead frame 52 Mold resin
【手続補正書】[Procedure amendment]
【提出日】平成４年６月１６日[Submission date] June 16, 1992
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１４[Correction target item name] 0014
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１４】図３は、第３実施例を示す断面図で、この
実施例はＩＣチップを絶縁基板に封止したものに本発明
を適用したものである。図３において、１１は絶縁基板
で、該絶縁基板１１にＩＣチップ２をダイボンドにより
接着し、ボンディングワイヤ３で接続を行ったのち、エ
ポキシ系樹脂，フェノール系樹脂，アクリル系樹脂等の
封止樹脂５をＩＣチップ２及びボンディングワイヤ３を
覆うように塗布し硬化する。次いで封止樹脂５の表面及
びその周辺部に、常温液状ガラスを塗布し硬化させて、
ガラス層６を形成した半導体装置を構成する。FIG. 3 is a sectional view showing a third embodiment. In this embodiment, the present invention is applied to an IC chip sealed on an insulating substrate. In FIG. 3, reference numeral 11 denotes an insulating substrate, the IC chip 2 is bonded to the insulating substrate 11 by die bonding, and the bonding wire 3 is used for connection, and then a sealing resin such as an epoxy resin, a phenol resin, an acrylic resin, or the like. 5 is applied so as to cover the IC chip 2 and the bonding wire 3 and is cured. Next, the normal temperature liquid glass is applied to the surface of the sealing resin 5 and its peripheral portion and cured ,
A semiconductor device having the glass layer 6 is formed.
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１６[Correction target item name] 0016
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１６】図５は、第５実施例を示す断面図で、フリ
ップチップ方式の半導体装置に本発明を適用したもので
ある。図５において、３１はフリップチップ方式のＩＣ
チップで、該ＩＣチップ３１を絶縁基板３２にバンプ３
３を介してフェースダウンボンディングにより接続した
のち、ＩＣチップ３１の周囲及びその接続部分に、エポ
キシ系樹脂等の封止樹脂５を塗布し硬化させる。次いで
封止樹脂５の表面及びその周辺部に、常温液状ガラスを
塗布又は浸漬し硬化させて、ガラス層６を形成した半導
体装置を構成する。なおこの実施例においては、絶縁基
板３２として透光性基板を用いることもできる。FIG. 5 is a sectional view showing a fifth embodiment, in which the present invention is applied to a flip-chip type semiconductor device. In FIG. 5, 31 is a flip-chip type IC
Chip, bump the IC chip 31 onto the insulating substrate 32
After connecting by face-down bonding via 3, the sealing resin 5 such as an epoxy resin is applied to the periphery of the IC chip 31 and its connecting portion and cured. Next, a normal temperature liquid glass is applied or dipped on the surface of the sealing resin 5 and its peripheral portion to be cured to form a semiconductor device in which the glass layer 6 is formed. In this embodiment, a translucent substrate may be used as the insulating substrate 32.
【手続補正３】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１７[Correction target item name] 0017
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１７】図６は、第６実施例を示す断面図で、ＴＡ
Ｂ方式によりＩＣチップを絶縁基板にフェースダウンボ
ンディングで接続し封止したものに本発明を適用したも
のである。図６において、４１は絶縁基板で、該絶縁基
板４１上のインナーリードとＩＣチップ３１をバンプ３
３を介してフェースダウンボンディングにより接続した
のち、ＩＣチップ３１の周囲，絶縁基板４１の接続部分
の両面に、エポキシ系樹脂等の封止樹脂５を塗布し硬化
させる。次いで封止樹脂５の表面及びその周辺部に、常
温液状ガラスを塗布又は浸漬し硬化させて、ガラス層６
を形成した半導体装置を構成する。FIG. 6 is a sectional view showing a sixth embodiment, TA
The present invention is applied to an IC chip connected to an insulating substrate by face-down bonding and sealed by the method B. In FIG. 6, reference numeral 41 is an insulating substrate, and the inner leads on the insulating substrate 41 and the IC chip 31 are bumped by bumps 3.
After connecting by face-down bonding via 3, the sealing resin 5 such as epoxy resin is applied and cured on the periphery of the IC chip 31 and both surfaces of the connection portion of the insulating substrate 41. Next, the normal temperature liquid glass is applied or dipped on the surface of the sealing resin 5 and its peripheral portion to cure the glass , and the glass layer 6 is formed.
To form a semiconductor device.
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１８[Correction target item name] 0018
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１８】図７は、第７実施例を示す断面図で、この
実施例はリードフレームを用いたモールド封止方式の半
導体装置に本発明を適用したものである。図７におい
て、５１はリードフレームで、該リードフレーム５１上
にＩＣチップ２をダイボンドにより接着し、リードフレ
ーム５１上のリード配線部とボンディングワイヤ３で接
続したのち、ＩＣチップ２，ボンディングワイヤ３及び
リードフレーム５１の下面を囲むように、エポキシ系樹
脂等のモールド樹脂５２でトランスファーモールドし封
止する。次いでモールド樹脂５２の表面及びその周辺部
に、常温液状ガラスを塗布又は浸漬し硬化させて、ガラ
ス層６を形成した半導体装置を構成する。FIG. 7 is a sectional view showing a seventh embodiment. This embodiment applies the present invention to a mold-sealing type semiconductor device using a lead frame. In FIG. 7, reference numeral 51 is a lead frame, and the IC chip 2 is adhered onto the lead frame 51 by die bonding, and the lead wiring portion on the lead frame 51 is connected by the bonding wire 3, and then the IC chip 2, the bonding wire 3 and Transfer molding is performed with a molding resin 52 such as an epoxy resin so as to surround the lower surface of the lead frame 51 and sealing is performed. Next, the normal temperature liquid glass is applied or dipped on the surface of the mold resin 52 and the peripheral portion thereof to be cured to form a semiconductor device in which the glass layer 6 is formed.
【手続補正５】[Procedure Amendment 5]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１９[Name of item to be corrected] 0019
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１９】上記各実施例において、遮光，着色が必要
な場合、ガラス層を形成するための常温液状ガラスに着
色顔料を混合したものを用いてもよく、これにより機密
性及び遮光性の高い封止が得られる。[0019] In the above embodiments, the light-shielding, if coloring is needed, may be used a mixture of colored pigment in cold liquid glass for forming the glass layer, thereby high confidentiality and shielding properties A seal is obtained.
【手続補正７】[Procedure Amendment 7]
【補正対象書類名】図面[Document name to be corrected] Drawing
【補正対象項目名】図７[Name of item to be corrected] Figure 7
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【図７】 [Figure 7]
フロントページの続き (72)発明者 西村 芳郎 東京都渋谷区幡ケ谷２丁目43番２号 オリ ンパス光学工業株式会社内Front page continued (72) Inventor Yoshiro Nishimura 2-43-2 Hatagaya, Shibuya-ku, Tokyo Inside Olympus Optical Co., Ltd.
Claims (2)
子とを基体に接続しプラスチックで封止した半導体装置
において、前記プラスチック封止部及びその周辺の外表
面に常温液状ガラスを塗布又は浸漬して形成したガラス
層を設けたことを特徴とする半導体装置。1. A semiconductor device in which a semiconductor element or a semiconductor element and a peripheral circuit element are connected to a substrate and sealed with plastic, by applying or immersing normal temperature liquid glass on the outer surface of the plastic sealing portion and its periphery. A semiconductor device comprising the formed glass layer.
されていることを特徴とする請求項１記載の半導体装
置。2. The semiconductor device according to claim 1, wherein the normal temperature liquid glass is mixed with a coloring pigment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3356760A JPH05183000A (en) | 1991-12-26 | 1991-12-26 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3356760A JPH05183000A (en) | 1991-12-26 | 1991-12-26 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05183000A true JPH05183000A (en) | 1993-07-23 |
Family
ID=18450636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3356760A Withdrawn JPH05183000A (en) | 1991-12-26 | 1991-12-26 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05183000A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005508763A (en) * | 2001-11-09 | 2005-04-07 | ３デー プリュー | Device for hermetic encapsulation of components protected from arbitrary stress |
| JP2015192144A (en) * | 2014-03-27 | 2015-11-02 | インテル・コーポレーション | Electric circuit on flexible substrate |
-
1991
- 1991-12-26 JP JP3356760A patent/JPH05183000A/en not_active Withdrawn
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005508763A (en) * | 2001-11-09 | 2005-04-07 | ３デー プリュー | Device for hermetic encapsulation of components protected from arbitrary stress |
| JP2015192144A (en) * | 2014-03-27 | 2015-11-02 | インテル・コーポレーション | Electric circuit on flexible substrate |
| US9930793B2 (en) | 2014-03-27 | 2018-03-27 | Intel Corporation | Electric circuit on flexible substrate |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990311 |