JPH05182985A - Manufacture of bottom-gate-type semiconductor device - Google Patents

Abstract

PURPOSE:To enhance the reliability of, e.g. a CMOS SRAM using a bottom-gate- type TFT by a method wherein the gate withstand voltage of the bottom-gate- type TFT is improved. CONSTITUTION:In the manufacturing method of a bottom-gate-type semiconductor device, a gate electrode GT1 is provided on an insulating film 3 formed on a substrate and an active layer AC1 is formed on the gate electrode GT1 via a gate insulating film 4. In the manufacturing method, a semiconductor film is deposited on the insulating film 3 and, after that, impurities are introduced into the semiconductor film. After that, a heat treatment is executed to the whole surface; the growth of grains in the semiconductor film is promoted sufficiently; after that, the semiconductor film is patterned; the gate electrode GT1 composed of said semiconductor film is formed. After that the gate insulating film 4 is formed on the gate electrode GT1. After that, a semiconductor film is formed on the gate insulating film 4; after that, the semiconductor film is patterned; the active layer Ac1 is formed. After that, an interlayer insulating film 6 is formed on the active layer Ac1; after that, a heat treatment is executed; the interlayer insulating film 6 is flattened.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, for example, a TFT having a bottom gate structure (inverse stagger type) used as a load for a driving element for liquid crystal display or SRAM.
The present invention relates to a manufacturing method of (thin film transistor).

[0002]

2. Description of the Related Art Conventionally, a drive element for liquid crystal display or SR
As a structure of a TFT used as an AM load, there are a top gate structure (a positive stagger type) and a bottom gate structure (a reverse stagger type).

Particularly, the latter TFT having a bottom gate structure
Is a CMOS type SRAM adopting a memory cell having an N-MOS transistor and a P-MOS transistor.
In, it is advantageous for miniaturization.

That is, if the bottom gate structure TFT is adopted as the P-MOS transistor and the TFT is stacked on the N-MOS transistor, the CM is formed.
The area occupied by the OS transistor is significantly reduced, and the CM
It is possible to achieve high integration of the OS type SRAM.

A conventional P-channel type TFT manufacturing method is shown in FIG.
It will be explained based on. First, as shown in FIG. 7A, after forming a polycrystalline silicon layer on the insulating film 31, patterning is performed to form a gate electrode 32. After that, the entire surface is SiO
_A gate insulating film 33 made of 2 is formed.

Next, as shown in FIG. 7B, a thin polycrystalline silicon layer is formed on the entire surface and then patterned to form an island-shaped active layer 34. After that, the photoresist film 3
P-type impurities, for example, BF ₂ ^+, are ion-implanted into the source and drain portions through 5, and activation annealing is performed to form P-type source regions 34S and drain regions 34D in the active layer 34, respectively. To do. At this time, the portion above the gate electrode 32 becomes the channel region 34C.

Next, as shown in FIG. 7C, after forming an interlayer insulating film 36 of, eg, a BPSG film on the entire surface, 90
A heat treatment is performed at 0 ° C. for 20 minutes to flatten (reflow) the interlayer insulating film 36. Then, the interlayer insulating film 36
An opening 36a is formed in a portion corresponding to the source region 34S and the drain region 34D, and a source electrode 37S and a drain electrode 37D each made of an Al layer are formed so as to fill the opening 36a.
FT (hereinafter, simply referred to as P-TFT) is obtained.

[0008]

However, in the conventional manufacturing method, the grain of the gate electrode 32 grows rapidly when the heat treatment for flattening the interlayer insulating film 36 is applied. In the gate insulating film 33,
The stress associated with the above-described grainin growth is applied, and as a result, the film quality of the gate insulating film 33 is deteriorated and the gate breakdown voltage is significantly deteriorated. This is P-
This causes defective reliability of the TFT and leads to deterioration of yield.

The present invention has been made in view of the above problems, and its object is to provide a bottom gate type TF.
It is an object of the present invention to provide a method for manufacturing a bottom gate type semiconductor device capable of improving the gate breakdown voltage of T and improving the reliability of, for example, a CMOS type SRAM using a bottom gate type TFT.

[0010]

The present invention has a gate electrode GT ₁ on an insulating film 3 formed on a substrate, and an active layer Ac ₁ on the gate electrode GT ₁ via a gate insulating film 4. In the method of manufacturing the bottom gate type semiconductor device in which
After depositing the semiconductor film 22 on the insulating film 3, impurities are introduced into the semiconductor film. After that, heat treatment is performed on the entire surface to sufficiently advance the grain growth of the semiconductor film 22, and then the semiconductor film 22 is patterned to form a gate electrode GT ₁ of the semiconductor film 22. Then, the gate insulating film 4 is formed on the gate electrode GT ₁ . Then, after forming a semiconductor film on the gate insulating film 4, the semiconductor film is patterned to form the active layer Ac ₁ . Then, the active layer Ac ₁
After forming the interlayer insulating film 6 thereon, heat treatment is performed to planarize the interlayer insulating film 6.

In this case, after forming the gate insulating film 4 on the gate electrode GT ₁ , a heat treatment may be performed for the purpose of improving the crystal of the gate insulating film 4.

[0012]

According to the manufacturing method of the present invention described above, the gate electrode GT
_{After the} semiconductor film 22 to be ₁ is formed on the insulating film 3, heat treatment is performed so that the grains of the semiconductor film 22 are sufficiently grown. Therefore, for example, for planarizing the interlayer insulating film 6 performed thereafter. The grain growth of the semiconductor film 22 is not caused by the heat treatment of
_{1 No} stress is applied to the gate insulating film 4 formed in the upper layer. Therefore, according to the manufacturing method of the present invention, the gate breakdown voltage of the bottom gate type TFT can be improved, and for example, a CMOS type S using the bottom gate type TFT can be used.
The reliability of RAM can be improved.

[0013]

Embodiments of the present invention will be described below with reference to FIGS. FIG. 1 is a sectional view showing the structure of a CMOS SRAM manufactured by the manufacturing method according to this embodiment, and FIG. 2 is an equivalent circuit diagram of the SRAM.

As shown in FIG. 2, this SRAM has a pair of driver transistors (N-MOS transistors) T.
r ₁ and Tr ₂ and a pair of P-channel type thin film transistors connected to the storage nodes N 1 and N ₂ of these driver transistors Tr ₁ and Tr ₂ (hereinafter simply referred to as P-TFT).
A memory cell is composed of a flip-flop circuit FF composed of a load composed of T ₁ and T ₂ and a pair of access transistors (N-MOS transistors) Q ₁ and Q ₂ . In the drawing, WL is a word line, and BL and (inverted BL) are bit lines.

That is, the structure of this SRAM is based on FIG.
To explain, SiO is formed on the P-type well region 1.₂Etc.
Driver transistor Tr via the gate insulating film 2₁
And Tr₂(Tr₂(Not shown) for each gate
Pole GD and access transistor Q₁And Q₂(Q₁
(Not shown) for the gate electrode, that is, the word line WL
Is the first semiconductor layer, for example, the polycide layer.
Is formed, and SiO is formed on the gate electrodes such as GD and WL.₂
P-TFT (T ₁And T
₂) Each gate electrode GT₁And GT₂Is the second layer semiconductor
Layers, for example polycrystalline silicon layers,
Electrode GT₁And GT₂P over the gate insulating film 4
-TFT (T₁And T₂) Each active layer Ac₁And Ac₂
(Ac₂(Not shown) is formed and configured
There is.

SD is a source / drain region of the access transistor Q ₂ , 5 and 6 are interlayer insulating films made of SiO ₂ , 7 is a Vcc line, and 8 is a bit line extracting wiring made of a metal film. Further, 9S is a source region, 9D
Is a drain region to which the power source Vcc is applied, 9C is a channel region, and 10 is a ground line.

Next, a method of manufacturing the SRAM will be described with reference to FIGS. The same reference numerals are given to those corresponding to FIG. In the following description, the driver transistor Tr ₁ , the P-TFT (T ₁ ) and the access transistor Q ₂ will be mainly described.
r ₂ , P-TFT (T ₂ ) and access transistor Q
The description of ₁ is omitted because the same manufacturing process is performed.

First, as shown in FIG. 3A, a field insulating layer 21 is formed on the P-type well region 1 by a selective oxidation (LOCOS) method. Then, after forming a first semiconductor film, for example, a tungsten polycide layer on the entire surface, the polycide layer is patterned to form a gate electrode GD of the driver transistor Tr ₁ , a gate electrode (word line) WL of the access transistor Q ₂ , and The ground wire 10 is formed. Then, N-type impurities are ion-implanted using these gate electrodes GD, WL and 10 as a mask to form N-type source / drain regions SD on the surface of the well region 1.

Next, as shown in FIG. 3B, for example,
SiO₂After forming the inter-layer insulation film 3 consisting of
The opening 3a is formed in the contact portion with the pole GD. That
Then, a second-layer semiconductor film, for example, with a thickness of 4 is formed on the interlayer insulating film 3.
After forming the polycrystalline silicon layer 22 of 00 to 600 Å,
Injection energy = 25 keV, injection amount = 1 × 10¹⁵cm ^-2
Under the conditions of N type impurities such as phosphorus (P⁺) Is polycrystalline
Ions are implanted into the silicon layer 22.

Next, as shown in FIG. 4A, the entire surface has a thickness of 5
A SiO ₂ film (cap SiO ₂ film) 23 of 00Å is formed. Then, heat treatment is performed at a temperature of 600 to 700 ° C. for about 10 hours to sufficiently advance the grain growth of the polycrystalline silicon layer 22. This heat treatment is performed for 10 hours in this example, but may be shorter than that time. By this heat treatment, the grain growth of the polycrystalline silicon layer 22 becomes almost saturated.

Next, as shown in FIG. 4B, the cap SiO ₂ film 23 on the polycrystalline silicon layer 22 is removed by etching with an HF solution, and then the polycrystalline silicon layer 22 is patterned to form a P-TFT (T ₁ ) And (T ₂ ) gate electrodes GT ₁ and GT ₂ are formed.

Next, as shown in FIG. 5A, SiO 2 is formed on the entire surface.
_After the gate insulating film 4 made of ₂ and having a thickness of about 500 Å is formed by the CVD method, heat treatment is performed in an oxygen atmosphere. This thermal oxidation treatment improves the film quality of the gate insulating film 4 and is effective in improving the interlayer breakdown voltage. After that, the opening 4a is formed in the contact portion between the active layer Ac ₁ and the gate electrode GT ₂ of the P-TFT (T ₂ ) which will be formed later.

Next, as shown in FIG. 5B, after forming a third semiconductor film, for example, a polycrystalline silicon layer on the entire surface, the polycrystalline silicon layer is patterned to form the active layer Ac ₁ and Vcc line 7. Form. After that, in the active layer Ac ₁ ,
The photoresist film 24 is formed on the portion to be the channel region 9C.
Then, P type impurities such as BF ₂ ⁺ are ion-implanted into the active layer Ac ₁ and the Vcc line 4 using the photoresist film 24 as a mask. By this ion implantation,
In the active layer Ac ₁ , a P-type source region 9S and a drain region 9D are formed, and an intrinsic channel region 9C is formed. Further, the Vcc line 7 is also made conductive by the introduction of the above impurities.

Next, as shown in FIG. 6, after forming an interlayer insulating film 5 made of SiO ₂ having a relatively large film thickness on the entire surface,
The opening 5a is formed in a portion corresponding to the other source / drain region SD of the access transistor Q ₂ . afterwards,
After forming a metal film on the entire surface, the metal film is patterned to form the bit line extraction wiring 8. The bit line lead-out wiring 8 is formed in order to improve the step coverage of the bit line (inversion BL) due to the Al layer formed later.

Then, as shown in FIG. 1, BPS is applied to the entire surface.
After forming the G film 6, a heat treatment for flattening the BPSG film is performed. This heat treatment is performed, for example, in a nitrogen atmosphere at a temperature of 900 ° C. for 20 minutes. By this heat treatment, the BPSG film 6 is melted and flattened as a whole.
After that, an opening 6a is formed in a portion corresponding to the bit line extraction wiring 8 and then an Al layer is formed on the entire surface. Then, this Al layer is patterned to form a bit line (inversion B
By forming L), the SRAM according to this example is obtained.

According to this manufacturing method, after the polycrystalline silicon layer 22 to be the gate electrode GT ₁ is formed on the interlayer insulating film 3, heat treatment is performed to sufficiently grow the grains of the polycrystalline silicon layer 22. Therefore, during the subsequent low temperature heat treatment for the purpose of crystal improvement of the gate insulating film 4 and high temperature heat treatment for planarizing the BPSG film 6, the polycrystalline silicon layer 22 (that is, the gate electrode GT ₁ ) is Grain growth does not occur, and stress is not applied to the gate insulating film 4 formed in the upper layer of the gate electrode GT ₁ . Therefore, according to the manufacturing method of this example, the gate breakdown voltage of the bottom gate type TFT can be improved, and the reliability of, for example, the CMOS type SRAM shown in FIG. 1 using the bottom gate type TFT can be improved.

[0027]

According to the method of manufacturing the bottom gate type semiconductor device of the present invention, the gate breakdown voltage of the bottom gate type TFT can be improved, and the reliability of, for example, a CMOS type SRAM using the bottom gate type TFT is improved. Can be made

[Brief description of drawings]

FIG. 1 is a sectional view showing a configuration of a CMOS SRAM manufactured by a manufacturing method according to an embodiment.

FIG. 2 is an equivalent circuit diagram showing a configuration of a CMOS SRAM manufactured by the manufacturing method according to this embodiment.

FIG. 3 is a process diagram (1) showing the method for manufacturing the P-TFT according to the present embodiment in accordance with the method for manufacturing SRAM.

FIG. 4 is a process diagram (No. 2) showing the method for manufacturing the P-TFT according to the present embodiment in accordance with the method for manufacturing SRAM.

FIG. 5 is a process diagram (3) showing the method for manufacturing the P-TFT according to the present embodiment in accordance with the method for manufacturing SRAM.

FIG. 6 is a process diagram (4) showing the method for manufacturing the P-TFT according to the present embodiment in accordance with the method for manufacturing SRAM.

FIG. 7 is a process drawing showing a method for manufacturing a P-TFT according to a conventional example.

[Explanation of symbols]

Tr ₁ , Tr ₂ driver transistor T ₁ , T ₂ P-TFT Q ₁ , Q ₂ access transistor WL word line BL, inverted BL bit line FF flip-flop circuit 1 P-type well region 2, 4 gate insulating film 3, 5 Interlayer insulation film GD, GT ₁ , GT ₂ Gate electrode 6 BPSG film 7 Vcc line 8 Bit line extraction wiring 9S source region 9D drain region 9C channel region Ac ₁ active layer 10 ground line 22 polycrystalline silicon layer (gate electrode GT ₁ )

Continuation of front page (51) Int.Cl. ⁵ Identification code Office reference number FI technical display location H01L 27/11

Claims (2)

[Claims] 1. A method for manufacturing a bottom gate type semiconductor device, comprising: a gate electrode formed on an insulating film formed on a substrate; and an active layer formed on the gate electrode via a gate insulating film. After depositing a semiconductor film on the semiconductor film, a step of introducing impurities into the semiconductor film, a step of performing heat treatment on the entire surface to sufficiently promote grain growth of the semiconductor film, and a step of patterning the semiconductor film A step of forming the gate electrode by a film, a step of forming the gate insulating film on the gate electrode, and a step of forming a semiconductor film on the gate insulating film, and then patterning the semiconductor film to form the active layer. A bottom gate type semiconductor device comprising: a step of forming the interlayer insulating film on the active layer; and a step of performing a heat treatment to planarize the interlayer insulating film after forming the interlayer insulating film on the active layer. Manufacturing method. 2. The method for manufacturing a bottom gate type semiconductor device according to claim 1, wherein after the gate insulating film is formed on the gate electrode, a heat treatment for improving the crystal of the gate insulating film is performed. ..