JPH05181984A - Data processing system - Google Patents

Abstract

PURPOSE:To obtain a data processing system wherein a data drive type information processor and a Neumann type type information processor are connected on a on-line basis to enable mutual data transfer. CONSTITUTION:The data processing system includes a Neumann type computer 200, a data drive type computer 300, a bus I/F 10, and transfer control parts 101 and 102 for making a mutual on-line connection between the computers. 200 and 300; and the transfer control part 101 controls data transfer from the Neumann type computer 200 to the data drive computer 300 through the bus I/F and the transfer control part 102 controls data transfer from the data drive type computer 300 to the Neumann type computer 200 through the bus I/F 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing system, and in particular, a data driven type information processing apparatus is online connected to an existing system including a Neumann type information processing apparatus to mutually transfer data. Such a data processing system.

[0002]

2. Description of the Related Art In a conventional computer, various instructions are stored in a program memory as a program, addresses of the program memory are sequentially specified by a program counter, the instructions are sequentially read, and the Neumann type information is executed. Most are processing equipment.

On the other hand, the data driven type information processing apparatus is a kind of non-Neumann type computer which does not have the concept of sequential instruction execution by a program counter. Such a data driven type information processing apparatus employs an architecture based on parallel processing of instructions. Then, as soon as all the data to be operated are available, the instruction can be executed, and multiple instructions are executed simultaneously depending on the data.
Programs are executed in parallel according to the natural flow of data. As a result, it is considered that the time required for calculation is significantly shortened.

The architecture peculiar to the data driven type information processing apparatus described above includes a program storage section, an ignition detection section and an arithmetic processing section, and the data includes three pieces of information of its own destination, arithmetic operation and data body. A set of data including these three is called a packet. In operation, a packet is first thrown into an ignition detection unit having a queuing mechanism. In the data driven method, as described above, since the calculation is performed when the data are gathered, a mechanism for aligning the data is performed in the ignition detection unit. When the data is gathered in the firing detection unit, the gathered data is made into one packet and sent to the next arithmetic processing unit. The arithmetic processing unit performs arithmetic using the arithmetic information of the transmitted packet and the data body. The calculation result is stored in the data body of the packet,
This packet is sent again to the program storage section. A data flow program for performing predetermined arithmetic processing is loaded in the program storage unit in advance. The program storage unit reads out new destination information and operation information by being addressed based on the destination information of the given packet, stores them in the input data packet, and sends them again to the ignition detection unit. As described above, the data packet flows in the order of the program storage unit → the ignition detection unit → the arithmetic processing unit → the program storage unit → ..., Thus, the execution of the data flow program stored in advance in the program storage unit is promoted.

In the data driven type information processing apparatus as described above, conventionally, a dedicated input / output device is connected and a data packet for the input / output apparatus to load the dataflow program into the dataflow type information processing apparatus. And to provide a data packet for execution to execute the loaded program. Further, this dedicated input / output device operates so as to input a data packet storing the calculation result in the connected data driven type information processing device and perform a predetermined program process. When connecting such a dedicated input / output device to a Neumann type information processing device which is an existing system, an off-line serial transfer method has been used as shown in FIG. That is, conventionally, there has not been a mechanism for connecting the data driven information processing device and the Neumann information processing device online.

[0006]

Since the data driven type information processing apparatus and the Neumann type information processing apparatus cannot be connected online, the Neumann type information processing apparatus commands the data driven type information processing apparatus in an interactive manner. Issue
There is a problem that the operation status of the data driven type information processing apparatus cannot be monitored in real time on the Neumann type information processing apparatus side. Therefore, in order to confirm the soundness of the operating condition of the data-driven information processing device, the input / output data packet is temporarily stored in a dedicated input / output device as in the conventional case, and the data-driven information processing is performed by offline transfer. There was no choice but to grasp the operation status by transferring it to the device and analyzing the data later on the data driven type information processing device side. Therefore, such a method of monitoring the operating state is time-consuming and lacks real-time performance, which is inconvenient and inferior in practicality.

Therefore, an object of the present invention is to provide a data processing system in which a data driven type information processing apparatus and a Neumann type information processing apparatus are online connected and data can be transferred mutually.

[0008]

A data processing system according to the present invention is a data driven type information processing apparatus, a Neumann type information processing apparatus, and data and a data driven type information processing apparatus according to the specifications of a bus of the Neumann type information processing apparatus. Format mutual conversion means for mutually converting the data format with the packet data having a unique tag part, and buffering the difference between the data transfer speed of the bus and the data input / output speed of the data driven information processing device. The data-driven information processing device and the Neumann-type information processing device are connected online to transfer data to each other.

[0009]

Since the data processing system according to the present invention is configured as described above, it is possible to connect the data driven type information processing apparatus and the Neumann type information processing apparatus online.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram of a data transfer control unit in a data processing system according to an embodiment of the present invention.

FIG. 2 is a block diagram of a data processing system according to an embodiment of the present invention. 3 (a) and 3 (b)
FIG. 3 is a diagram showing an example of a circuit configuration for inputting / outputting a transmission signal, an input signal, a transmission permission signal, and an input permission signal in the data driven computer shown in FIG. 2.

FIGS. 4A to 4E are input / output timing charts of the transmission signal, the input signal, the transmission permission signal and the input permission signal shown in FIGS. 3A and 3B.

FIGS. 5A to 5C are views for explaining an example of the format of data transferred in the data processing system according to the embodiment of the present invention.

In FIG. 2, the data processing system according to the present embodiment includes a Neumann type computer 200, a data driven type computer 300 and computers 200 and 3.
Bus I / F (interface) 10 for connecting 00 to enable mutual data transfer and online connection,
It includes transfer control units 101 and 102. The Neumann type computer 200 is configured to include a CPU (central processing unit) and sequentially executes programs using a program counter. The detailed configuration of the transfer control units 101 and 102 will be described later, but the transfer control unit 101 is configured to give data and instructions to the data driven computer 300 based on an instruction given in a conversational form from the Neumann computer 200. .. Further, the transfer control unit 102 is configured to transmit the data derived from the data driven computer 300 to the Neumann computer 200 based on an instruction given from the Neumann computer 200 in a conversational manner.

The data driven computer 300 is an SB
It is provided as an integrated circuit including C (single board computer) and EDS (external data memory) connected to SBC. The EDS is a memory for storing a large amount of data to be processed in the SBC in advance. S
The BC includes a plurality of QJBs (branching / merging unit), CPSs (program storage unit), FCs (data pair detection unit), FPs (arithmetic processing unit), and PIFs (extended program storage unit).

The QJB selectively determines the output destination based on the destination information of the given packet data. CPS
The PIF stores the data flow program in advance. The FC waits for given packet data. That is, when two different packet data having the same destination information are detected, it is output as one packet data. The FP similarly performs arithmetic processing on the data stored in the supplied packet data based on the instruction stored therein, and stores the arithmetic result again in the input packet data. The packet data derived from the FP is output to the outside of the data driven computer 300 via QJB or is given to the CPS again.

Each of the above-mentioned SBC components is a bus I.
/ F10 and a series of control signals for transmitting / receiving data to / from the Neumann computer 200 via the transfer control units 101 and 102, with the circuits shown in FIGS. 3A and 3B incorporated therein. .. As shown in FIG. 3A, each unit forming the SBC includes a transfer control circuit 11 and a data holding circuit 12 connected to the circuit 11. The transfer control circuit 11 is connected to the transfer control unit 101 or 102. When data is transmitted from the Neumann type computer 200 to each part of the SBC, the transfer control part 101 if the SBC can receive the data to be transmitted.
Outputs the transmission signal CI to the SBC. On the contrary, when data is transmitted from the SBC of the data driven computer 300, the input permission signal RI is given from the Neumann computer 200 via the transfer control unit 102, so that the SBC transmits the data to the Neumann computer 200. Is transmitted, the input signal CO is output via the transfer control circuit 11. The input signal CO is also given to the data holding circuit 12 at the same time, and accordingly, the data holding circuit 12
The data DI input to and held in is derived as data DO and given to the transfer control unit 102. An example of the circuit configuration of the transfer control circuit 11 is shown in FIG.

4A to 4E, a transmission signal CI, a transmission permission signal RO, an input signal CO, an input permission signal RI and output data in the transfer control circuit 11 shown in FIG. 3A. A DO input / output timing chart is shown.

The logic level "H" of each signal in FIGS. 4A to 4D indicates the output state or permission state of the signal, while the logic level "L" indicates the output stop state or the inhibition state of the signal. .. Since the transfer control circuit 11 outputs the transmission permission signal RO in the permitted state, the transfer control circuit 11 and the data holding circuit 12 are supplied with the data DI together with the transmission signal CI. After that, the transfer control circuit 11 makes the transmission permission signal RO fall in response to the fall of the transmission signal CI to shift to the prohibited state, and prohibits the next input of the data DI. The input data DI is data that is held in the data holding circuit 12 and is output as data DO. At this time, since the transfer control circuit 11 is supplied with the input permission signal RI, the transfer control circuit 11 and the data holding circuit 12
Outputs the data DO together with the input signal CO. After that, the transfer control circuit 11 lowers the signal level of the input signal CO, and accordingly, the input permission signal RI falls and prohibits the continuous output of the next data DO. Then, to allow the input of the next data DI,
The transmission permission signal RO rises, and the next data DI is input together with the transmission signal CI. Thus, in the data driven computer 300, the Neumann computer 2
Input data DI from 00 and Neumann computer 2
The input / output with the output data DO to 00 is controlled.

FIGS. 5A to 5C show data transferred in the data processing system according to this embodiment. The Neumann computer 200 transfers data to the data driven computer 300 in word units (one word unit). The word-unit data transmitted from the Neumann computer 200 is edited inside the transfer control unit 101 into packet data having a two-word structure that can be processed by the computer 300. The edited packet data is then provided to the data driven computer 300. Conversely, the data driven computer 300 transmits data to the Neumann computer 200 in packet data units. The transmitted packet data is directly transmitted to the Neumann computer 200, and is divided into data in word units by a program process prepared in the computer 200 in advance. 5A and 5B show the first word data and the second word data that form the packet data shown in FIG. 5C. In this embodiment, the packet data has a 2-word structure, but the number of words to be composed is not limited to this, and N (N
= 1, 2, 3, ...) Word structure may be used. next,
The block configuration of the data transfer control units 101 and 102 in the data processing system shown in FIG. 1 will be described.

In FIG. 1, transfer control units 101 and 102 are provided so that the existing Neumann computer 200 and the data driven computer 300 can mutually transfer data.
Is provided.

The transfer control unit 101 includes an arbiter (arbitration circuit) 20, a memory access control unit 30, a packet output number / interval control unit 40, and a packet output memory 5.
0, output controller 60 and data buffer 70.
The transfer control unit 102 includes an arbiter 21, a memory access control unit 31, a trace information control unit 41, a packet input memory 51, an input control unit 61, and a data buffer 71.

The bus I / F 10 is a CPU bus of the Neumann type computer 200 and the transfer control units 101 and 102.
Connect. The bus I / F 10 is provided with an address signal ADDR1, a control signal CNT1 and data DATA, which the user gives in a conversational manner via the Neumann type computer 200.
Enter 1. In addition, the data DATA2 provided from the transfer control units 101 and 102 is input to the data DAT.
A1 is given to the Neumann computer 200. The bus I / F 10 controls the control signals PKT1, ARB1, MAC1, MAC2 based on the control signal CNT1 supplied thereto.
And TRC1 are output.

The arbiters 20 and 21 have control signals AR.
B1 is applied, and the input / output operation is arbitrated accordingly.
In other words, when the input / output operation of the arbiter 20 is in the enable state in response to the control signal ARB1, the arbiter 21 is set to the input / output operation prohibited state. Therefore, one of the arbiters 20 and 21 is selectively permitted to perform its input / output operation by the control signal ARB1. The arbiter 20 or 21 in the permitted state outputs the control signal ARB2 or ARB3.

The memory access control units 30 and 31 are
It controls the packet output memory 50 and the packet input memory 51, respectively. The memory access control unit 30 is activated in response to the control signal ARB2 output when the arbiter 20 is in the enable state, and is supplied with the control signal M.
The control signal MAC3 is derived to the packet output memory 50 based on AC1. The control signal MAC1 corresponds to the address designated by the address signal ADDR1. Packet output memory 50 receives data DATA2
Is stored by addressing based on the control signal MAC3, and the stored data is stored in the control signal MAC3.
Data DATA3 is read out by addressing based on. The memory access control unit 31 inputs the control signal ARB3 output when the arbiter 21 is in the enable state, and is activated accordingly. Memory access control unit 3
1 gives the control signal MAC4 to the packet input memory 51 based on the given control signal MAC2. The control signal MAC2 is a signal derived based on the address signal ADDR1. The memory 51 writes and stores the given DATA6 at a specified address based on the control signal MAC4. Further, the data is read from the designated address based on the control signal MAC4 and the data DATA2 is output.

Number of packet outputs / interval control section 40
Is a control signal PK derived based on the control signal CNT1.
The control signal CNT2 is derived to the output controller 60 based on T1.

The trace information controller 41 controls the control signal CN
The control signal CNT3 is derived to the input control unit 61 based on the control signal TRC1 derived based on T1.

The data buffer 70 buffers the data DATA3 derived from the packet output memory 50, and under the control of the output control unit 60, the data DATA4.
And output to the data driven computer 300. The data buffer 71 buffers the data DATA5 provided from the data driven computer 300 and derives it as the data DATA6 into the packet input memory 51 under the control of the input controller 61.

The trace information control unit 41 includes the input control unit 6
While controlling 1 by the control signal CNT3, the data DATA5 given from the data driven computer 300 is prevented from being written into the packet input memory 51 via the data buffer 71 and causing data overflow in the memory 51. Have a function. More specifically, the trace information control unit 41 includes an input control unit 61 which is a data driven computer 30.
The control signal CN output according to the input of the input signal CO given from 0 is input and counted. When this count value reaches a predetermined value, the control signal CNT3 is given to the input control section 61 to derive the input permission signal RI for prohibiting the input of the data DATA5 from the data driven computer 300. Data overflow is prevented.

The packet output memory 50 receives data DATA under the control of the memory access controller 30.
Write 2 by addressing. At this time, the memory 50
Internally, as shown in FIGS. 5 (a) to 5 (c), the supplied data DATA2 in word units are continuously written and stored for two words to edit the packet data of FIG. 5 (c). .. This packet data is read out in response to a read request from the computer 200 and data D
It is derived as ATA3. Therefore, the memory 50 has a function of editing the word unit data of the Neumann computer 200 into packet data that can be processed by the data driven computer 300.

In the packet input memory 51, the data DATA6 from the data driven computer 300 given as the packet data of FIG. 5C is written under the control of the memory access control unit 31, and then the computer 20.
Data DATA2 is read in response to a read request from 0.
And give it to the bus I / F 10. The bus I / F 10 converts the supplied DATA2 into data DATA1 and supplies it to the Neumann computer 200. The Neumann computer 200 edits the supplied packet data DATA1 into processable word-unit data.

Next, the specific operation of the transfer control unit in the data processing system of this embodiment shown in FIG. 1 will be described.

First, data transfer from the Neumann computer 200 to the data driven computer 300 will be described. A control signal CN given from the CPU bus of the Neumann type computer 200 in a user's conversation form.
T1, address signal ADDR1 and data DATA1
Is input to the bus I / F 10. The bus I / F 10 outputs the control signal ARB1 based on the applied control signal CNT1, sets the arbiter 20 in the enable state, and sets the arbiter 21 in the disable state. Furthermore, the bus I / F 10 is an arbiter 20.
The signal MAC1 derived based on the address signal ADDR1 to the memory access control unit 30 activated by the control signal ARB2 output from the memory access control unit 30 and the data DATA2 derived based on the data DATA1 similarly supplied to the memory 50 for packet output. Give to each. further,
The bus I / F 10 supplies the control signal PKT1 derived based on the supplied control signal CNT1 to the packet output number / interval control unit 40. The packet output number / interval control unit 40 gives a control signal CNT2 to the output control unit 60 in order to control the output number of the data packet desired by the user and the output interval based on the given control signal PKT1.

The data edited in the packet output memory 50 from word data to packet data and stored in the memory 50 is stored in the memory 50 until a read request from the Neumann computer 200 is issued by the control signal CNT1. When there is a read request from the Neumann computer 200, the bus I / F 10 derives the control signal ARB1 based on the applied control signal CNT1,
The arbiter 20 is set to the permitted state and the arbiter 21 is set to the prohibited state. The bus I / F 10 further provides a "control signal MAC1 to the memory access control unit 30 based on the address signal ADDR1 provided thereto. The memory access control unit 30 receives the control signal ARB2 output from the arbiter 20 set to the enable state. Since it has been activated, the control signal MAC3 is applied to the memory 50 based on the applied control signal MAC1 and the packet data stored in the memory 50 is read out.
Stored at 0 once.

The output controller 60 controls the data buffer 7 based on the control signal CNT2 and the transmission permission signal RO provided thereto.
The packet data stored in 0 is converted into data DATA4 and is derived together with the transmission signal CI. In other words, the output control unit 60 sends the packet data stored in the data buffer 70 together with the transmission signal CI to the packet data DATA4 when the transmission permission signal RO is input in the permitted state.
And then output.

On the contrary, when the data driven computer 300 cannot receive the data from the Neumann computer 200, the transmission permission signal RO is in the prohibited state and is given to the output control unit 60. 60 does not output data from the data buffer 70. Therefore, the data DATA3 is buffered in the data buffer 70, and the transmission operation is on standby until the transmission permission signal RO is in the permission state. In this way, the bus transfer speed of the computer 200 and the data input / output speed of the computer 300 are buffered.

Next, data transfer from the data driven computer 300 to the Neumann computer 200 will be described. The control signal CNT1, the address signal ADDR1 and the data DATA1 are transferred from the CPU bus of the Neumann type computer 200 to the bus I / O according to the user's conversation style.
Input to F10.

The bus I / F 10 is supplied with a control signal CN
The arbiter 2 outputs the control signal ARB1 based on T1.
0 is set to the prohibited state, and the arbiter 21 is set to the permitted state. Further, the bus I / F 10 is provided with an address signal A
The control signal MAC2 is derived to the memory access control unit 31 based on the DDR1.

Since the memory access control unit 31 is activated by the control signal ARB3 output from the arbiter 21 set to the enable state, the control signal MAC is stored in the memory 51.
4 is derived and the writing of data in the memory 51 is controlled.

Further, the bus I / F 10 outputs the control signal TRC1 to the trace information control section 41 based on the applied control signal CNT1. Trace information control unit 41
Is a control signal CN based on the applied signal TRC1.
The input control unit 61 is supplied with T3 to control the input of data from the data driven computer 300.

The input control unit 61 derives the input permission signal RI based on the control signal CNT3. The input permission signal RI is in the permission state, and the data driven computer 300
When there is output data DATA5 from the data buffer 5, the data DATA5 is input to the data buffer 71 and the input signal CO is input to the input control unit 61.

The packet data DATA5 buffered in the data buffer 71 is written in the memory 51 as the data DATA6. At the same time, the trace information control unit 41 counts the number of data input by the control signal CN given from the input control unit 61, and derives the signal CNT3 based on this count value to avoid data overflow in the memory 51. ing.

Data DAT is stored in the packet input memory 51.
The packet data stored as A6 is stored in the memory 51 and waits until there is a read request by the control signal CNT1 from the Neumann computer 200.

When there is a read request from the Neumann type computer 200, the bus I / F 10 derives the control signal ARB1 based on the applied control signal CNT1 to set the arbiter 20 in the prohibited state, and the arbiter 2
Set 1 to the permitted state. The bus I / F 10 provides a control signal MAC2 to the memory access control unit 31 based on the address signal ADDR1 provided further. The memory access control unit 31 sets the arbiter 21 set to the enabled state.
Since it has been activated by the control signal ARB3 output from, the control signal MAC4 is applied to the memory 51 based on the applied control signal MAC2, and the packet data stored in the memory 51 is read. The read packet data is input to the Neumann type computer 200 via the bus I / F 10 as data DATA2, and the Neumann type computer 200 executes a series of processes including data editing.

As described above, according to the transfer control unit of the data processing system shown in FIG. 1, the data in word units according to the CPU bus specification of the Neumann computer 200 and the data drive type computer 300 shown in FIG. ), It is possible to perform format mutual conversion with packet data composed of a plurality of word data. Further, at the time of data transfer, the output control unit 60 and the input control unit 61 are respectively controlled to perform buffer control via the data buffer 70 and the data buffer 71. Therefore, the transfer time and data of the CPU bus of the Neumann computer 200 The difference between the input / output cycle time of the packet data of the drive type computer 300 can be absorbed (buffered).

Thus, the Neumann type computer 20
0 is connected to the data driven computer 300 online, and the data driven computer 300 is connected in real time.
Since it is possible to input desired data and process the data, it becomes possible for the Neumann computer 200 to monitor the operation status of the data driven computer 300 in real time.

[0048]

As described above, according to the present invention, there is an effect that the data driven type information processing apparatus and the existing Neumann type information processing apparatus can be connected online to mutually transfer data.

Due to the above-mentioned effects, there is an effect that the user can monitor the operation status of the data driven type information processing apparatus interactively from the Neumann type information processing apparatus. By enabling this monitoring, it is possible to monitor the soundness of the operation of the data-driven information processing device with a Neumann computer, and if there is an abnormality, quickly analyze and recover the abnormality. It is also possible to increase the operating rate of the system including the type information processing device.

[Brief description of drawings]

FIG. 1 is a block diagram of a data transfer control unit in a data processing system according to an embodiment of the present invention.

FIG. 2 is a configuration diagram of a data processing system according to an embodiment of the present invention.

3A and 3B are diagrams showing an example of a circuit configuration for inputting and outputting a transmission signal, an input signal, a transmission permission signal, and an input permission signal in the data driven computer shown in FIG. 2; Is.

4 (a) to (e) are input / output timing charts of the transmission signal, the input signal, the transmission permission signal, and the input permission signal shown in FIGS. 3 (a) and 3 (b).

5A to 5C are diagrams illustrating an example of a format of data transferred in the data processing system according to the embodiment of the present invention.

FIG. 6 is a diagram for explaining a conventional data transfer system of a Neumann computer and a data driven computer.

[Explanation of symbols]

 10 bus I / F 20 and 21 arbiter (arbitration circuit) 30 and 31 memory access control unit 40 packet output number / interval control unit 41 trace information control unit 50 packet output memory 51 packet input memory 60 output control unit 61 input control Parts 70 and 71 Data buffers 101 and 102 Transfer control unit 200 Neumann type computer 300 Data driven type computer CI transmission signal RO transmission permission signal RI input permission signal CO input signal In each figure, the same reference numerals indicate the same or corresponding parts. ..

Claims (1)

[Claims] 1. A data driven type information processing apparatus, a Neumann type information processing apparatus, data conforming to bus specifications of the Neumann type information processing apparatus, and packet data having a tag section unique to the data driven type information processing apparatus. Format mutual conversion means for mutually converting the data formats of the above, and buffer means for buffering the difference between the data transfer speed of the bus and the data input / output speed of the data driven information processing device. , The data driven type information processing device and the Neumann type information processing device are connected online to mutually transfer data,
Data processing system.