JPH05181928A - Pattern generation device for logical simulation - Google Patents

Abstract

PURPOSE:To shorten the generation period and to improve the reliability of the logical simulation by providing a command file for converting a test pattern for a device testing machine into a pattern file for simulation. CONSTITUTION:The hexadecimal data file of the test pattern for the device testing machine needs to be converted into binary data for simulation and further the data format needs to be converted. Data in hexadecimal notation are developed into the binary data first. Then the binary developed values are assigned, digit by digit, to a matrix which has terminal numbers as row components and a clock period as column component as shown in a figure. In the figure, the clock is 160+1 seconds and the number of terminals is 7. According to the data, a high potential is set to 1 and a low potential is set to 0; and the time of a potential variation point and a potential after the variation are found to generate and output the test pattern for simulation. Thus, the test pattern for logical simulation is automatically generated and the generation is easier and more accurate than before.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic simulation of a digital logic circuit, and particularly,
It relates to a test pattern creation device.

[0002]

2. Description of the Related Art Conventionally, there are roughly two methods for creating a pattern file that describes a test pattern for logic simulation of a digital logic circuit. One is a method of describing a format peculiar to a simulator by a person, and the other is a method of creating a pattern using a time chart editor.
The former uses a screen editor provided by the basic program of the computer, uses a data format that can be input from the simulator, and uses a character image for the signal value in units of elapsed time for all input terminals. That is, the description is made using 0, 1 or H, L and the like.

On the other hand, the latter uses an editor capable of editing a time chart with a graphic image, and again, for all input terminals, the signal value in units of elapsed time, but here is the actual waveform image. Is input as it is as a figure, and this is converted into a format unique to the simulator via an intermediate file. In any case, the operator finally creates a pattern file as shown in FIG. 5, and the operator
The pattern creation and input work were always performed with the specific numerical values on the pattern file in mind.

[0004]

However, for logic simulation of a digital logic circuit, there are various parameters that constitute a control signal, such as a clock period, a clock initial value at start, a pulse width, and a pulse rise time. It is necessary to decide the test pattern for simulation in consideration of the above. These test patterns are determined depending on the hardware specifications of the digital circuit to be tested. Therefore,
When determining the test pattern for simulation,
Based on these parameters, the pulse waveform, in particular, the numerical values related to time such as pulse timing and duration must be calculated by the operator, and the result must be input to the simulator using the above-mentioned device, which requires a great deal of labor. I needed it. Furthermore, when an error occurs, it is very difficult to find the cause.

The present invention is often concerned with the above-mentioned problems of insufficient efficiency and reliability in the case of editing data and checking errors, as well as pattern creation, error detection and correction. To solve the problem of taking time to realize, shorten the test pattern creation period, improve the reliability of logic simulation, and provide a test pattern creation device for simulation that reduces the burden on the operator. It is what

[0006]

In order to solve the above-mentioned drawbacks of the test pattern creating apparatus for simulation, the present invention provides an apparatus tester for inputting a signal to an actual digital circuit for testing. The test file is converted into a test pattern for simulation, and a command file for describing this in a pattern file is provided.

[0007]

By the above means, the test pattern for the device tester is read by the workstation for logic simulation, and the pattern file having the test pattern for simulation on the workstation is stored.
Create automatically.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 2 is a conceptual diagram showing an outline of the configuration of a pattern file creating apparatus which is an embodiment of the present invention. In the figure, 1 is a pattern input device. The pattern input device 1 may be, for example, a commercially available personal computer or the like. 2 is a work station for logic simulation. This work
The station 2 may be essentially the same as the pattern input device 1, but must be capable of processing a large amount of data at high speed in order to control the operation of the simulation of the digital circuit in real time. I have to. A recording medium 3 records a test pattern. This is, for example, a flexible disk or the like, but in this embodiment, the form is not particularly limited. However, at least it must be available to both the pattern input device 1 and the work station 2. 4 is
It is a device testing machine. The device tester 4 includes an output terminal and an input terminal (not shown), actually creates an electric signal according to the test pattern, outputs the electric signal from the output terminal, and outputs the electric signal received at the input terminal. , And has a function of converting into another signal having a format unique to the device tester 4. By using this function, it is possible to send a test pattern to an actual digital circuit under test (not shown), monitor the output from the digital circuit under test, and check whether the operation of the circuit conforms to the required specifications.

First, the operator uses the pattern input device 1 to create a pattern waveform or edit a created waveform. For this purpose, a lot of software for creating waveform data is commercially available, and an operator can proceed with the work while appropriately displaying necessary data and signal waveforms on the screen. When the operator performs a predetermined operation while seeing such a display, the waveform data creating software automatically creates a data file for controlling the device testing machine 4. An example of this data file is shown in FIG. In the data file shown in the figure, the value indicating the output of the device tester 4, that is, the timing at which the input of the digital circuit under test (not shown) becomes a high potential, is shown for each specific clock cycle for a specific terminal with a specific promise. It is displayed in hexadecimal based on the above. Therefore, for example, if FF ₁₆ continues, it means that it remains at a high potential during that period.

In the present invention, the data file for the device testing machine 4 is used as a work file for logical simulation.
A command file shown in FIG. 3 necessary for converting into a pattern file for simulation for giving a waveform instruction to the station 2 and a method for converting data using this command file are provided. An example of this conversion will be described in detail below. In the present embodiment, it is assumed that the command file converts the above test pattern on the work station 2.

FIG. 1 shows a flow chart for creating a simulation pattern file using a command file. The generation of the simulation test pattern is started from step 101, and in step 102, it is selected whether or not to correct the test pattern for the device testing machine 4. If necessary, in step 103, the test pattern is modified appropriately. Then, step 104
At, the parameters are set. The parameters referred to in the present embodiment are the file name of the test pattern for the device testing machine 4, the signal name of the input terminal, the signal name of the clock, the clock period, the rising time of the signal, the duty ratio, and the like. At this point, the input parameter values are merely recorded in the command file. Then step 1
At 05, it is selected whether or not to confirm the timing. If you select timing confirmation here, step 1
At 06, the waveform image is displayed on the screen of the work station 2 in the form as shown in FIG.
Asks again if the pattern needs to be modified. On the other hand, if there are no mistakes, you can say that no correction is necessary and proceed to the next step. After this, the parameters will be set again in step 105. However, at this time, since there is no need to make corrections, the process of step 105 can be omitted by a simple operation such as pressing the return key. Good. On the other hand, when it is necessary to correct the timing, the found error may be corrected in step 102.

On the other hand, when the operator replies that no correction is necessary in step 102, or when the operator selects the timing confirmation unnecessary in step 105,
The process proceeds to step 107. In this step 107, the simulation pattern / frame data is read from the pattern file for the tester 4 designated by the command file. The simulation pattern / frame data is described in the form as shown in FIG. The meaning of this description will be described later.

The number of valid data is calculated from the number of frames given simultaneously with this data. Since one frame of simulation pattern / frame data consists of 2430 bytes, the number of valid data is defined as the number of valid data = 2430 * (the number of frames + 1), and the data is read out by the number of this valid data. You can do it like this. In addition, in this specification, * is an operation symbol indicating integration. Then, in step 108, it is checked whether the number of frames is 4 or 16, and if the number of frames is 4 or 16,
In step 109, these frames are byte-interleaved multiplexed to create 4- and 16-multiplexed data. If the number of frames is not 4 or 16, the process of step 109 is omitted.

Then, in step 110, the test patterns for the device testing machine 4 already stored in the file of the workstation 2 are converted for logic simulation. Here, this conversion method will be described. As already described in the section of the prior art, the test pattern data file for the device tester 4 specifies the output of the device tester 4, that is, the timing at which the input of a digital circuit under test (not shown) becomes high potential. It is a hexadecimal representation of the value shown for each terminal for each clock cycle based on a specific promise. On the other hand, the pattern file for the workstation 2 displays the state of the signal for each clock period in parallel for all terminals, as shown in FIG. Therefore, in order to convert the data file of the test pattern for the device testing machine 4 into the pattern file for the workstation 2, the hexadecimal number is 2
It is necessary to convert to a base number and then to convert the data format.

For example, taking the data AA ₁₆ shown in FIG. 5 as an example, when this is expanded into binary numbers by 8 bits, both the upper 8 bits and the lower 8 bits are represented as 00010110 ₂ . In the device tester 4, 1 is set to high potential,
0 is associated with a low potential, and the first three cycles of the clock cycle are low potential, the next one cycle is high potential, the next one cycle is low potential, the next two cycles are high potential, and the last one. Low potential for the cycle,
And outputs the signal potential to the digital test circuit. In order to convert this into a pattern file for a workstation, first, the hexadecimal display data is developed in binary. Then, the binary expanded value is assigned to the matrix having the terminal number and the clock period as the row component and the column component one by one. For example, in FIG. 6, binary expanded data is assigned to a matrix having terminal numbers as row components and clock periods as column components. In the data shown in FIG. 6, the clock cycle is 160 nanoseconds and the number of terminals is 7.

In accordance with this data, the workstation associates 1 with a high potential and 0 with a low potential in step 111 from the data obtained in the above process,
The time of the potential change point and the potential after the change are obtained, and in step 112, a test pattern for simulation is created and output.

[0017]

As described above, according to the present invention, the test pattern for the logic simulation by the workstation is automatically generated by using the test pattern for the device tester used for the logic test of the digital circuit. Can be created in With this, the logical simulation
The effect is much easier and more accurate than before.

[Brief description of drawings]

FIG. 1 is a flowchart for creating a test pattern for simulation.

FIG. 2 is a conceptual diagram showing an outline of the configuration of a pattern file creation device.

FIG. 3 is an explanatory diagram showing the content of condition setting of a command file.

FIG. 4 is an explanatory diagram showing a waveform display example of a control signal of a device testing machine.

FIG. 5 is an explanatory diagram showing a data file for a device testing machine.

FIG. 6 is an explanatory diagram showing data of a test pattern for a simulator.

[Explanation of symbols]

 1 pattern input device 2 work station 4 device tester

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Masao Izumi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd.

Claims (1)

[Claims] 1. A command file for automatically creating a pattern file containing a test pattern for a simulation device from a test pattern for a device tester for performing a logic test of an actual digital logic circuit. A device for creating patterns for logical simulation.