JPH05181703A - Data processor - Google Patents

Abstract

PURPOSE:To protect the PC value of a preceding routine saved to a stack and a stack pointer value obtained after calling a subroutine. CONSTITUTION:In case of writing data in an area specified by the 1st register for saving a PC value to a PC stack instead of a normal stack and storing the initial value of PC stack pointer (PCSP) and the 2nd register for storing the value of the PCSP obtained after executing a subroutine instruction, an error is generated to interrupt processing. Consequently the generation of a change in a program flow due to the reading of an incorrect PC value or runaway can be prevented by protecting the PC value of a preceding routine from careless overwriting and distinguishing a stack for saving the PC value from a normal stack and debugging can easily be executed because of the protection of the PC value of the preceding routine.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data processing device having a debug support function and a stack pointer.

[0002]

2. Description of the Related Art Reading data from a normal memory,
When writing data to memory, it is common to specify the address of the memory involved in reading and writing and transfer the data, but the method of specifying the address is different from the usual case Data may be transferred in. A stack is a container for data that has a structure in which the previously put data comes out later. Putting data on the stack is called push, and putting data on the stack is called pop.
An address for pushing or popping data is designated by a stack pointer (hereinafter referred to as SP). The value of SP changes with push and pop operations and always points to the address of the data for which the newest stack operation has been performed, so the data pushed later is popped first.

Conventionally, a data processing device has a memory for storing a value of a program counter (hereinafter referred to as PC) of a routine for interrupting processing when a subroutine is called by a jump subroutine instruction (hereinafter referred to as JSR). Some use stacks as devices. In such a data processing device, [JS
R (jump destination effective address)]
After the return, the start address of the instruction is pushed to the stack as the PC value after restoration, and the jump destination effective address is set to the PC as the new PC value. After that, the instruction having the contents of the PC as the start address is fetched from the memory and the processing of the subroutine is started. At this time, the value of SP indicates the address of the stack that stores the PC value after the return of the previous routine pushed on the stack. If a return subroutine instruction (hereinafter referred to as RTS) is executed at the end of the subroutine, S
PC after recovery that was saved from the stack indicated by P
The value is popped and set in the PC, and the process is restarted from the instruction next to the JSR of the previous routine. At this time, the value of SP is JSR
It returns to the value before executing.

FIG. 5 is a subroutine 1 in which the JSR is executed in the middle of the main program in the conventional data processing apparatus.
It shows the flow of processing when invoking and the state of the stack before and after the execution of JSR. In FIG. 5, the main program consists of instructions A0, B0, JSR, and C0, and subroutine 1 consists of instructions A1, B1, and RTS. The start address of the memory in which the instruction A0 is stored is PC (A0), and the instructions B0, JSR, C0,
The head addresses of the memory storing A1, B1, and RTS are PC (B0), PC (JSR), and PC, respectively.
(C0), PC (A1), PC (B1), PC (RT
S). The jump destination effective address of JSR is assumed to be the start address PC (A1) of the memory in which the start instruction A1 of subroutine 1 is stored. The value of SP before JSR is executed is SP (0), and the value of SP after JSR is executed is SP (1). The JSR will be described below with reference to FIG.
The operation of will be described in detail.

During execution of the main program, [JSR PC
(A1)] is read, the value of SP is changed from SP (0) to SP (1) and the start address PC (C0) of the next instruction C0 of the main program JSR is pushed onto the stack as the PC value after restoration. To do. Next, the jump destination effective address PC (A1) designated by JSR is set in the PC, and the process of the subroutine 1 is started. When the instruction A1 having PC (A1) as the start address is sequentially read and executed and [RTS] is read at the end of subroutine 1, the value SP (1) of SP is saved as the start address from the stack. After returning, the PC value PC (C0) is popped, set in the PC, and the process returns to the main program.
The value of SP has returned to SP (0).

Further, FIG. 6 shows the flow of processing when n times of subroutine jumps are continuously performed in the conventional data processing apparatus, the state of the stack before JSR, and the nth J.
It shows the state of the stack after SR execution. The main program consists of instructions A0, ..., JSR, instructions C0 ,.
..., JSR, command C1, ..., RTS.
Similarly, the subroutine j is composed of instructions Aj, ..., JSR, instructions Cj ,. Instruction A0, instruction B
0, JSR, C0 are PC (A0) and PC (B
0), PC (JS0), and PC (C0) as the start addresses. Main program JS
The jump destination effective address of R is the address PC (A1) of the memory storing the first instruction A1 of subroutine 1.
Suppose Similarly, the instructions Aj and B of the subroutine j
j, JSR, Cj, and RTS are PC (Aj) and P, respectively.
C (Bj), PC (JSj), PC (Cj), PC (R
Tj) is stored in the memory having the start address as
The jump destination effective address of the JSR in the subroutine j is assumed to be the address PC (A (j + 1)) of the memory in which the head instruction A (j + 1) of the subroutine (j + 1) is stored. The SP value before the first JSR is executed is SP (0), and the SP value after the nth JSR is executed is SP (n). A detailed description will be given below with reference to FIG.

During execution of the main program, [JSR PC
(A1)] is read, the value of SP is changed from SP (0) to SP (1) and the start address PC (C0) of the next instruction C0 of the main program JSR is pushed onto the stack as the PC value after restoration. To do. Next, the jump destination effective address PC (A1) designated by JSR is set in the PC, and the processing of the subroutine 1 is started. Instructions are sequentially read from the instruction A1 having PC (A1) as the start address and executed, and [JSR PC (A
2)] is read, the SP value is changed from SP (1) to S
It is changed to P (2), and the start address PC (C1) of the next instruction C1 of the JSR of the subroutine 1 is pushed onto the stack as the PC value after restoration. Similarly, when the subroutine jump is executed n times and the process of the subroutine n is started, n pieces of data are pushed onto the stack and the value of SP is SP (n). When [RTS] is read at the end of subroutine n, the value S of SP from the stack
PC (C (n-1)) of the PC value after returning to the saved subroutine (n-1) with P (n) as the start address
Pops, sets it on the PC, and makes a subroutine (n-1)
Return to processing. The value of SP has returned to SP (n-1). Similarly, by continuing the processing while popping the data by n times of RTS commands and setting it in the PC, it is possible to return to the processing of the main program.

In the conventional data processing device, a stack frame generation instruction (hereinafter referred to as EN) is also used as an instruction for forming a stack frame for a high-level language and saving a register.
TER), and instructions to restore registers, release stack frames, and restore PC values (hereinafter referred to as EXI).
Some of them have TD).

FIG. 7 shows the flow of processing when ENTER is executed after calling subroutine 1 by JSR in the middle of the main program, the state of the stack before executing ENTER, and the state of the stack after executing ENTER. Is explained. In FIG. 7, the main program consists of instructions A0, B0, JSR, and C0, and the subroutine 1 is ENTER, ..., EXITD.
Consists of. The start address of the memory in which the instruction A0 is stored is PC (A0), and similarly the instructions B0, JSR, C0,
The start address of the memory where ENTER and EXIT are stored is PC (B0), PC (JSR), P
Let C (C0), PC (EN), and PC (EX). JS
The jump destination effective address of R is the start address P of the memory in which the start instruction ENTER of subroutine 1 is stored.
It is assumed that it is C (EN). S before JSR is executed
The values of P and FP are SP (0), FP (0), and JS, respectively.
The value of SP after R is executed is SP (1), ENTER
The SP and FP values after executing
(3) and SP (2). A detailed description will be given below with reference to FIG. 7.

[JSR PC
(EN)] is read, the value of SP is changed from SP (0) to SP (1), and the start address PC (C0) of the next instruction C0 of the main program JSR is pushed onto the stack as the PC value after restoration. To do. After that, the jump destination effective address PC (EN) designated by JSR is set in the PC, and the process of the subroutine 1 is started. When the instruction ENTER with PC (EN) as the start address is read and executed, the value FP (0) of FP before the execution of ENTER is pushed onto the stack, and the value SP (2) of SP is added to FP as the new F.
Store as P value. After that, the local variable area is secured on the stack and then the general-purpose register group is pushed. EN
The value of SP is SP (3) when all the stack pushes of the TER are completed. After the ENTER processing, the processing of subroutine 1 is executed, and at the end of subroutine 1, [E
XITD] is read, the SP value S from the stack
First, the value of the general-purpose register group is popped with P (3) as the start address, the FP value SP (2) is stored in SP to open the local variable area, and FP (0) is set as the FP value from the stack indicated by SP. , After the return, PC (C0) is popped as the PC value and set in FP and PC, respectively, and the process returns to the main program. The value of SP has returned to SP (0).

[0011]

Since the stack as described above is usually placed in a part of the memory, the start address of the next instruction of the previous routine is saved in the stack when the subroutine jump is performed as described above. In this method, the PC value is accidentally written to the location where the PC value is saved during the execution of the subroutine, or a push operation or a pop operation is performed to change the RT value while the value is different from the SP after JSR.
If S is executed, the PC value cannot be popped after returning from the previous routine that called the subroutine, and incorrect data will be set in the PC, and the flow of the program will change.
There was a problem that the program itself would be damaged or data would be destroyed due to a runaway, making debugging difficult.

If data is carelessly written to the FP during execution of the subroutine and ENTER is executed with the FP value changed, an incorrect SP value will be read, so the FP value in the previous routine is restored. There was a problem that it could not be done.

Further, if a push operation or a pop operation is performed during execution of a subroutine after forming a stack frame as in the conventional example and EXIT is executed with the value changed from SP after ENTER, an incorrect register value is popped. There was also a problem that the correct result could not be obtained.

The present invention has been made to solve the above problems, and the PC of the previous routine saved in the stack
To obtain a data processing device capable of protecting data such as a value and an FP value and checking the normality of a stack pointer value of a stack storing a PC value and an FP value and an SP value of a normal stack immediately after forming a stack frame. To aim.

[0015]

A data processing apparatus according to the first invention has the following elements. (A) a first stack for storing a predetermined type of data,
(B) a second stack that stores data other than the data stored in the first stack; (c) when storing data in the stack, whichever of the first and second stacks is used depending on the type of the data. Selection means for selecting or.

A data processing apparatus according to the second invention has the following elements. (A) A stack that stores predetermined data, and (b) a prohibition unit that prohibits writing to a used area of the stack.

A data processing apparatus according to the third invention has the following elements. (A) Stack for storing predetermined data, (b) Stack pointer indicating the top of the stack, (c) Holding means for holding the value of the stack pointer, (d) Value of the stack pointer and value of the holding means An inspection means for comparing the two and inspecting the destruction of the stack pointer.

The data processing apparatus according to the fourth aspect of the present invention is
The present invention is provided with a specifying means for specifying that the selecting means, the prohibiting means, and the inspecting means in the third invention are selectively operated.

[0019]

According to the first aspect of the invention, the selecting means stores the predetermined type of data such as the PC value and the FT value in the first stack, and the normal data other than the PC value and the FP value is stored in the second stack. Since the above data is stored, even if the second stack is destroyed, the predetermined type of data such as the PC value and the FP value in the first stack is protected.

According to the second aspect of the invention, since the prohibiting means prohibits writing to the area where the stack is used, the PC value and FP value saved in the stack and other data are protected.

According to the third aspect of the invention, the value of the stack pointer is changed after being compared with the value held by the holding means, so that the value of the stack pointer is changed after it is confirmed that the value of the stack pointer is normal. Be changed.

According to the fourth aspect of the invention, the designating means designates the selecting means, the inhibiting means, and the inspecting means to select and execute, so that the debugging work can be easily performed.

[0023]

【Example】

Example 1. An ordinary SP will be described below as an embodiment of the present invention.
Separately, a PC stack pointer (hereinafter referred to as PCSP) is provided as a stack pointer that points to a stack for saving PC values (hereinafter referred to as PC stack), and a register SR0 that holds the initial value of PCSP and a register that changes together with PCSP A bit that specifies whether to select the normal stack or the PC stack to save the PC value in the register that has SR1 and controls the debug environment, and prohibits writing to the PC stack when the PC stack is selected. The operation of the data processing device provided with the bit for specifying whether or not to carry out will be described with reference to FIGS.

FIG. 1 shows a data processing device of the present invention.
It shows the flow of processing when n times of subroutine jumps are continuously performed, the state of the PC stack before JSR, and the state of the PC stack after execution of the nth JSR. The main program is instructions A0, ..., JS
, R, instruction C0, ..., Subroutine 1 comprises instructions A1, ..., JSR, instruction C1, ..., RTS, and similarly, subroutine j comprises instructions Aj ,.
R, instruction Cj, ..., RTS. Instruction A0, instruction B0, JSR, C0 are PC (A0) and PC, respectively.
(B0), PC (JS0), and PC (C0) are stored in the memory having the start address. The jump destination effective address of the JSR of the main program is the address PC (A
1). Similarly, the instruction Aj of the subroutine j,
Bj, JSR, Cj, and RTS are PC (Aj),
PC (Bj), PC (JSj), PC (Cj), PC
(RTj) is stored in the memory having the start address, and the jump destination effective address of the JSR in the subroutine j is the address PC (A (j + 1)) of the memory in which the start instruction A (j + 1) of the subroutine j is stored. Suppose The value of PCSP before the first JSR is executed is PCSP (0), and the PC after the nth JSR is executed
The value of SP is PCSP (n).

Reference numeral 10 in FIG. 2 shows a debug environment control register of the data processor of the present invention. A PCD bit 11 specifies whether to save the PC value in the normal stack or in the PC stack. Reference numeral 12 is a PCW bit that specifies whether or not the PC stack is write-protected for the memory in the range of SR0 to SR1.

PCD bit 11 and PCW bit 1 of FIG.
When 2 is set, the value of the initial PCSP after reset is SR0 and S before the main program is executed.
It is transferred to R1. After that, the value of SR0 does not change until reset is applied. In the middle of the main program, click [JSR
PC (A1)] is read, the value of PCSP is changed to PC
It is changed from SP (0) to PCSP (1), and the start address PC (C
After returning 0), it is pushed to the PC stack as the PC value. When the value of PCSP changes, the value of SR1 also changes to PC
It changes to SP (1), and the contents of PCSP and SR1 are always the same. Next, the jump destination effective address PC (A1) designated by JSR is set in the PC, and the process of the subroutine 1 is started. Instruction A with PC (A1) as the start address
When instructions are sequentially read from 1 and executed, and [JSR PC (A2)] is read in the middle of subroutine 1, P
The value of CSP is changed from PCSP (1) to PCSP (2), and the start address PC (C1) of the next instruction C1 of the JSR of subroutine 1 is pushed onto the PC stack. At this time, the value of SR1 also becomes PCSP (2). Similarly, n
The value of PCSP is PCSP (n) and the value of SR1 is also PCSP (n) when the subroutine jump is executed a number of times and the process of the subroutine n is started. When [RTS] is read at the end of the subroutine n, PC (C (n-) of the PC value after returning to the subroutine (n-1) saved from the PC stack with the PCSP value PCSP (n) as the start address is read. 1)) is popped, it is set in the PC, and the process returns to the subroutine (n-1). PCSP
And SR1 become PCSP (n-1). Similarly, if the PC value is popped from the PC stack by n times of RTS instructions, it is possible to return to the processing of the main program.

For the write operation to all the memories in the subroutine, the address of the memory to be written is compared with the values of SR0 and SR1 and the address of the memory to perform the write operation is within the range of SR0 to SR1. A write-prohibit error is generated when If it is not within the range of SR0 to SR1, the writing is permitted and the processing is continued.

The stack push and pop in the subroutine are performed using normal SP, and the PC stack is JSR.
It is used only when pushing the PC value as shown in.

In the above embodiment, the PCD bit 11 of FIG.
And PCW bit 12 is set and PC value is pushed by P
Although it is decided to write to the C stack and prohibit writing to the PC stack, if the PCD bit 11 is cleared, the PC value is also saved in the normal stack, and the PCD bit 12 is ignored. If the PCW bit 12 is cleared even if the PCD bit 11 is set, the PC value is saved in the PC stack, but the write operation check to the PC stack is not performed.

As described above, the data processing apparatus according to this embodiment stores the second stack that stores the normal stack, the second stack pointer that is the stack pointer, and the stack for saving the program counter value. A first stack and a first stack pointer which is the stack pointer thereof, a first holding means for holding an initial value of the first stack pointer, and a change in the value of the first stack pointer. Second holding means for holding the same value as the first stack pointer value, selecting means for selecting whether or not to save the program counter value in the first stack, the first holding means, and the second The holding unit is provided with a prohibiting unit that prohibits writing to the area of the first stack.

Further, according to this embodiment, when the bit for designating whether to save the PC value to a stack different from the normal stack is set in the register for controlling the debug environment, the PC value is set to the normal PC value. Save to a stack different from the stack, and if the register that controls the debug environment has the bit that specifies whether writing to the stack different from the normal stack is set, Area designated by the first holding means for holding the initial value of the stack pointer for the stack and the second holding means for holding the stack pointer value of a stack different from the normal stack after the execution of the subroutine instruction When writing to this area is prohibited and an attempt is made to write data to this area, an error occurs and the processing is interrupted.

As described above, according to this embodiment, the PC value saved in the stack is protected from inadvertent overwriting of data, and the stack for saving the PC value is a stack for performing normal data push-pop. Since the stack pointer value of the stack that saves the PC value is not changed by dividing it with, it is possible to prevent the flow of the program from changing and runaway due to reading an incorrect PC value, and to protect the program itself and data. There is an effect that you can. In addition, the PC value of the previous routine is protected, which facilitates debugging.

Example 2. Hereinafter, as one embodiment of the present invention, a PC stack pointer (hereinafter referred to as PCSP) is provided as a stack pointer that points to a stack (hereinafter referred to as PC stack) for saving a PC value separately from a normal SP,
In addition, registers SR0 and JS that hold the initial value of PCSP
Register S that holds the value of PCSP after execution of R, and register S that holds the value of SP after execution of ENTER
PC with R2 in the register that controls the debug environment
A bit that specifies whether to select the normal stack or the PC stack to save the value, a bit that specifies whether to select the normal stack or the PC stack to save the FP value, and the PC P to save the value or FP value
When the C stack is selected, the operation of the data processing device having a bit for designating whether or not writing to the PC stack is prohibited will be described with reference to FIGS. 3 and 4.

FIG. 3 shows the data processing device of the present invention.
Subroutine 1 by JSR in the middle of the main program
This is a description of the flow of processing when executing ENTER after calling, the state of the stack before executing ENTER, and the state of the stack after executing ENTER. In FIG. 3, the main program is instruction A0,
It consists of B0, JSR, and C0, and subroutine 1 consists of ENTER, ..., EXITD. The start address of the memory where the instruction A0 is stored is PC (A
0), as well as the instructions B0, JSR, C0, ENTER, E
The start address of the memory in which XITD is stored is PC (B0), PC (JSR), PC (C0),
PC (EN) and PC (EX). The jump destination effective address of JSR is the start instruction ENTER of subroutine 1.
Is the start address PC (EN) of the memory in which is stored. SP, FP, PC before JSR is executed
The SP values are SP (0), FP (0), and PCSP, respectively.
(0), PCS value of PCSP after JSR is executed
P (1), SP after PC ENTER is executed, PCSP
Let SP (1) and PCSP (2) be the values of, respectively.

Reference numeral 10 in FIG. 4 indicates a debug environment control register. A PCD bit 11 specifies whether to save the PC value in the normal stack or in the PC stack. 1
Reference numeral 2 denotes an FPD bit, which specifies whether to save the FP value in the normal stack or the PC stack. 13 is a PC
W bit (1 bit) PC stack with SR0 to S

PCD bit 11 and FPD bit 1 of FIG.
2. When the PCW bit 13 is set, first reset the initial PCS before executing the main program.
The value of P is transferred to SR0 and SR1. After that, the value of SR0 does not change until reset is applied. When [JSR PC (EN)] is read in the middle of the main program,
The value of PCSP is changed from PCSP (0) to PCSP (1), and the head address PC (C0) of the next instruction C0 of the JSR of the main program is pushed onto the stack as the PC value after restoration. SR1 as soon as the value of PCSP changes
Also changes to PCSP (1), and always PCSP and SR1
Will be the same. Next, the jump destination effective address PC (EN) designated by JSR is set in the PC, and the processing of the subroutine 1 is started. First instruction EN of subroutine 1
When TER is read and executed, first, PCSP and SR1
Value of PC is changed from PCSP (1) to PCSP (2), the value FP (0) of FP before ENTER is pushed to the PC stack, and the value SP (0) of SP is stored in FP as a new FP value. To do. After that, the local variable area is secured on the stack and then the general-purpose register group is pushed. ENRE
When all stack pushes of R are completed, the value of SP becomes SP (2), and at the same time, the value of SR2 also becomes SP (2). After the ENTER processing, the processing of subroutine 1 is executed, and when [EXIT] is read at the end of subroutine 1, the SP value and the SR2 value are compared, and if they match, the SP value SP (2) from the stack is the start address. First, pop the values in the general-purpose register group, and then add the FP value SP
(0) is stored in SP and the local variable area is released.
Next, the previous routine FP value FP (0) saved from the PC stack is popped and stored in FP. PCSP is P
Change from CSP (2) to PCSP (1). Then P
After returning from the C stack, the PC value is popped and set in the PC, and the process returns to the main program. PCSP value is P
Returning to CSP (0).

In the above embodiment, the case where SP and SR2 match when EXIT is read has been described, but an error occurs when SP and SR2 do not match.

For the write operation to all memories in the subroutine, the address of the memory to be written is compared with the values of SR0 and SR1 and the address to perform the write operation is within the range of SR0 to SR1. When a write-protect error occurs. If it is not within the range of SR0 to SR1, the writing is permitted and the processing is continued.

The stack push and pop in the subroutine are performed by using the normal SP, and the PC stack is used only when pushing the PC value and the FP value.

In the above embodiment, the PCD bit 11 of FIG.
And FPD bit 12 and PCW bit 13 are set to P
The C value and FP value are pushed to the PC stack, and writing to the PC stack is prohibited. However, if the PCD bit 11 and the FPD bit 12 are cleared, the PC value and the F value are deleted.
The P value is also saved in the normal stack and PCD bit 13 is ignored. If PCW bit 12 is cleared even if PCD bit 11 and FPD bit are set, P
Although the C value and the FP value are saved in the PC stack, the write operation check to the PC stack is not performed.

As described above, the data processing device according to the present invention includes the second stack pointer which indicates the normal second stack, and the first stack pointer which indicates the first stack for saving the program counter value. A frame pointer that points to a stack frame, a first holding unit that holds the initial value of the first stack pointer, and the same value as the first stack pointer value with a change in the value of the first stack pointer. A second holding means for holding the value, a third holding means for holding the value of the second stack pointer immediately after the formation of the stack frame, and a program counter value for saving the program counter value in a normal stack Selection means for selecting whether to save to the stack for saving, and a program designated by the first holding means and the second holding means. Those comprising inhibiting means for inhibiting writing to the stack of ram counter value cache.

Further, according to this embodiment, when the bit for designating whether to save the PC value to a stack different from the normal stack is set in the register for controlling the debug environment, the PC value is set to the normal value. Saves to a stack other than the stack and stores FP in the register that controls the debug environment.
When the bit that specifies whether to save the value to a different stack from the normal stack is set, the FP value is saved to a different stack from the normal stack, and the normal stack is saved in the register that controls the debug environment. When the bit that specifies whether writing to a stack other than the above is prohibited, the first holding means for holding the initial value of the stack pointer for the stack different from the normal stack, and the instruction for the subroutine If you prohibit writing to the area specified by the second holding means that holds the stack pointer value of a stack different from the normal stack after execution, and try to write data to this area, an error will occur. Suspend processing. Also, when the stack frame release instruction is executed and the value of the stack pointer that points to the normal stack does not match the third holding means that holds the stack pointer value of the normal stack after the execution of the stack frame formation instruction, an error is generated. Occurs and interrupts processing.

As described above, according to this embodiment,
After the subroutine call by protecting the PC value and FP value of the previous routine saved in the stack from inadvertent overwriting of data, and separating the stack that saves the PC value and FP value from the stack that performs normal data push-pop Of P
Since the stack pointer value of the stack that saves the C value and FP value is not changed, it is possible to prevent changes in the program flow or runaway caused by reading the wrong FP value or PC value, and protect the program itself and data. The effect is that you can. In addition, the PC value of the previous routine is protected, which facilitates debugging. Furthermore, since the SP value immediately after forming the stack frame is held and compared with the SP value at the time of executing EXIT, there is an effect of preventing an incorrect register value from being popped.

[0044]

As described above, according to the first invention, since the stack is divided into two, even if one stack is destroyed, the other data is protected.

Further, according to the second aspect of the invention, since writing to the stack is prohibited, the data in the stack is protected.

Further, according to the third invention, since the value of the stack pointer is held separately, it is possible to check the normality of the value of the stack pointer.

Further, according to the fourth invention, the above-mentioned first to third
Since the invention of (1) can be selectively operated, the debugging work becomes easy by using it when debugging.

[Brief description of drawings]

FIG. 1 is a flow chart of processing when n sub-routine jumps are continuously performed in a data processing device of the present invention, a state of a stack area before the first JSR, and a state of a stack area after execution of the n-th JSR. It is the figure shown about.

FIG. 2 is a diagram showing registers that control a debug environment of the data processing device of the present invention.

FIG. 3 is a diagram showing a flow of processing when an ENTER instruction is executed in the data processing device of the present invention, and a PC stack and a state of the stack after execution of the ENTER.

FIG. 4 is a diagram showing registers that control a debug environment of the data processing device of the present invention.

FIG. 5 is a diagram showing a flow of processing when a subroutine 1 is called by JSR while a main program is being executed in a conventional data processing device, and a state of a stack area before and after execution of JSR.

FIG. 6 is a flow of processing when a conventional data processing device performs n times of subroutine jumps in succession and the first J
It is the figure which showed the state of the stack area | region before SR and the state of the stack area | region after execution of n-th JSR.

[FIG. 7] E after calling subroutine 1 by JSR during execution of a main program in a conventional data processing device
It is a figure explaining the flow of processing at the time of performing NTER, the state of the stack before performing ENTER, and the state of the stack after performing ENTER.

[Explanation of symbols]

 10 Register for controlling debug environment of the present invention 11 PCD bit 12 FPD bit 13 PCW bit

Claims (4)

[Claims] 1. A data processing device comprising: (a) a first stack for storing data of a predetermined type;
(B) a second stack that stores data other than the data stored in the first stack; (c) when storing data in the stack, whichever of the first and second stacks is used depending on the type of the data. Selection means for selecting or. 2. A data processing device comprising: (a) a stack that stores predetermined data; and (b) a prohibition unit that prohibits writing to a used area of the stack. 3. A data processing device comprising: (a) a stack for storing predetermined data; (b) a stack pointer indicating the beginning of the stack; and (c) a holding means for holding the value of the stack pointer. , (D) inspection means for inspecting the destruction of the stack pointer by comparing the value of the stack pointer with the value of the holding means. 4. The data processing device according to claim 1, 2, or 3, further comprising a specifying unit that specifies that the selecting unit, the prohibiting unit, or the checking unit is selectively operated. The data processing device according to 1, 2, or 3.