JPH0518154B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to an information processing device having a graph display function, and more particularly to a graph display device that displays a graph with an abbreviated waveform.

[Prior art and its problems]

Generally, when creating various graphs on paper, wavy lines (abbreviated waveforms) as shown in Figure 1 are sometimes used to omit part of the scale due to paper size constraints or scaling considerations. .
However, in the past, in information processing equipment such as office computers, when displaying graphs on a CRT monitor, graphs were not displayed using wavy lines (abbreviated waveforms), which was inconvenient.

Therefore, it is conceivable to provide these information processing devices with a graph display function with wavy lines (abbreviated waveforms). A conceivable means for achieving this is to prepare a wavy line (abbreviated waveform) display pattern and directly overwrite the graph pattern. However, with this means, as shown in FIG. 2, the graph and the wavy lines (omitted waveforms) are displayed overlapping each other, making it difficult to see and unnatural.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and an object thereof is to provide a graph display device that has a simple configuration and yet displays graphs with wavy lines in an easy-to-read and natural state.

[Embodiments of the invention]

FIG. 3 shows a schematic configuration of an information processing device according to an embodiment of the present invention. In the figure, 10 is a disk file in which various data such as sales data is stored, and 20 is a classification/aggregation unit that classifies and aggregates the data stored in the disk file 10 and creates a data table. Classification/aggregation section 20
The data table created is stored in another area of the disk file 10. Reference numeral 30 denotes an autoscaling control section, which performs scaling based on the maximum value, minimum value, etc. of the data in the data table stored in the disk file 10. The autoscaling control section 30 then creates an x, y axis table and writes it into a graphics memory (not shown) within the graph drawing control section 40. Next, the autoscaling control unit 30 creates a graph from the data table stored in the disk file 10,
The data is written to the graphics memory in the graph drawing control section 40. In this way, the graph is overwritten on the x and y axis table. That is, a graph pattern is written into the graphic memory. The operations up to this point are performed using conventional techniques.

Next, the autoscaling control unit 30 outputs information specifying the abbreviated waveform display applicable area of the graph drawing control unit 40 to the graph drawing control unit 40 in order to write the abbreviated waveform to the graphic memory in the graph drawing control unit 40. At the same time, an activation signal is output to the abbreviated waveform drawing control section 50. In addition,
The abbreviated waveform display applicable area is an area where the graph and the abbreviated waveform overlap, as shown in FIG. 2, and refers to the area where the abbreviated waveform is drawn. As a result, the graph pattern in the abbreviated waveform display area of the graphics memory is read out in predetermined bit units and supplied to the abbreviated waveform drawing control section 50. This abbreviated waveform drawing control section 5
0 has the function of generating two types of patterns related to omitted waveforms (a pattern applied to display erasure of the waveform area of omitted waveforms and a pattern applied to display of omitted waveforms), and auto scaling control. These two types of patterns are generated in units of predetermined bits in response to an activation signal from the section 30. Further, the abbreviated waveform drawing control section 50 has two types of logical addition functions (AND addition and OR addition). The abbreviated waveform drawing control unit 50 then AND-adds the display erasing pattern with the graph pattern in the abbreviated waveform display corresponding area in predetermined bit units, thereby creating a graph in which each bit corresponding to the abbreviated waveform area is turned OFF. Get the pattern. Next, the abbreviated waveform drawing control section 5
0, the graph pattern obtained in this manner and the display pattern described above are OR-added in predetermined bit units to obtain a graph pattern with an abbreviated waveform. This graph pattern with the abbreviated waveform is written in the original area of the graphics memory in the graph drawing control section 40 in units of predetermined bits. By displaying the screen on the CRT monitor 60 using the contents of this graphics memory, the graph with abbreviated waveforms is displayed in a natural state.

The outline of one embodiment of the present invention has been described above. Next, one embodiment of the present invention will be described in detail with reference to FIGS. 4 to 6. FIG. 4 mainly shows the main configurations of the graph drawing control section 40 and the abbreviated waveform drawing control section 50. In the same figure, 3
1 is an address control signal generating section. The address control signal generation section 31 is an autoscaling control section 3.
0, and outputs an address to the graph drawing control section 40 and an activation signal to the abbreviated waveform drawing control section 50 when creating a graph pattern with an abbreviated waveform. Graph drawing control unit 40
has a graphics memory 41 in which graph patterns are stored, an address control device 42 that generates addresses for the graphics memory 41, and a graphics control device 43 that performs read/write control for the graphics memory 41. . The abbreviated waveform drawing control unit 50 also includes an AND pattern memory 51 and an AND pattern memory 51.
Address control device 5 that generates an address for
2, an OR pattern memory 53, an address control device 54 that generates an address for the OR pattern memory 53, an AND circuit 55, and an OR circuit 56.

OR pattern memory (first pattern memory) 5
3, for example, an OR pattern (first
Seed pattern) PTN1 is stored in 16-bit row (horizontal) pattern units. This OR pattern
PTN1 is the basic waveform that is the constituent unit of the abbreviated waveform,
For example, it is bit pattern data necessary to display a one-cycle waveform. On the other hand, the AND pattern memory (second pattern memory) 51 stores an AND pattern (second type pattern) PTN2 having a 16×16 bit configuration, as shown in the operation explanatory diagram of FIG.
Stored in 16-bit row (horizontal) pattern units. This AND pattern PTN1 is bit pattern data necessary for display erasing the area within the first half period waveform. However, in this embodiment, each bit corresponding to the area within the 1-cycle waveform is turned ON, and each bit corresponding to the area outside the 1-cycle waveform is OFF.

When a graph pattern with an abbreviated waveform is required, the autoscaling control unit 30 stores data in the graphic memory 41 that corresponds to each one-cycle waveform display area constituting the abbreviated waveform display area determined by scaling. The address control signal generator 31 sequentially generates the start address of each area. Further, the autoscaling control section 30 also generates a start signal from the address control signal generation section 31 when the above-mentioned first address is generated. This activation signal is sent to the address control device 5 in the abbreviated waveform drawing control section 50.
I am led to 2,54. Thereby, the address control devices 52 and 54 sequentially generate addresses for the corresponding AND pattern memory 51 and OR pattern memory 53 from, for example, address 0 to the final address at respective timings. As a result, the AND pattern PTN2 is read out from the AND pattern memory 51 in units of 16-bit row patterns starting from the first row pattern. Further, from the OR pattern memory 53, the OR pattern PTN1 is similarly read out in 16-bit row pattern units starting from the first row pattern (at a timing delayed from the above-mentioned AND pattern PTN2 by, for example, the delay time of the AND circuit 55). AND pattern memory 5
The 16-bit row pattern read from 1 is
It is led to one input part of the AND circuit 55. Also,
The 16-bit row pattern read from OR pattern memory 53 is guided to one input of OR circuit 56.

On the other hand, the start address generated from the address control signal generation section 31 (that is, the start address of a certain one-cycle waveform display area in the graphics memory 41) is guided to the address control device 42 in the graph drawing control section 40. The data is loaded into an address counter (not shown) of the address control device 42. As a result, the first address is supplied as an address to the graphics memory 41. The address control device 42 repeatedly increments an address counter at a predetermined timing, and stores an address string following the above-mentioned top address corresponding to the one-cycle waveform display area in the graphics memory 41 (specified by the autoscaling control section 30). are output one address at a time. As a result, the area corresponding to the designated one-cycle waveform display in the graphics memory 41 is designated by the address string starting from the above-mentioned top address. The graphics control device 43 is configured to first execute a read cycle and then execute a write cycle in response to one address output from the address control device 42. Now, considering only the read cycle as appropriate, the designation of the address output from the address control device 42 causes the graphics memory 4
1, the graph patterns within the area corresponding to the one-cycle waveform display are read out in units of 16-bit row patterns starting from the first row pattern. This indicates that the graph pattern GPTN1 within the area corresponding to the one-cycle waveform display is cut out from the graphic memory 41, as shown in the operation explanatory diagram of FIG. The 16-bit row pattern read from graph memory 41 is guided to the other input of AND circuit 55.

The AND circuit 55 is composed of 16 two-input AND gates (not shown), and receives the 16-bit row pattern level inversion data read from the AND pattern memory 51 and the 16-bit row pattern data read from the graphics memory 41. AND the row pattern in a bit-wise manner. As a result, in the 16-bit row pattern read from the graphics memory 41, the bits (group of bits) that overlap with the area within one period of the waveform are turned OFF. The output of AND circuit 55 (16-bit row pattern) is led to the other input of OR circuit 56.

The OR circuit 56 is composed of 16 two-input OR gates (not shown), and combines the 16-bit row pattern output from the AND circuit 55 and the 16-bit row pattern read from the OR pattern memory 53. OR addition based on bit correspondence. This creates a row pattern with abbreviated waveforms.

At this point, the graphics control device 43 switches the cycle from the read cycle to the write cycle. As a result, the 16-bit row pattern output from the OR circuit 56 is stored in the graphic memory 4.
1 is written to the original address location.

The above operation is performed by one
By repeating the graph pattern GPTN1 stored in the periodic waveform display area in row pattern units, as shown in the operation explanatory diagram of FIG. All OFF
A graph pattern GPTN2 is obtained as an intermediate result, and a graph pattern GPTN3 in which a one-period waveform (OR pattern PTN1) is superimposed on the graph pattern GPTN2 is obtained as a final result. This graph pattern GPTN3 is written into the area of the graphics memory 41 where the graph pattern GPTN1 was stored. That is,
Graph pattern in graphic memory 41
GPTN1 is rewritten to graph pattern GPTN3. In addition, an AND pattern memory 51, an OR pattern memory 53, and a graphic memory 41
The read timing of is determined by the AND circuit 55.
AND pattern PTN2 and graph pattern GPTN1
AND addition is performed on the row patterns of the same row, and in the OR circuit 56, the OR pattern PTN1
The timing is such that the OR addition between the graph pattern GPTN2 and the graph pattern GPTN2 is performed on the row patterns of the same row.

As is clear, by performing the above-mentioned processing on all the one-cycle waveform display corresponding areas constituting the abbreviated waveform display applicable area in the graphic memory 41, the graph pattern with the abbreviated waveform is stored in the graphic memory 41. can do. By displaying the screen on the CRT monitor 60 using the graph pattern with the abbreviated waveform stored in the graphic memory 41, the graph with the abbreviated waveform is displayed in a natural and easy-to-see state as shown in FIG. .

In addition, although the case of the graph in the vertical direction was explained in the above embodiment, it can be similarly applied to the case of the graph in the horizontal direction. However, when reading from the AND pattern memory 51 and the OR pattern memory 53, so-called vertical and horizontal conversion is required.

Further, the present invention can also be applied to color graph display. However, in this case, the above-mentioned AND addition is
It is necessary to perform this for all R, G, and B graph patterns. On the other hand, OR addition needs to be performed only on AND addition results corresponding to display colors.

〔Effect of the invention〕

As described in detail above, according to the present invention, a graph with abbreviated waveforms (wavy lines) is displayed in an easy-to-read and natural state despite having a simple configuration.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a graph with an abbreviated waveform drawn on a paper, FIG. 2 is a diagram showing an example of a conventional screen display of a graph with an abbreviated waveform, and FIG. 3 is information related to an embodiment of the present invention. FIG. 4 is a block diagram showing a schematic configuration of the processing equipment. FIG. 4 is a block diagram mainly showing the main structure of the graph drawing control section and omitted waveform drawing control section shown in FIG. 3. FIG. 5 is a block diagram showing the operation related to creating a graph with omitted waveforms. The explanatory diagram, FIG. 6, is a diagram showing an example of a screen display of a graph with an abbreviated waveform. 30...Auto scaling control section, 40...
Graph drawing control unit, 41...Graphic memory, 50...Abbreviated waveform drawing control unit, 51...
AND pattern memory, 53...OR pattern memory, 55...AND circuit, 56...OR circuit.

Claims (1)

[Claims] 1 means for storing graph pattern data, means for storing pattern data of omitted waveforms, means for storing pattern data for graph erasure for erasing omitted waveform areas, and means for storing pattern data for graph erasure based on the pattern data for graph erasure. It is characterized by comprising means for erasing the graph pattern data in the waveform area, and means for superimposing and writing the pattern data of the omitted waveform in the omitted waveform area of the graph pattern data erased by the erasing means. graph display device.