JPH05181436A - X driving circuit and liquid crystal driving device - Google Patents

Abstract

PURPOSE:To make a multicolor and gradational display without increasing the circuit scale nor the number of voltage input pins for liquid crystal application by providing a voltage dividing circuit and obtaining a gradational display having >=(n) gradations. CONSTITUTION:For example, a 6-bit latch circuit 3 latches 6-bit display data 1 with a clock 2 to obtain latch data. A voltage selector 14 inputs voltages 5-13 and the high-order three bits of the latch data 4 in the latch circuit 3 and selects voltages of two levels among the voltages 5-13 of nine levels according to the value of the high-order three bits. In this case, resistances 17-24 are connected in series, and output voltages 15 and 16 of the voltage selector 14 are connected to both the ends; and the output voltage 25 of the resistances 17 and 8 is outputted from their resistance connection point, the output voltage 26 of the resistances 18 and 19 is outputted from their connection point, and the output 31 of the resistances 23 and 24 is outputted from their connection point. Then the output voltage 23 of a voltage selector 32 is amplified by an amplifying circuit 34 to obtain an output 35.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device capable of multi-gradation / multi-color display, and more particularly to an X drive circuit, a liquid crystal drive device and a drive system for an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art There is a system using a HD66310T described in Hitachi LCD Driver LSI Data Book (1990 edition: P650-663) as a liquid crystal driving device for displaying multi-gradation / multi-color. This method is a method of selecting an 8-level voltage by using eight switching elements. But,
In this method, if the number of selection voltages is increased above eight levels, the number of switching elements increases correspondingly and the cost of the driver increases. In addition, when the number of selection voltages increases, the number of input pins of the driver increases and the chip area of the driver increases, which is an obstacle to miniaturization. Further, when the number of input pins is increased, a high mounting technique is required when mounting the driver, and the production cost is not taken into consideration.

A conventional technique will be described below with reference to FIG. 7 as an example. FIG. 7 is a block diagram of a conventional 8-level voltage application method.

Reference numeral 300 is 3-bit display data, 301 is a latch circuit, 302 is a clock, and 303 is 3-bit latch data. The latch circuit 301 fetches the 3-bit display data 300 in synchronization with the clock 302 and latches it. Output as data 303. 304 is a voltage selector, 305 to 312 are outputs S0 to S7 of the voltage selector, and the voltage selector 304 is a 3-bit latch data 3
03 is decoded, and one of the outputs S0 to S7 is set to "high" and the rest is set to "low" according to the decoding. 31
3 to 320 are liquid crystal application voltages, which are V0 to V7, respectively.
It has the voltage value shown by. 321 to 328 are switching elements, and 330 is an output to the liquid crystal. The outputs S0 to S7 of the voltage selector 304, the voltages 313 to 320, and the output 330 to the liquid crystal are connected to the switching elements 321 to 328, respectively. When the output of the voltage selector 304 is "high", the voltage and the liquid crystal are outputted. When the output 330 is ON, and the output of the voltage selector 304 is “low”, the voltage and the output 330 to the liquid crystal are OFF.

Next, the operation of this circuit will be described.
The latch circuit 301 outputs the display data 300 to the clock 30.
It is fetched in synchronization with 2 and output as latch data 303. The latch data 303 is decoded by the voltage selector 304. The voltage selector 304 sets one of the outputs S0 to S7 of the voltage selector 304 to "high" according to the decode signal. That is, when the decode value is "0", the output S0 of the voltage selector 304, "1"
, The output S1, ..., “7” of the voltage selector 304
In this case, the output S7 of the voltage selector 304 is set to "high". As a result, the switching element connected to the output of the voltage selector 304 which becomes “high” becomes conductive,
The voltage connected to the switching element is applied to the liquid crystal via the output 330 to the liquid crystal.

For example, when the display data 300 is "low, high, high", the latch data 303 also becomes "low, high, high", so that the output S3 of the voltage selector 304 becomes "high" by the voltage selector 304. The switching element 324 becomes conductive, and the voltage value V3 given to the voltage 316 is applied to the liquid crystal through the output 330 to the liquid crystal. As described above, the voltages V0 to V7 can be selected according to the value of the display data 300 and applied to the liquid crystal. Since the light transmittance of liquid crystal changes depending on the applied voltage value, when the present liquid crystal driving device is used, a display having a gradation of 8 levels for each pixel can be obtained.

[0007]

In the above driving method, when the number of gradations is further increased, the number of voltages input to the liquid crystal driving device increases, so that the number of pins and the circuit scale of the liquid crystal driving device are increased. The number is increasing, and accordingly, high packaging technology is required. Further, the large scale of the drive circuit hinders downsizing of the system and space saving. In addition, the size of the liquid crystal driving device for multicolor increases, resulting in an increase in cost, which hinders multicolor display of the liquid crystal and cost reduction.

An object of the present invention is to realize a liquid crystal driving device and a driving method capable of multicolor / multigradation display without increasing the circuit scale or the number of voltage input pins for applying liquid crystal.

[0009]

The above-mentioned object is to supply a liquid crystal applied voltage from the outside to the X drive circuit in a number smaller than the number of gray scales, and by the voltage selector 1, the high order n1 bits (n1) of the display data.
According to <n), 2 levels out of the 2n1 + 1 level voltage supplied from the outside are selected, the selected 2-level voltage is input to the voltage dividing circuit, and the voltage of 2n 2 level is selected. Lower n2 bits of generated data (n2 <n, n1
+ N2 = n), 2 n generated by the voltage dividing circuit
This can be achieved by selecting one level voltage of the square level voltage by the voltage selector 2 and then amplifying the selected voltage by the amplifier circuit and using the liquid crystal drive circuit which propagates to each display pixel portion.

As another means, a voltage bus which supplies a liquid crystal applied voltage smaller than the number of gray scales from the outside and divides it by a voltage dividing circuit inside the X drive circuit to form a voltage bus for propagating the output voltage of the voltage dividing circuit is formed. Then, the voltage selector in each X drive circuit selects one level from the voltage bus for the voltage corresponding to the display data, and the selected circuit amplifies the selected voltage. This can be achieved by using a liquid crystal drive circuit that propagates to each display pixel portion.

[0011]

With the above structure, in the present invention, since the voltage dividing circuit is provided inside the X driving device, a voltage according to the display data can be generated by simply supplying the liquid crystal applied voltage smaller than the number of gradations from the outside. Can be applied to each pixel, and the increase in the number of input pins of the X drive circuit and the increase in circuit scale can be suppressed to the minimum. Further, the liquid crystal material, the voltage level, and the like can be changed by changing the level of the voltage supplied from the outside.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A first embodiment of the present invention will be described below with reference to FIGS.
This will be described with reference to FIG. In the present embodiment, an example will be described in which the number of gradations is 64 and the display data per pixel is 6 bits. 1 is a block diagram of an X drive circuit corresponding to one display pixel, FIG. 2 is a simple block diagram of a liquid crystal drive circuit of the present invention, and FIG. 3 is a simple block diagram of a liquid crystal display device of the present invention.

In FIG. 1, 1 is 6-bit display data having binary data of "high" and "low" per bit, 2 is a clock, 3 is a 6-bit latch circuit, and 4 is a 6-bit latch. The 6-bit latch circuit 3 latches the 6-bit display data 1 with the clock 2 as the latch data of the circuit 3 to obtain the latch data 4.

Reference numerals 5 to 13 are 9-level externally supplied voltages, 14 is a voltage selector, and 15 and 16 are output voltages of the voltage selector.
3 and the upper 3 bits of the latch data 4 of the latch circuit 3 are input, and the 2 level voltage is selected from the 9 level voltages 5 to 13 according to the value of the upper 3 bits. Selected 2
The level voltage becomes the output voltages 15 and 16 of the voltage selector.

17 to 24 are resistors, 25 to 31 are output voltages generated by voltage division by the resistors 17 to 24, 32 is a voltage selector, 33 is an output voltage of the voltage selector 32, 34 is an amplifier circuit, and 35 is an amplifier circuit. It is an output, and resistors 17 to 24 are connected in series, and the voltage selector 1
4, the output voltages 15 and 16 are connected, the resistance output voltage 25 is from the connection point of the resistors 17 and 18, the resistance output voltage 26 is from the connection point of the resistors 18 and 19, ..., The resistances 23 and 24.
The output voltage 31 of the resistor is output from each of the connection points. Output voltage 25 to 31 generated by resistors 17 to 24
Up to the voltage values of the output voltages 15 and 16 are internally divided by the ratio of resistance values. The voltage selector 32 inputs the internally divided output voltages 25 to 31 and the lower 3 bits of the latch data 4 of the latch circuit 3, and outputs the output voltages 18 and 2.
One voltage corresponding to the 3-bit latch data 4 is selected from the 8-level voltages 5 to 31 and is set as the output voltage 33 of the voltage selector 32. This output voltage 33 is
The amplified signal is amplified by the amplifier circuit 34 and used as the output 35. 36 is a voltage applying circuit, and the voltage applying circuit 36 is a voltage selector 14
And resistors 17 to 24, voltage selector 32, and amplifier circuit 34
It consists of.

The voltage applying circuit 36 can select one of the voltages corresponding to the 6-bit display data 1 from the 64 levels of the voltage obtained by internally dividing the 8 sets of voltages into 8 levels.

FIG. 2 shows a simple block diagram of a liquid crystal drive circuit provided with a plurality of X drive circuits corresponding to one display pixel shown in FIG. In this embodiment, a liquid crystal drive circuit corresponding to 160 pixels is shown.

Reference numeral 50 is a shift register, 51 is an input carry signal from the previous liquid crystal drive circuit, 52 is an output carry signal to the next liquid crystal drive circuit, 53 is a clock, 54 is an output clock of the shift register 50, and shift The register 50 is an input carry signal 51 from the previous liquid crystal drive circuit.
Is high, the S0 to S160 of the output clock 54 are sequentially output in synchronization with the clock 53.
"High" for 1 clock of. When it becomes "high" until S160, the output carry signal 52 to the next liquid crystal drive circuit is made "high". Reference numeral 55 is a 6-bit display data bus, which transfers display data in synchronization with the clock 53. Reference numeral 56 is a latch circuit, 57 is latch data of the latch circuit 56, and the latch circuit 56 is the shift register 50.
When the output clock 54 is high, the display data on the display data bus 55 is latched and used as latch data 57. For example, the output S0 of the shift register 50 is "high".
At this time, the latch circuit 56-0 latches the display data,
The latch data is 57-0. 58 is a latch circuit, and 59
Is the latch data of the latch circuit 58, and is clock 2
Is a latch circuit 5 to which one horizontal display data corresponds.
It is generated after being captured in 6. The latch circuit 58 is
The latch data 57 of the latch circuit 56 at the previous stage is latched in synchronization with the clock 2 and used as the latch data 59. Since the clock 2 is connected to the liquid crystal drive circuit for one line, the latch circuit 58 for one line operates simultaneously. 6
Reference numeral 0 is a voltage application circuit, 61 is an output voltage of the voltage application circuit 60, and 62 is a voltage bus. The voltage selector 60 inputs the latch data 59 of the latch circuit 58, and outputs the voltage corresponding to the latch data 59 of multiple levels. One of the liquid crystal application voltage buses 62 is selected and used as the output 61. This output 6
Reference numerals 1 are each connected to one display pixel of the active matrix type liquid crystal panel.

The latch data 57 is obtained by parallelizing the display data 1 shown in FIG. 1 for 160 pixels, and a latch circuit 58.
1 is the one in which the latch circuit 3 shown in FIG. 1 is provided in parallel for 160 pixels, the latch data 59 is the one in which the latch data 4 shown in FIG. 1 is provided in parallel for 160 pixels, and the voltage application circuit 60 is shown in FIG.
160 voltage applying circuits 36 shown in parallel are provided,
The output voltage 61 is the output voltage 33 shown in FIG. 1 arranged in parallel for 160 pixels, and 62 is the voltage 5 to 13 shown in FIG.

FIG. 3 is a simple block diagram of a liquid crystal display device provided with a plurality of liquid crystal drive circuits corresponding to the 160 pixels shown in FIG. In this embodiment, one horizontal line is 192
A liquid crystal display device having 0 pixels and 480 vertical lines will be described.

Reference numeral 100 is a display data bus, 101-0 to 101-11 are 160-output liquid crystal drive circuits, 102 is a power supply, and 103 is a clock. The liquid crystal drive circuit 101 is
Display data corresponding to each pixel is sequentially read from the display data bus 100 in synchronization with the clock 53, and a voltage corresponding to the display data is selected and output. The power supply 102 generates multi-level voltage, outputs it as the voltage bus 62, and supplies it to each liquid crystal drive circuit 101. Further, the power source 102 synchronizes the voltage applied to the liquid crystal in synchronization with the clock 103. Reference numeral 104 denotes a Y drive circuit having an output of 480, and 105 and 10.
6 is a clock, and the Y drive circuit 104 is a clock 10
After resetting the shift register in the Y drive circuit 104 in synchronization with 6, the value of the shift register in the Y drive circuit 104 is changed in synchronization with the clock 105.
When the shift register of the Y drive circuit 104 counts the clock 105 n times after reset and the nth output becomes “high”, the Y drive circuit 104 outputs “high” from the output Yn, and outputs from other outputs. Outputs “low”. 1
Reference numeral 07 denotes a signal source, 108 denotes an active matrix type liquid crystal panel, and the signal source 107 generates each clock and display data. The output of the Y drive circuit 104 is connected to the horizontal lines of the active matrix type liquid crystal panel 108, and the output of the liquid crystal drive circuit 101 is connected to the vertical lines.

Reference numeral 109 is a carry signal, and the carry signal 109-0 becomes "high" after the liquid crystal drive circuit 101-0 latches the display data for 160 pixels. In the liquid crystal drive circuit 101-1, the carry signal 109-0 is "high".
After that, the display data for 160 pixels is sequentially latched in synchronization with the clock 53, and the carry signal 109-1 is set to "high". This operation is sequentially performed by the liquid crystal drive circuit 101.
Repeat from -1 to 101-11.

The operation of the liquid crystal display device will be described with reference to FIG.

The Y drive circuit 104 has a built-in shift register of 480 outputs, resets the shift register at the clock 106, changes the value of the shift register in synchronization with the clock 105, and sequentially outputs the outputs Y0 to Y479. High ” The output of the Y drive circuit is connected to the horizontal line of the active matrix type liquid crystal panel 108,
The switching element of the display pixel connected to one horizontal line that has become "high" becomes conductive, and the liquid crystal drive circuit 10
The voltages X0 to X1919 of the outputs 1-0 to 101-11 are applied to each display pixel. The liquid crystal drive circuits 101-0 to 101-11 synchronize the display bus 1 in synchronization with the clock 53.
00 to output X0 to X1919, the display data corresponding thereto are sequentially latched, and the signal source 107 outputs the clock 2 after outputting the display data for one line. The liquid crystal drive circuits 101-0 to 101-11 synchronously output the voltages corresponding to the latched display data from the outputs X0 to X1919 in synchronization with the clock 2. The liquid crystal drive circuit 1
01-0 to 101-10 are carry signals 1 to the next liquid crystal drive circuit when the display data for 160 pixels is latched.
09-0 to 109-10 are sequentially set to "high". The liquid crystal drive circuits 101-1 to 101-11 latch the display data in synchronization with the clock 53 when the carry signals 109-0 to 109-10 are "high". The voltages corresponding to the display data are the liquid crystal drive circuits 101-0 to 10-10.
The voltage of the voltage bus 62 input to 1-11 is divided inside the liquid crystal drive circuits 101-0 to 101-11, and one level is selected from the divided voltages.

The operation of the liquid crystal drive circuit will be described with reference to FIG.

When the carry signal 51 output from the liquid crystal drive circuit in the preceding stage is "high", the shift register 50 synchronizes with the clock 53 and outputs the output clock 54 from S0 to S15.
9 is sequentially set to "high" for one clock. When S0 of the output clock 54 becomes "high", the latch circuit 56-0
Latches the display data on the display data bus 55 and outputs the latch data 57-0. Next, when the clock 53 becomes “high”, the shift register 50 outputs the output clock 5
S0 of 4 is set to "low", and S1 of the output clock 54 is set to "high". When S1 of the output clock 54 becomes "high", the latch circuit 56-1 latches the display data on the display data bus 55 and outputs the latch data 57-1. In this operation, the shift register 50 outputs the output clock 5
S159 of 4 is set to "high", and the latch circuits 56-159
Repeatedly latches the display data from the display data bus 55 and outputs latch data 57-159, and thereafter,
The shift register 50 makes the carry signal 52 "high". Latch circuit 58-0 when clock 2 goes high
58 to 159 are latch data 57-0 to 57-1
59 is latched, and latched data 59-0 to 59-15
9 is output. Latch data 59-0 to 59-159
Is input to the voltage application circuits 60-0 to 60-159,
The voltage bus 62 is input, the voltage is divided by the voltage dividing circuit, one of the voltages corresponding to the latch data 59-0 to 59-159 is divided, and the selected voltage is amplified by the amplifying circuit. To output 61-0 to 61-159.

The operations of the latch circuit 58 and the voltage application circuit 60 will be described in detail with reference to FIG.

When the display data 1 is "high, low, high, high, low, low, low", the latch circuit 3 displays the display data 1 "high, low, high, high, high" when the clock 2 becomes "high". Latch data “Low, Low” and latch data 4 “High, Low, High, High,
Outputs "low, low". Upper 3 of this latch data 4
The bits “high, low, high” are input to the voltage selector 14. The voltage selector 14 selects the voltage 10 corresponding to the upper 3 bits of the latch data 4 and the voltage 11 corresponding to the data “high, high, low” which is 1 higher than the upper 3 bits of the latch data 4, and the voltage 10 is the output voltage. 15 and the voltage 11 is output as the output voltage 16. Voltage 8
, V9, and the voltage value of the voltage 16 is V8, the voltage value of the output voltage 15 is V5, and the voltage value of the output voltage 16 is V6. This output voltage 15 is input to the next voltage selector 32. Further, the resistors 17 to 24 are connected in series between the output voltage 15 and the output voltage 16, and the voltage internally divided by the resistors is set as the output voltages 25 to 31, and the voltage selector 32 inputs the voltage. The voltage selector 32 inputs the lower 3 bits “high, low, low” of the latch data 4. The voltage selector 32 selects the output voltage 28 corresponding to the lower 3 bits “high, low, low” of the latch data 4 and sets it as the output voltage 33 of the voltage selector 32. When the resistance value of each resistor is equal to R, the voltage value of the output voltage 28 is V5 + 4 × R / (8 × R) ×
(V6-V5), and the output voltage 33 has the same value. The output voltage 33 is input to the amplification circuit 34, and the amplification circuit 3
When the voltage amplification factor of 4 is 1, the voltage value of the output 35 of the amplifier circuit is V5 + 4 × R / (8 × R) × (V6-V5). A voltage value V5 + 4 × R / (8 × R) × (V6-V5) corresponding to display data “high, low, high, high, low, low” is applied to the display pixel to which the output 35 is connected. , Get the brightness that matches the display data.

After the latch circuit 3, the X driving circuits corresponding to the display pixels of one line simultaneously operate, so that the lines where the output of the Y driving circuit is "high" can display at the same time.

The resistance values may not be equal. For example, assuming that the resistance value of the resistor 17 is R0, ..., And the resistance value of the resistor 24 is R8, the voltage value of the output voltage 33 is V5 + (R0
+ ... + R3) / (R0 + ... + R8) * (V6-V5).

According to this embodiment, the number of externally supplied voltages can be made smaller than the number of gradations.

Further, as shown in FIG. 2, the X drive circuits for a plurality of display pixels are accommodated in one LSI, whereby the liquid crystal drive circuit can be downsized.

FIG. 4 shows a second embodiment in which the voltage of 9 levels supplied from the outside is reduced to 2 levels in the first embodiment. FIG. 4 is a block diagram of an X drive circuit corresponding to one display pixel.

Reference numerals 150 and 151 denote supply voltages from an external power source, 152 to 159 are resistors, 160 to 166 are output voltages generated by the resistors 152 to 159, and the resistor 15
2 to 159 are connected in series, and supply voltages 150 and 151 from an external power supply are connected to both ends of the series resistance. Output voltages 160 to 166 generated by the resistors 152 to 159 are output from the connection points of the resistors, and output voltages 160 to 1
The voltage of 9 levels of 66 and the supply voltages 150 and 151 from the external power supply are input to the voltage selector 14. Resistor 152
The voltage values of the outputs 160 to 166 generated in steps 159 to 159 are values obtained by internally dividing the voltages 150 and 151. 167,
168 is an amplifier circuit, 169 and 170 are amplifier circuits 167,
The amplifier circuits 167 and 168, which are the outputs of 168, amplify the output voltages 15 and 16 of the voltage selector 14 and further perform impedance conversion.

When the upper 3 bits of the latch data 4 of the latch circuit 3 are "high, low, low", the voltage selector 14
Selects the fourth output voltage 163 and the fifth output voltage 164, which is one higher. When the voltage values of the supply voltages 150 and 151 are V0 and V1, respectively, and the resistance values of the resistors 152 to 159 are equal to R, the voltage value of the output voltage 163 is
V0 + 4 × R / (8 × R) × (V1-V0), and the voltage value of the output voltage 164 is V0 + 5 × R / (8 × R) ×
(V1-V0). Output voltage 163 is output voltage 1
5, the output voltage 164 becomes the output voltage 16, which is input to the amplifier circuits 167 and 168, respectively, is amplified and impedance-converted, and becomes the outputs 169 and 170. The purpose of impedance conversion is to connect resistors 152 to 159 and resistor 17
The reason is that Nos. 24 to 24 are not parallel resistance circuits.

Other operations are similar to those of the first embodiment.

According to this embodiment, the number of voltages supplied from the outside can be made smaller than the number of gradations.

The values of the resistors do not have to be equal as described in the first embodiment. Further, the size can be reduced by accommodating the X drive circuits for several pixels in one LSI.

When the display data is 6 bits, the first embodiment
In 2, the upper and lower bits are divided into 3 bits, but the upper 2 bits and the lower 4 bits may be divided. For example, using FIG. 1 used in the first embodiment, the number of bits input to the voltage selector 14 is 2, the voltage supplied from the outside is 5 levels, the number of resistors connected in series is 16, and the voltage selector This can be handled by setting the number of bits input to 32 to 4 bits.

Further, the increase in the number of bits of display data can be dealt with by increasing the number of resistors used in the first and second embodiments, the number of inputs of the voltage selector, and the number of stages of the voltage selector.

A third embodiment of the present invention will be described in detail with reference to FIGS. FIG. 5 shows a simple block of the liquid crystal drive circuit, and FIG. 6 shows a voltage dividing circuit. In the present embodiment, the output of the series resistance is used by a plurality of voltage selectors.

In FIG. 5, 200 is a 9-level voltage bus, 201 is a voltage dividing circuit, 202 is a 64-level voltage bus, 203 is a voltage applying circuit, and the voltage dividing circuit 201 is
A 9-level voltage is input from the 9-level voltage bus 200, divided into 64-level voltages, and the 64-level voltage bus 202 is output. The 64-level voltage bus 202 is
Input to the voltage selector 203. Voltage application circuit 203
Is 1 corresponding to the display data from 64 level voltage
A level voltage is selected and amplified to output 61.

FIG. 6 shows an example of the voltage dividing circuit 201 for dividing the voltage from 9 levels to 64 levels. 210 to 21
8 (212 to 216 are not shown) is a 9-level voltage supplied from the outside, 220-1 to 220-63 (22
0-9 to 220-54 are not shown) are resistors, 230-
1 to 230-55 (230-8 to 230-47 not shown) is an output voltage generated by the resistors 220-1 to 220-63, and the resistors 220-1 to 220 are provided between the voltages.
0-63 are connected in series, and output voltages 230-1 to 230-55 are output from the connection points of the resistors and the voltage 210
Through 218 form the voltage bus 202 of FIG. For example, a resistor 220-1 between the voltages 210 and 211.
To 220-7 are connected in series, and output voltages 230-1 to 230-6 are output from the connection points between the resistors. Voltage 2
Resistors 220-8 to 220 between 11 and 218
-63 are connected in series in sequence of 8 each. From the connection point of the resistor between each voltage, output voltage 230-7 to 230-5
5 is output. By doing so, it is possible to obtain a voltage of 9 levels and a divided voltage of 55 levels, so that a total of 64 levels of voltage can be generated and a voltage bus 202 having a voltage of 64 levels can be formed. 5 to the voltage application circuit 203. The voltage application circuit 203 selects one voltage corresponding to the 6-bit latch data 59, amplifies it by an amplifier circuit in the voltage application circuit, and outputs it.

According to this embodiment, it is possible to reduce the number of externally supplied voltages and the number of resistors used in one LSI.

The number of resistors between each voltage may be arbitrary, as long as the number of voltages on the voltage bus corresponds to the number of gradations. Further, as the number of gradations increases, the number of supply voltages and the number of resistors may be changed. You can deal with it by increasing it.

Also in the other embodiments, the output of one voltage dividing circuit may be used in a plurality of circuits as in the third embodiment.

In the first, second and third embodiments, the voltage dividing circuit is used in the sixth embodiment.
Although the example of four gradation display is shown, the number of voltages obtained by the voltage dividing circuit does not have to be equal to the number of displayed gradations, and the number of gradations may be equal to or more than the number of voltages supplied from the outside. ..

[0048]

According to the present invention, since the number of externally input voltages due to the multicolor of the liquid crystal device can be reduced, the number of input terminals of the liquid crystal drive circuit can be reduced. Further, since the number of voltages generated by the external power source can be reduced, the scale of the power source circuit can be reduced. Due to these effects, it can be expected that multi-color / multi-gradation display can be performed with a small number of power supplies and input terminals.

[Brief description of drawings]

FIG. 1 is a block diagram of a 64-gradation voltage dividing system according to an embodiment of the present invention.

FIG. 2 is a block diagram of an X drive circuit according to an embodiment of the present invention.

FIG. 3 is a block diagram of a liquid crystal display device according to an embodiment of the present invention.

FIG. 4 is a block diagram of a 64-gradation voltage dividing system according to an embodiment of the present invention.

FIG. 5 is a block diagram of an X drive circuit according to an embodiment of the present invention.

FIG. 6 is a block diagram of a 64-gradation voltage dividing circuit according to an embodiment of the present invention.

FIG. 7 is a block diagram of a conventional 8-level voltage application system.

[Explanation of symbols]

1 ... Display data 2 ... Clock 3 ... Latch circuit 4 ... Latch circuit 3 output 5-13 ... Voltage 14 ... Voltage selector 15, 16 ... Voltage selector 14 output 17-24 ... Resistor 25-31 ... Resistor output voltage 32 ... voltage selector 33 ... output of voltage selector 32 34 ... amplifier circuit 35 ... output of amplifier circuit 36 ... voltage application circuit 50 ... shift register 51 ... input carry signal from previous liquid crystal drive circuit 52 ... to next liquid crystal drive circuit Output carry signal 53 ... Clock 54 ... Output clock of shift register 50 55 ... Display data bus 56 ... Latch circuit 57 ... Latch data 58 ... Latch circuit 59 ... Latch data 60 ... Voltage applying circuit 61 ... Output voltage 62 ... Voltage bus 100 ... Display data bus 101-0 to 101-11 ... 160 output liquid crystal drive circuit 102 ... electric Reference numeral 103 ... Clock 104 ... 480-output Y drive circuit 105, 106 ... Clock 107 ... Signal source 108 ... Active matrix type liquid crystal panel 109 ... Carry signal 150, 151 ... Supply voltage from external power supply 152-159 ... Resistors 160-166 ... Output voltage 167, 168 generated by resistors 152-159 ... Amplification circuit 169, 170 ... Output of amplification circuit 167, 168 200 ... Voltage bus 201 ... Voltage dividing circuit 202 ... Voltage bus 203 ... Voltage application circuit 210-218 ... Supply voltage 220-1 to 220-63 ... Resistance 230-1 to 230-55 ... Resistance 220-1 to 220-
Output voltage 300 generated by 63 ... Display data 301 ... Latch circuit 302 ... Clock 303 ... Latch data 304 ... Voltage selector 305-312 Output of voltage selector 313-320 Liquid crystal application voltage 321-328 Switching element 330 ... Output to liquid crystal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor ▲ Hiroyuki Nono 292 Yoshida-cho, Totsuka-ku, Yokohama-shi, Kanagawa, Ltd. Inside Hitachi, Ltd. Microelectronics Device Development Laboratory (72) Inventor Tsutomu Furuhashi Totsuka-ku, Yokohama-shi, Kanagawa Hitachi, Ltd. Microelectronics Device Development Laboratory, 292, Yoshidacho (72) Inventor Tetsuya Suzuki, 292, Yoshidacho, Totsuka-ku, Yokohama, Kanagawa Pref., Hitachi Image Information Systems (72) Inventor, Koji Takahashi, Mobara, Chiba, Japan 3300 Address Hitachi Ltd. Mobara Plant (72) Inventor Satoru Tsunekawa 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Stocks Ltd. Semiconductor Design Development Center

Claims (12)

[Claims] 1. An active matrix liquid crystal panel comprising a switching element and a liquid crystal to form each display pixel portion, and a voltage corresponding to display data in which one pixel is composed of k bits (k: integer) is generated for gray scale display. In the liquid crystal display device including the X drive circuit, the power is supplied to the X drive circuit from the outside.
X is characterized in that a voltage dividing circuit for dividing each voltage into m voltages (n <m) is provided to obtain gradation display of n gradations or more.
Drive circuit. 2. The display data of k bits according to claim 1, wherein k1 bits (k1 <k, k1: integer) are n.
A two-level voltage selector that selects two voltages from the two voltages, a voltage dividing circuit that divides the two voltages output from the two-level voltage selector, and k among the k-bit display data.
An X drive circuit characterized by comprising a divided voltage selector for selecting one voltage of the outputs of the voltage dividing circuit with 2 bits (k2 <k, k2: integer). 3. The method according to claim 2, wherein n = 1 + 2 to the power k1,
An X drive circuit, wherein k = k1 + k2. 4. A liquid crystal drive device of a liquid crystal display device, wherein the X drive circuit according to claim 2 or 3 is housed in one LSI chip for at least one pixel or more. 5. An LS containing the liquid crystal driving device according to claim 4.
A liquid crystal display device characterized by being capable of simultaneously driving display pixels of one line by using one or more I chips. 6. The voltage according to claim 1, wherein two voltages are supplied from the outside, and n voltages are generated by the first voltage dividing circuit, and k
A 2-level voltage selector that selects two voltages from the n voltages by k1 bits of the bit display data;
A voltage divider circuit that divides two voltages output from the two-level voltage selector and a voltage divider voltage selector that selects one voltage of the output of the voltage divider circuit by k2 bits of k-bit display data are provided. An X drive circuit characterized by the above. 7. The method according to claim 6, wherein n = 1 + 2 to the power k1.
An X drive circuit, wherein k = k1 + k2. 8. The X drive circuit according to claim 6, at least 1.
A liquid crystal drive device of a liquid crystal display device, characterized in that more than the pixels are contained in one LSI chip. 9. An X drive circuit housed in one LSI chip according to claim 6, wherein n voltages generated by the first voltage dividing circuit are input to a two-level voltage selector for several pixels. A liquid crystal driving device of a liquid crystal display device. 10. A liquid crystal display device, wherein one line of display pixels can be simultaneously driven by using one or more LSI chips containing the liquid crystal drive device according to claim 8. 11. A voltage dividing circuit for dividing n voltages supplied from the outside and a voltage bus for propagating an output voltage of the voltage dividing circuit according to claim 1, wherein the voltage bus is X drive for several pixels. An X drive circuit connected to a circuit and housed in one LSI chip. 12. A liquid crystal display device, wherein one line of display pixels can be simultaneously driven by using one or more LSI chips containing the liquid crystal drive device according to claim 11.