JPH05180960A - Delay-time measuring apparatus - Google Patents

Delay-time measuring apparatus

Info

Publication number
JPH05180960A
JPH05180960A JP36034391A JP36034391A JPH05180960A JP H05180960 A JPH05180960 A JP H05180960A JP 36034391 A JP36034391 A JP 36034391A JP 36034391 A JP36034391 A JP 36034391A JP H05180960 A JPH05180960 A JP H05180960A
Authority
JP
Japan
Prior art keywords
delay time
difference
attenuation
circuit
delay
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP36034391A
Other languages
Japanese (ja)
Inventor
Toshibumi Igarashi
俊文 五十嵐
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP36034391A priority Critical patent/JPH05180960A/en
Publication of JPH05180960A publication Critical patent/JPH05180960A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To improve the measuring accuracy of a delay-time measuring apparatus for measuring a delay time by switching the amount of attenuation in response to the input level of a received signal. CONSTITUTION:A transmitting signal (a) outputted from a transmitting-signal generating circuit 1 is used. Thus, the difference in delay times caused by the difference in attenuation amounts of a digital-controlled attenuator 3 is measured before hand in response to the attenuation amount with a phase-difference measuring circuit 4 and a microcomputer 5. The difference is stored in a memory circuit 6. The delay time, which is measured by using the received signal (b) from an external circuit, is corrected by the time difference stored in the memory circuit 6.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明はデータ遅延時間測定装置
に関し、特に自装置内遅延時間の自動補正を行う遅延時
間測定装置に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data delay time measuring device, and more particularly to a delay time measuring device for automatically correcting the delay time in its own device.

【0002】[0002]

【従来の技術】従来の遅延時間測定装置は、装置外部の
回路を通ることによる遅延時間を測定する際に、入力信
号レベルを内部で一定にするためにアッテネータのアッ
テネーション量を制御している。そして、予め自装置内
遅延時間を測定しておき、外部回路経由の遅延時間測定
値から自装置内遅延時間を減算して外部回路の遅延時間
を求めている。ここで、自装置内遅延時間の測定時に
は、アッテネータを固定のアッテネーション量で行って
いる。
2. Description of the Related Art A conventional delay time measuring device controls the amount of attenuation of an attenuator in order to keep an input signal level internally when measuring a delay time caused by passing through a circuit outside the device. The internal device delay time is measured in advance, and the internal device delay time is subtracted from the delay time measurement value via the external circuit to obtain the external circuit delay time. Here, when measuring the delay time in the device itself, the attenuator is used with a fixed amount of attenuation.

【0003】[0003]

【発明が解決しようとする課題】このため、従来の遅延
時間測定装置では、外部回路の入力信号レベルを一定に
するためにアッテネーション量を変化させたときの自装
置内遅延時間の変化については測定値に対して補正され
ることはなく、高精度な遅延時間の測定が困難になると
いう問題がある。本発明の目的は、遅延時間を高精度に
測定することができる遅延時間測定装置を提供すること
にある。
Therefore, in the conventional delay time measuring device, the change in the delay time in the device itself when the amount of attenuation is changed in order to keep the input signal level of the external circuit constant is measured. There is a problem that it is difficult to measure the delay time with high accuracy because the value is not corrected. An object of the present invention is to provide a delay time measuring device that can measure the delay time with high accuracy.

【0004】[0004]

【課題を解決するための手段】本発明は、受信信号の入
力レベルに対応して切り換えるアッテネータのアッテネ
ーション量の差による遅延時間の差をアッテネーション
量に対応して予め測定する手段を有しており、計測時に
アッテネーション量に応じて計測遅延時間を補正する。
The present invention has means for previously measuring the difference in delay time due to the difference in the attenuation amount of the attenuator, which is switched according to the input level of the received signal, in correspondence with the attenuation amount. , Corrects the measurement delay time according to the amount of attenuation during measurement.

【0005】[0005]

【作用】予め測定したアッテネーション量の差に対する
遅延時間の差を、計測時にアッテネーション量に応じて
計測遅延時間を補正することで、アッテネーション量の
変化による自装置内遅延時間の変化を補正することがで
きる。
[Function] By correcting the difference in delay time with respect to the difference in attenuation amount measured in advance, by correcting the measurement delay time according to the attenuation amount at the time of measurement, it is possible to correct the change in the delay time in the device itself due to the change in the attenuation amount. it can.

【0006】[0006]

【実施例】次に、本発明について図面を参照して説明す
る。図1は本発明の装置の一実施例のブロック図であ
る。送信信号発生回路1から発生した信号は入力信号切
換スイッチ2をCAL側にすることにより自装置内で折
り返され、ディジタル制御アッテネータ3を経由して位
相差計測回路4に入力される。位相差計測回路4では、
送信信号発生回路1からの信号とディジタル制御アッテ
ネータ3からの自装置内折り返し受信信号との位相差を
計測する。マイクロコンピュータ5はディジタル制御ア
ッテネータ3へ制御信号を出力し、アッテネーション量
を変化させながら、位相差計測回路4で測定した位相差
データを入力し、アッテネーション量に対応させた自装
置内遅延時間として記憶回路6に格納する。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the device of the present invention. The signal generated from the transmission signal generating circuit 1 is turned back in the device by setting the input signal changeover switch 2 to the CAL side, and is input to the phase difference measuring circuit 4 via the digital control attenuator 3. In the phase difference measuring circuit 4,
The phase difference between the signal from the transmission signal generation circuit 1 and the in-house folded reception signal from the digital control attenuator 3 is measured. The microcomputer 5 outputs a control signal to the digital control attenuator 3, inputs the phase difference data measured by the phase difference measuring circuit 4 while changing the amount of attenuation, and stores it as a delay time in its own device corresponding to the amount of attenuation. It is stored in the circuit 6.

【0007】次に、入力信号の切換スイッチ2をOPR
側にすることにより、装置外部の回路を通ることによる
遅延時間を測定する構成となるが、このとき受信信号の
入力レベルによってディジタル制御アッテネータ3のア
ッテネーション量をマイクロコンピュータ5が自動的に
制御する。このときのアッテネーション量はマイクロコ
ンピュータ5で保持しており、外部回路経由の遅延時間
測定値からアッテネーション量に対応した自装置内折り
返し遅延時間を減算し、外部回路の遅延時間を算出す
る。
Next, the input signal changeover switch 2 is set to OPR.
By setting it to the side, the delay time due to passing through a circuit outside the device is measured. At this time, the microcomputer 5 automatically controls the attenuation amount of the digital control attenuator 3 according to the input level of the received signal. The amount of attenuation at this time is held by the microcomputer 5, and the loopback delay time in the own device corresponding to the amount of attenuation is subtracted from the delay time measurement value via the external circuit to calculate the delay time of the external circuit.

【0008】[0008]

【発明の効果】以上説明したように本発明は、受信信号
の入力レベル調整のためのアッテネータのアッテネーシ
ョン量の変化による自装置内遅延時間の変化を補正する
ことができるので、高精度な遅延時間の測定が可能にな
るという効果がある。
As described above, according to the present invention, since it is possible to correct the change in the delay time in the device itself due to the change in the attenuation amount of the attenuator for adjusting the input level of the received signal, the delay time with high precision can be obtained. Has the effect of enabling measurement of.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例のブロック図である。FIG. 1 is a block diagram of an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 送信信号発生回路 2 入力信号切換スイッチ 3 ディジタル制御アッテネータ 4 位相差計測回路 5 マイクロコンピュータ 6 記憶回路 1 Transmission signal generation circuit 2 Input signal changeover switch 3 Digital control attenuator 4 Phase difference measurement circuit 5 Microcomputer 6 Storage circuit

Claims (1)

【特許請求の範囲】[Claims] 【請求項1】 送信信号と、この送信信号と同一の周波
数を有する受信信号との位相差を測定し、送信と受信の
遅延時間を測定する遅延時間測定装置において、受信信
号の入力レベルに対応して切り換えるアッテネータのア
ッテネーション量(減衰量)の差による遅延時間の差を
アッテネーション量に対応して予め測定する手段を有
し、計測時にアッテネーション量に応じて計測遅延時間
を補正するように構成したことを特徴とする遅延時間測
定装置。
1. A delay time measuring device for measuring a phase difference between a transmission signal and a reception signal having the same frequency as the transmission signal to measure a delay time between transmission and reception, which corresponds to an input level of the reception signal. It has a means to measure beforehand the difference in delay time due to the difference in the attenuation amount (attenuation amount) of the attenuator that is switched in accordance with the attenuation amount, and is configured to correct the measurement delay time according to the attenuation amount during measurement. A delay time measuring device characterized by the above.
JP36034391A 1991-12-30 1991-12-30 Delay-time measuring apparatus Pending JPH05180960A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP36034391A JPH05180960A (en) 1991-12-30 1991-12-30 Delay-time measuring apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP36034391A JPH05180960A (en) 1991-12-30 1991-12-30 Delay-time measuring apparatus

Publications (1)

Publication Number Publication Date
JPH05180960A true JPH05180960A (en) 1993-07-23

Family

ID=18468993

Family Applications (1)

Application Number Title Priority Date Filing Date
JP36034391A Pending JPH05180960A (en) 1991-12-30 1991-12-30 Delay-time measuring apparatus

Country Status (1)

Country Link
JP (1) JPH05180960A (en)

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