JPH05176183A - Memory control circuit - Google Patents

Abstract

PURPOSE:To obtain a memory control circuit keeping the same operating characteristic as that of an SRAM even when an inexpensive DRAM is used as a memory. CONSTITUTION:A recording/read speed of luminance signal data and color difference signal data to DRAMs 14, 14' is quickened more than a transmission speed of input/output data to a memory control section by using shift registers 42, 43 and shift registers 32, 33. Then a load address is increased periodically in the recording and read of the data to the DRAMs 14, 14', and address allocation is implemented to increase load addressing periodically and to repeat it, then no refreshing is required and all data are continuously processed. Thus, the same data processing by an SRAM is implemented regardless of the use of a DRAM.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control circuit for storing image data input in line order or block order in a temporary memory, converting a data array in block order or line order, and reading it from the memory.

[0002]

2. Description of the Related Art When an image is digitized and recorded on a recording medium of some kind, a technique for storing a huge amount of information on a recording medium having a limited capacity is required. An image compression technique is one of them, and the DCT (Discrete Cosine Transform) compression method has become the main focus recently.

FIG. 6 shows the configuration of a still image file device using the DCT compression method. First, a signal processing method for recording an image will be described. The image pickup unit 10 performs signal processing on the picked-up image and supplies it to the memory control unit 60 as image data. The memory control unit 60 stores the image data in the memory 61 in line order. Then, after storing the image data for one screen, the image data is read for each block of 8 × 8 pixels and supplied to the DCT unit 15. The DCT unit 15 orthogonally transforms the supplied image data block by block, and the encoder 1
Supply to 6. The encoder 16 encodes and compresses the data and records it on the recording medium 17.

When reproducing an image, the compressed code data extracted from the recording medium 17 is expanded and decoded by the decoder 18,
The DCT unit 15 performs inverse orthogonal transform to convert the image data into image data, which is then supplied to the memory control unit 60. The memory control unit 60 stores the image data for each block in the memory 61 for one screen. After that, the image data is read from the memory 61 in line order and displayed on the image receiving unit 12 via the video processing unit 11.

Next, a data transfer and recording method will be described with reference to FIGS. 7 and 8. FIG. 7 shows interlaced image data. The interlace system is a system in which two fields form one screen, and the first field is composed of even lines and the second field is composed of odd lines. Each field is composed of 244 lines, and one line is composed of 768 data. As shown in FIG. 8, these data have addresses A0 to A9 in the horizontal direction of the image and A10 to A1 in the vertical direction of the image in the memory 61.
Record in a form corresponding to 8. Although an unused area is generated in the memory 61, it is not related to the present invention.

FIG. 9 shows the order of reading data. As shown in this figure, 1D0 to 1D7 are read out, followed by 2D0, and finally 8D7. In this way, one screen
It is divided into × 96 blocks and read.

As described above, the role of the memory controller 60 is complicated. Moreover, since the image data processing must be performed at high speed, what is adopted for the memory 61 is an important point. To perform image data processing at high speed, it is easiest to use SRAM (static RAM) as the memory 61. Some of the current SRAMs have a 1 Mbit capacity and can be read / written for 70 ns, and can be easily used as an image memory.
However, SRAM is a DRAM (dynamic RA
There is a problem that the price per capacity is much higher than that of M).

On the other hand, DRAM is mainly 4 Mbit at present and the price is low. One screen is divided into about 768 × 488 pixels, the luminance signal (Y) and the color difference signals (Cr, Cb) have an accuracy of 8 bits, and the ratio of the luminance signal to the color difference signal is Y: Cr: Cb = 4 :. In the case of the specification of 2: 2, it is possible to sufficiently cope with the capacity by using a 4 Mbit DRAM configured by 512 kbytes × 8 bits for each of the luminance signal and the color difference signal. Therefore, considering the price of the entire device and the number of mounted devices, it is most desirable to use the 4M bit DRAM.

However, when comparing DRAM with SRAM, the cycle time of random access is slow (about 10
0 ns) and refreshing are required. In the case of 768 × 488 pixels in the normal NTSC system, the sampling frequency of the image data is 14.3 MHz
This is before and after, and about 70 ns is required for the memory read / write cycle. For this reason, the fast page mode is used because it is not possible to use the DRAM normally. In the ordinary DRAM addressing method, a row address corresponding to a row and a column address corresponding to a column are specified for each data. On the other hand, in the fast page mode, the row address is first set and then only the column address is updated to shorten the setting time. Moreover, in the case of image data, the fact that there is a blanking period between line data is used, a row address is set in this blanking period, and the column address is updated in synchronization with the data It is possible to continuously read and write line data.

However, in the case of a 4 Mbit DRAM composed of 512 kbytes × 8 bits, the column address is 51
There is only 2 and the data for one line (768 bytes)
Can not perform continuous fast page mode. Further, since access for each block is close to random access, the transfer rate is low, and a refresh operation is required during data transfer. Therefore, the time required for the compression encoding process becomes long, and the functional deterioration of important elements such as the recording time required for continuous recording and the high-speed image reproduction at the time of reproduction cannot be avoided.

[0011]

When an SRAM is used as a memory for high-speed image data processing, the DR
The price per capacity is much higher than that of AM. Considering the number of mounted devices, it is most desirable to use a 4M bit DRAM. However, when comparing DRAM with SRAM, there are problems that the cycle time of random access is slow (about 100 ns) and refresh is necessary. For this reason, the fast page mode is used because it is not possible to use the DRAM normally.

However, in the case of a 4 Mbit DRAM composed of 512 kbytes × 8 bits, the column address is 51
There is only 2 and the data for one line (768 bytes)
Can not perform continuous fast page mode. Further, since access for each block is close to random access, the transfer rate is low, and a refresh operation is required during data transfer. Therefore, the time required for the compression encoding process becomes long, and the functional deterioration of important elements such as the recording time required for continuous recording and the high-speed image reproduction at the time of reproduction cannot be avoided.

It is an object of the present invention to provide a memory control circuit which maintains an operation performance equivalent to that of an SRAM even if an inexpensive DRAM is used as the memory.

[0014]

The means according to the present invention records in the image data of the approximate memory supplied in line order, N
In a memory control circuit that converts into a block composed of × M (N, M: integer) pixels and reads out, or records image data of each block in a memory and reads out in line order,
At least two storage means for temporarily storing N words are provided, and read / write access is performed in a high-speed access mode in units of N words, and all valid row addresses are periodically repeated in a short period.

[0015]

By the above means, even if a DRAM is used as a memory, there is no need to refresh and all data can be processed continuously at high speed. As a result, the same data processing as SRAM can be performed even though it is a DRAM.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS First, before explaining a memory control circuit according to the present invention, an overall structure of a filing apparatus will be explained. FIG. 5 is a diagram showing the overall configuration of the filing device. In this figure, the imaging unit 10 performs signal processing on the captured image,
The image data is supplied to the memory controller 13. The memory control unit 13 stores the image data in a line order as a memory DR.
Store in AM14. Then, after storing the image data for one screen, the image data is read for each block of 8 × 8 pixels,
It is supplied to the DCT unit 15. The DCT unit 15 orthogonally transforms the supplied image data for each block and supplies the image data to the encoder 16. The encoder 16 encodes and compresses the data and records it on the recording medium 17.

When reproducing an image, the decoder 18 decompresses the compressed code data extracted from the recording medium 17,
The DCT unit 15 performs inverse orthogonal transform to convert the image data into image data, which is then supplied to the memory control unit 13. The memory control unit 13 stores the image data for each block in the DRAM 14 for one screen. After that, the image data is read from the DRAM 14 in line order and displayed on the image receiving unit 12 via the video processing unit 11.

Next, the configuration of an embodiment according to the present invention will be described with reference to the drawings. FIG. 1 is a diagram showing a configuration of a memory control circuit according to the present invention. This corresponds to the memory control unit 13 in FIG. The luminance signal and the color difference signal supplied from the image pickup unit 10 are supplied to the YW bus 25 and the CW bus 27 via the terminals 20 and 21 and the I / O cells 22 and 23, respectively.

The brightness signal will be described below. The luminance signal is alternately held by the shift registers 42 and 43 via the selector 41. Here, the operation clock of the shift register 42 is SFA, and the operation clock of the shift register 43 is SFB. The outputs of the shift registers 42 and 43 are both input to the selector 44, and the selector 44 selects either one based on the control signal SL, and the I / O cell 46 is selected.
Is supplied to the DRAM 14 via.

By the way, from the control section 50 to the DRAM
A row address and column address setting clocks CAS and RAS are supplied to 14, and an address signal is supplied from the address generator 51. The DRAM 14 records the luminance signal data based on these signals.

On the other hand, when the data of 8 × 8 pixels is read from the DRAM 14, the output data of the DRAM 14 is I / O.
It is supplied to the FF (flip-flop) 48 via the cell 47. Then, the data delayed by the FF 48 is transferred to the selector 41
It is held alternately by the shift registers 42 and 43 via.
The selector 44 selects one of the outputs of the shift registers 42 and 43, and outputs the YR bus 2 via the I / O cell 45.
Output to 4. This data is output from the terminal 30 via the I / O cell 28.

When data of 8 × 8 pixels is supplied from the terminal 30, the data is supplied from the I / O cell 28 to the YW bus 25. The recording / reproducing method for the DRAM 14 is as described above. The data read from the DRAM 14 is transferred via the YR bus 24 and the I / O cell 22.
Output from the terminal 20.

Although the processing system for the color difference signal is different from that for the luminance signal, the configuration and operation are exactly the same. CW bus 27
The upper color difference signal is sent to the shift register 3 via the selector 31.
2 and 33 are alternately held and both outputs are input to the selector 34. After selecting either one, the I / O cell 3
It is supplied to the DRAM 14 'via 6 and recorded.

On the other hand, when the data of 8 × 8 pixels is read from the DRAM 14 ', the output data of the DRAM 14' is I
After being delayed by the FF 38 via the / O cell 37, they are supplied to the shift registers 32 and 33 via the selector 31 and held alternately. The selector 34 selects one of the outputs of the shift registers 32 and 33 and outputs it to the CR bus 26 via the I / O cell 35. This data is output from the terminal 30 via the I / O cell 29.

When color difference data of 8 × 8 pixels is supplied from the terminal 30, the data is supplied from the I / O cell 29 to the CW bus 27. The recording / reproducing method for the DRAM 14 'is as described above. The data read from the DRAM 14 'is the CR bus 26 and the I / O cell 23.
It is output from the terminal 21 via.

Next, the luminance signal processing operation will be described with reference to the drawings. Since the processing operation is the same for the color difference signal, description thereof will be omitted. FIG. 2 is a timing chart for explaining the recording operation of the luminance signal. The luminance signal (Y) data is continuous data using 4 Fs (14.3 MHz) as a data clock. On the other hand, the shift register 4
2 and 43 shift clocks SFA and SFB are each 4
The pulse of Fs and the pulse of the 3/4 cycle thereof are alternately repeated every 8 cycles, and SFA and SFB are 4
The generation times of the Fs pulse and its 3/4 cycle pulse are completely opposite. As a result, the Y data is divided into 8-byte units when the shift clock is a pulse of 4 Fs, and is alternately held in the shift registers 42 and 43. Further, when the shift clock is a pulse of 3/4 cycle of 4 Fs, the held Y data is output, and the selector 44 outputs the shift register 43 when SL is "HIGH", and conversely SL outputs "LOW". In the case of "", the data RWD is supplied to the DRAM 14 by selecting the output of the shift register 42. The DRAM 14 sets a row address at the fall of RAS and a column address at the fall of CAS, and records Y data.

FIG. 3 is a timing chart for explaining the operation for reading the luminance signal data from the DRAM.
First, the row address and column address of the DRAM 14 are set at the fall of RAS and CAS, and the data RR is set.
Output D. This data RRD is stored in the shift register 4
Hold at 2,43. In this case, the data RRD is held when the respective shift clocks SFA and SFB are pulses of 3/4 cycle of 4Fs, and the data is output when the shift clock is 4Fs. This allows continuous data Y
Generating RD.

FIG. 4 is a memory map in DRAM. In this figure, the row address and the column address are originally binary numbers, but are shown as decimal numbers for the sake of explanation. The 8-byte data (2D0 to 2D7) of the first second line is recorded at the row address "1" and the column address "0 to 7". That is, the high-speed page mode in which the row address is fixed and only the column address is changed is performed. For the next 8-byte data (2D8 to 2D15), the row address is updated in units of 8 such that the row address is "9" and the column address is "0 to 7". After the end of the second line, the 8-byte data of the fourth line (4D0
.About.4D7) are recorded at the row address "3" and the column address "0 to 7".

When the first field ends, the second field starts, and the 8-byte data (1D0 to 1D) of the first line
7) The row address is “0” and the column address is “0”.
It is recorded at the address of 7 ". Thereafter, the same recording is performed to record data of 768 × 488 bytes for one screen.

On the other hand, when the recorded data is read out for the DCT processing, the column address is set to "0 to 7", the row address is set to "0 to 7", "8 to 15".
Output as one block in units. After outputting the 96th block, the column address is changed to "8 to 15", and the row address "0 to 7" corresponding to the 97th block is output.
Read the data recorded in. After that, similar processing is performed to read data for one screen (96 × 61 blocks).

As described above, in the recording and reading of data to and from the DRAM 14, the row address is periodically increased and the address is allocated so that the row address is repeated, so that refreshing is not necessary and all the data is read. It can be processed continuously.

As described above, the recording / reading speed with respect to the DRAM 14 is made faster than the transmission / reception speed of the input / output data to / from the memory controller 13. And the DRAM 14
In the recording and reading of data to and from, the row address is increased periodically and the address is allocated so that it is repeated, so that refreshing is not necessary and all data can be processed continuously. it can. As a result, it is possible to perform the same data processing as SRAM even though it is DRAM.

In the embodiment, the number of pixels is 768 × 488.
However, the number of pixels is not limited to this. The capacity of the DRAM may be other than 4 Mbits. The address may be supplied in any form as long as the row address increases in a specific cycle during the transfer of image data for one screen. Further, in the embodiment, the data byte unit in the high speed page mode is 8 bytes, but it may be changed according to the block unit in the DCT processing. Further, the shift register is used to hold 8 bytes of data, but any device such as a FIFO or a dual port RAM that can alternately hold data and output data may be used. The image signal system does not have to be interlace.

[0034]

According to the present invention, DRAM is used for data recording.
Does not require refreshing and all data can be processed continuously. This makes DRA
Although it is M, the same data processing as SRAM can be performed.

[Brief description of drawings]

FIG. 1 is a configuration diagram showing a configuration of the present invention.

FIG. 2 is a timing chart explaining a data recording operation.

FIG. 3 is a timing chart explaining a data reading operation.

FIG. 4 is an explanatory diagram illustrating an address arrangement in a DRAM.

FIG. 5 is a configuration diagram showing an overall configuration of the present invention.

FIG. 6 is a configuration diagram showing a conventional configuration.

FIG. 7 is an explanatory diagram illustrating image data of an interlace system.

FIG. 8 is an explanatory diagram illustrating a conventional image data recording method.

FIG. 9 is an explanatory diagram illustrating a data reading order for DCT processing.

[Explanation of symbols]

14, 14 '... DRAM, 31, 34, 41, 44 ... Selector, 32, 33, 42, 43 ... Shift register, 3
8, 48 ... FF, 50 ... Control section, 51 ... Address generating section.

Claims (2)

[Claims] 1. The image data is supplied in line order and is recorded in approximate memory image data, converted into a block composed of N × M (N, M: integer) pixels and read out, or image data for each block is recorded in the memory. , A memory control circuit for reading in line order, comprising at least two storage means for temporarily storing N words, and performing read / write access to the memory in a high-speed access mode in units of N words. 2. The memory control circuit according to claim 1, wherein in the read / write access, all valid row addresses are periodically repeated in a short period.