JPH05175832A - Malfunction avoiding circuit for johnson counter - Google Patents

Abstract

PURPOSE:To automatically restore a counter without generating count deviation with a simple circuit configuration at the time of the occurrence of malfunction. CONSTITUTION:This circuit consists of an N-ary counter part 1 which generates an initial pulse which is high for first N/2 bits and is low for latter N/2 bits and a shift register part 2 which consists of N/2 stages of flip flops and takes the initial pulse into flip flop of the first stage to shift it, and the circuit is characterized by using the update of the initial pulse at intervals of N bits to immediately restore the shift register part 2 from the malfunction.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a Johnson counter, and more particularly to a Johnson counter malfunction avoidance circuit for avoiding malfunction due to occurrence of an abnormal mode. In recent years, with the demand for higher speed and higher reliability of transmission devices, there is a demand for a circuit configuration that is high in quality in terms of hardware design and that is compatible with high speed operation. For this reason, the Johnson counter, which is often used in circuit design, is not exempt and is required to have high speed and high reliability.

[0002]

2. Description of the Related Art In a conventional Johnson counter, a Bubi trap circuit is adopted as a circuit for avoiding a malfunction that is not permanently recovered, that is, a so-called bad loop.
FIG. 7 shows the state transition in the 5-bit Johnson counter. As can be seen from the figure, when an abnormality occurs in the output state of the flip-flop, the configuration returns from the bad loop to the normal loop after a maximum of 6 clocks. Is. That is, the output state “10001” that does not exist in the regular loop
In the case of occurrence of, a normal output state "11000" is restored by the effect of the trap.

In order to operate in this way, as shown in FIG. 8, it is necessary to incorporate a Bubi trap circuit 60 which anticipates a bad loop state in advance. In this case, the gate processing returns to the normal loop. Therefore, the flip-flop cannot be re-stamped by securing the margin.
It should be noted that the example shown in FIG. 8 is a 5-bit Johnson counter, and 61 to 65 are flip-flops, respectively, in which Q outputs are connected to the data terminal D of the next stage to form a shift register. is there.

[0004]

Although the above example has a 5-bit configuration, as the counter value increases, those values increase, and as a result, it takes a long time to return from the bad loop to the normal loop. Become. Further, not only it is necessary to anticipate all the bad loop states, but also high-speed operation becomes impossible because the flip-flops cannot be re-stamped by securing a margin.

Therefore, when the Johnson counter is incorporated into the transmission device, it takes time before the transmission device can be normally operated, and the state of the bad loop varies depending on the counter value. There is a problem that high speed operation cannot be performed due to the margin.

The present invention has been made in consideration of the above circumstances. It is possible to automatically return from a bad loop to a normal loop immediately, and a unified avoidance circuit that does not depend on the counter value. Provided is a Johnson counter malfunction avoidance circuit applicable to operation.

[0007]

FIG. 1 is a diagram for explaining the principle of the first invention. In the figure, the first invention comprises an N-ary counter section 1 for generating an initial pulse consisting of N / 2 bit high and N / 2 bit low, and an N / 2 stage flip-flop. Johnson which is composed of a shift register unit 2 which is input to a flip-flop to shift and which is used to immediately restore the shift register unit 2 from a malfunction by utilizing the fact that the initial pulse is updated every N bits.・ A counter malfunction prevention circuit.

In the first invention, in the N-ary counter section 1,
A Johnson counter is configured by generating initial pulses of "High" N / 2 bits and "Low" N / 2 bits and shifting the pulses in the shift register unit 2.

Since this initial pulse is updated every N bits, even if a malfunction occurs in the shift register section 2, it can be immediately restored and no deviation from the counter value before the malfunction occurs. Further, the N-ary counter unit 1 has a substantially unified circuit configuration even when the number of bits is different. Further, since it does not have a circuit that causes a marginal problem like the Bubi trap, it can be applied to high-speed operation.

FIG. 2 is a block diagram showing the principle of the second invention. In the same figure, the second invention comprises a Johnson counter section 3 which is composed of N stages of flip-flops, NOTs the output of the final stage and feeds back to the input, and one bit each connected to each output of the flip-flop. The shift unit 4 that holds the previous output value, compares the output value of the previous one bit and the output value from each of the flip-flops with respect to all bits, and outputs a signal when at least one mismatch is detected. However, it is a malfunction prevention circuit for the Johnson counter, which is configured by all the flip-flops and the comparison unit 5 that resets the shift unit 4.

The second invention is a Johnson counter section 3
Is compared with the output of the shift unit 4 by the comparison unit 5, and if the results do not match, all the flip-flops are reset and the normal state is immediately restored. The comparison unit 5 of the second invention can realize a unified circuit configuration even when the counter values are different, and can be re-configured by the flip-flop by securing a margin, and thus can operate at high speed. Can also be applied.

[0012]

According to the present invention, even if each flip-flop of the Johnson counter malfunctions due to the influence of electrostatic noise, power source noise, etc., and even if a bad loop is entered, that state is immediately avoided. Therefore, regardless of the processing speed,
It is possible to automatically and immediately return to the normal state, and it is possible to satisfy the demands for high speed and high reliability.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below based on the embodiments shown in the drawings. The present invention is not limited to this. FIG. 3 shows a first embodiment of the present invention.
The circuit structure of a bit Johnson counter is shown.
In the figure, 10 is a decimal counter unit, and 11 is a shift register unit. 12 to 16 are flip-flops,
Each Q output is connected to the data terminal D of the next stage to form a shift register.

In such a configuration, the decimal counter section 10 generates an initial pulse of "High" 5 bits and "Low" 5 bits, and inputs the pulse to the first stage 12 of the shift register section 11, Since the shift is performed, even if one of the flip-flops malfunctions, the flip-flop can be immediately returned to the normal state, and the count deviation does not occur.

FIG. 4 is a time chart showing the operation of the circuit shown in FIG. Q1-Q5 outputs at point a in the figure are "000
00 ", that at point b is" 10000 ", and c
That of the dot is "11000". This state is a normal state, and the signal generated by repeating the output of Q1 of 5 bits "High" and 5 bits "Low" is sequentially shifted.

Next, if an abnormality occurs at the point d under the influence of electrostatic noise, power source noise, etc., 5 bits "High",
The 5-bit "Low" state collapses, and this state is affected up to the Q4 output and the Q5 output. When the next 5-bit "High" initial pulse is input to the first-stage flip-flop 12 The state is the same as the state in which the reset is applied with and the normal output is obtained thereafter. Specifically, the abnormality is resolved at point c in FIG. Moreover, there is no count deviation.

FIG. 5 shows a second embodiment of the present invention.
The circuit structure of a bit Johnson counter is shown.
In the second embodiment, the output of the Johnson counter and the output of the shift unit are compared, and if the results do not match,
All flip-flops are reset and immediately restored to the normal state.

In the figure, 20 is a five-stage flip-flop 20a.
.About.20e, which is a Johnson counter unit, which is a configuration in which the Bubi trap circuit is removed from the normal Johnson counter. Reference numeral 21 denotes a shift section, which is composed of five stages of flip-flops 21a to 21e. Two
2 is E-OR gates 22a to 22e and OR gate 22f
And a latch circuit 22g.
The output of 2g is a comparison unit connected to the reset terminals of all flip-flops.

In such a configuration, normally, only the Johnson counter section 20 normally operates, but if it enters a bad loop under the influence of electrostatic noise, power source noise, etc., it cannot be escaped. Therefore, the shift unit 21 holds the previous state for one bit, and the comparison unit 22 holds the previous state,
By comparing the output value from the counter unit 20 for all bits, it is immediately determined that a bad loop has been entered, and all flip-flops are cleared and initialized to avoid the bad loop. It becomes possible.

That is, if the two inputs of the E-OR gates 22a to 22e in the comparison unit 22 do not match, the signal High is output, and if the OR gate 22f has at least one of the inputs High, the signal High. High is output, and all flip-flops 20a to 20e and 21a to 2 are output.
1e will be cleared. FIG. 6 is a time chart showing the above processing.

As described above, in the second embodiment, the flip-flops are cleared based on the comparison result, so that the flip-flops can be re-allocated by securing the margin. Further, even if the value of the Johnson counter changes, it is not necessary to grasp the state of all bad loops because the circuit configuration has a unified E-OR and OR gate.

[0022]

According to the first aspect of the present invention, the N-ary counter section generates an initial pulse and shifts the pulse. Therefore, even if each flip-flop malfunctions, a count deviation does not occur and a normal operation is immediately performed. Can return to the state.
Further, since a circuit that causes a marginal problem such as a Bubi trap is not required, high speed operation is possible. Furthermore, even if the number of bits in the Johnson counter changes,
It is only necessary to change the configuration of the N-ary counter, so that it is not necessary to grasp the state of the bad loop as in the conventional Johnson counter.

According to the second invention, it is possible to automatically return from the bad loop to the normal loop immediately, and it is possible to realize a unified avoidance circuit regardless of the counter value. In addition, high speed operation becomes possible.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of a Johnson counter according to a first invention.

FIG. 2 is a principle configuration diagram of a Johnson counter according to a second invention.

FIG. 3 is a configuration diagram of a 5-bit Johnson counter according to the first embodiment of the present invention.

FIG. 4 is a time chart of the 5-bit Johnson counter according to the first embodiment.

FIG. 5 is a configuration diagram of a 5-bit Johnson counter according to a second embodiment.

FIG. 6 is a time chart of a 5-bit Johnson counter according to the second embodiment.

FIG. 7 is a state transition diagram of a conventional 5-bit Johnson counter.

FIG. 8 is a configuration diagram of a Johnson counter of a conventional example.

[Explanation of symbols]

 1 N-ary counter unit 2 Shift register unit 3 Johnson counter unit 4 Shift unit 5 Comparison unit

Claims (2)

[Claims] 1. An N-ary counter section 1 for generating an initial pulse composed of N / 2 bit high and N / 2 bit low, and N / 2.
A first stage of the initial pulse
And a shift register unit 2 for inputting and shifting to the flip-flops of the stages, and utilizing the fact that the initial pulse is updated every N bits, the shift register unit 2 is immediately restored from the malfunction. A Johnson counter malfunction prevention circuit. 2. A flip-flop having N stages,
Johnson noting the output of the final stage and returning to the input
A counter unit 3, a shift unit 4 that is connected to each output of the flip-flops and holds an output value of one bit before, and an output value of one bit before and an output value from each of the flip-flops. Avoidance of malfunction of Johnson counter characterized in that it is composed of a comparison unit 5 which compares bits and outputs a signal when at least one mismatch is detected and resets all flip-flops and shift unit 4. circuit.