JPH05175806A - Variable delay circuit - Google Patents

Abstract

PURPOSE:To operate a variable delay circuit without degrading its S/N by eliminating the noise generated synchronously with a clock signal. CONSTITUTION:The variable delay circuit having a delay circuit 1, a capacitor memory circuit 2, and a write/read control circuit 4 is provided with a sample and hold circuit 10 which receives the output of the capacitor memory circuit 2 and is operated by a control signal phih from the write/read control circuit 4 and a sample and hold circuit 10' which receives the output of the sampling and holding circuit 10 and is operated by a control signal phih' from the write/ read control circuit 4. These two sample and hold circuits 10 and 10' are used to obtain a noiseless ultrasonic signal. That is, an ultrasonic tomographic image is obtained without degrading S/N of the variable delay circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an ultrasonic diagnostic apparatus, and more particularly to a variable delay circuit of the ultrasonic diagnostic apparatus suitable for preventing deterioration of S / N ratio.

[0002]

2. Description of the Related Art A conventional variable delay circuit is disclosed in Japanese Patent Laid-Open No. 3-19.
6709, a delay circuit 1, a capacitor memory circuit 2 subordinately connected to the delay circuit 1, a control unit 3 for sending a control voltage to the delay circuit 1 to control the delay time thereof, The control circuit 4 controls writing and reading of the capacitor memory circuit 2. Then, with the sampling frequency fs kept constant, the capacitor memory circuit 2 delays the sampling period 1 / fs by a maximum of N / fs to obtain the sampling period 1 / f.
A short delay of s or less is executed by controlling the delay time of the delay circuit 1. That is, the signal input from the input terminal IN passes through the delay circuit 1 whose delay time is controlled by the control unit 3 which generates the control voltage based on the delay data DS, is delayed by the capacitor memory circuit 2, and then is output from the output terminal. The delayed signal is output to OUT.

[0003]

In the above-mentioned conventional device, noise is prevented from being mixed in with the clock signal of the capacitor memory circuit being set to a constant period to prevent noise from mixing therein. Therefore, the S / N ratio of the variable delay circuit is deteriorated.

Therefore, an object of the present invention is to eliminate the noise generated in synchronization with the clock signal and to operate the variable delay circuit without degrading the S / N ratio.

[0005]

In order to achieve the above object, an inductor and a variable capacitance diode whose electrostatic capacitance changes according to the magnitude of the reverse voltage are used, and the delay time is changed by the change of the reverse voltage of this variable capacitance diode. A variable resistance circuit is used that forms a variable delay line that changes, and that feeds back with a constant resistance to an amplifier whose gain can be controlled by an electric signal as a signal source resistance and a termination resistance of this variable delay line to make the resistance value of the circuit variable. In a variable delay circuit having a delay circuit configured as follows, a capacitor memory circuit cascade-connected to the delay circuit, and a write / read control circuit that controls writing and reading of the capacitor memory circuit, the output of the capacitor memory circuit is received. A sample hole that operates with a control signal that is synchronized with the signal generated at a fixed cycle of the write / read control circuit. And a circuit, in which a sample and hold circuit operated by a control signal Disconnect periodic signals generated at a constant period of the writing and reading control circuit receiving the output of said sample and hold circuit.

[0006]

The sample and hold circuit, which receives the signal from the capacitor memory circuit, receives the signal synchronized with the signal generated from the write / read control circuit at a constant cycle and generates the ultrasonic signal. Further, the sample-hold circuit for inputting the ultrasonic signal receives the signal out of synchronization with the signal generated at a constant cycle and outputs the ultrasonic signal without noise.

[0007]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 is a block diagram showing an embodiment of a variable delay circuit according to the present invention, FIG. 2 is a circuit diagram of the variable delay circuit of the present invention, and FIG. 3 is a timing chart showing the operation of the present invention. Reference numeral 1 is a delay circuit for controlling a delay time, 2 is a capacitor memory circuit for delaying an input signal by the delay time, 3 is a control unit for reading delay data DS and sending a control voltage to the delay circuit 1, 4 is delay data DL and a clock. A write / read control circuit that inputs the signal CLK and outputs hold signals φh and φh ′ for controlling the write signal φw and the read signal φr and the sample and hold circuits 10 and 10 ′ for writing and reading the capacitor memory circuit 2. , 9 are adders for adding the outputs from the capacitor memory circuit 2, 10 and 10 ′ are sample and hold circuits for sampling and holding the ultrasonic signals US and US ′ according to the control signals h and φh ′, and 11 are sample and hold circuits 10 ′. It is an AD converter for digitally converting the ultrasonic signal US ′ from

Next, the operation of the variable delay circuit of the present invention will be described. The input signal from the input terminal IN is input to the delay circuit 1, and the delay circuit 1 inputs the control voltage of the control unit 3 which has received the delay data DS to determine the delay time. Then, the signal whose delay time is determined is sent to the capacitor memory circuit 2
, And write and read operations are performed. The write and read operations are controlled by the write signal φw and read signal φr of the write / read control circuit 4.

Then, the read signal is input to the sample hold circuit 10 to output the ultrasonic signal US. The ultrasonic signal US is input to the adder 9, and the added signal is input to the sample hold circuit 10 'to output a noise-free ultrasonic signal US'. This ultrasonic signal US '
When the digital conversion is performed by the D converter 11, an ultrasonic tomographic image is displayed by performing digital signal processing such as conversion of an ultrasonic signal into an absolute value, maximum value of amplitude in an arbitrary period, or average value processing in a detection circuit. To do.

Next, the operations of the capacitor memory circuit 2 and the sample and hold circuits 10 and 10 'will be described in detail with reference to FIGS. The output from the delay circuit 1 is passed through the buffer amplifier A3 in the input section of the capacitor memory circuit 2,
The write switches X1 to Xn enable capacitors C1 to C1.
It is written in Cn and delayed by the read switches Y1 to Yn. These write switches X1 to Xn
When the write signal φw of the write / read control circuit 4 and the clock signal CLK are input via the shift register SHR-W, the input signal from the delay circuit 1 is received and input to the capacitors C1 to Cn, that is, write is performed. To do. Similarly to the read switches Y1 to Yn, when the read signal φr and the clock signal CLK from the write / read control circuit 4 are input through the shift register SHR-R, the read switches output the signals written in the capacitors C1 to Cn, that is, read the signals. do.

Here, when the arbitrary write switch Xi and read switch Yi are selected, the capacitor Ci receives the write signal φw, the read signal φr, and the clock signal CLK from the shift registers SHR-W and SHR-R.
Write and read. The write timing at this time is shown by Wi in FIG. 3, and the read timing is R
Denote by i.

The signals written in the capacitors C1 to Cn are input to the sample hold circuit 10 via the reset switch X0 and the operational amplifier A2 when the read switches Y1 to Yn are turned on. The sample hold circuit 10 includes a switch Z0, a capacitor Cz, and an amplifier A.
4 and the hold control signal φh of the write / read control circuit 4 synchronized with the rising edge of the clock signal CLK.
In response to this, an ultrasonic signal US is generated, and this ultrasonic signal U
Input S to the adder 9.

Then, the ultrasonic signal US is added by the adder 9 and input to the sample hold circuit 10 '. The sample and hold circuit 10 ′ is for avoiding inductive noise generated when the clock signal CLK of the ultrasonic signal US rises and falls, and receives the hold control signal φh ′ from the write / read control signal 4. Ultrasonic signal U
Output S '. This hold control signal outputs a signal at a position apart from the rising and falling timings of the clock signal CLK to sample and hold signals other than the rising and falling edges of the ultrasonic signal US superimposed on the induction noise. This allows the ultrasonic signal US without noise
´ can be obtained.

[0014]

According to the present invention, by using the two sample hold circuits, it is possible to prevent the noise generated in synchronization with the signal of the constant cycle of the conventional capacitor memory circuit from being taken in. That is, an ultrasonic tomographic image can be obtained without deteriorating the S / N ratio of the variable delay circuit.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a variable delay circuit according to the present invention.

FIG. 2 is a circuit diagram of a variable delay circuit of the present invention.

FIG. 3 is a timing chart showing the operation of the present invention.

[Explanation of symbols]

 1 Delay Circuit 2 Capacitor Memory Circuit 3 Controller 4 Write / Read Control Circuit 9 Adder 10 Sample Hold Circuit 10 'Sample Hold Circuit 11 AD Converter CLK Clock Signal φw Write Signal φr Read Signal φh Hold Control Signal φh' Hold Control Signal

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Kanda 1-28 Higashi Koigakubo, Kokubunji City, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (1)

[Claims] Claim: What is claimed is: 1. An inductor and a variable capacitance diode whose capacitance changes according to the magnitude of the reverse voltage are used to form a variable delay line whose delay time changes according to the change of the reverse voltage of the variable capacitance diode. A delay circuit that uses a variable resistance circuit that varies the resistance value of the circuit by feeding back with a constant resistance to an amplifier whose gain can be controlled by an electric signal as a signal source resistance and a termination resistance of the line, and a subordinate connection to this delay circuit. A variable delay circuit having a stored capacitor memory circuit and a write / read control circuit for controlling writing and reading of the capacitor memory circuit, and a signal generated at a constant cycle of the write / read control circuit in response to an output of the capacitor memory circuit. The sample and hold circuit that operates with the control signal synchronized with Only the variable delay circuit, characterized in that a sample and hold circuit operated by a control signal Disconnect periodic signals generated at a constant period of the writing and reading control circuit.