JPH05175596A - Semiconductor laser device - Google Patents
Semiconductor laser deviceInfo
- Publication number
- JPH05175596A JPH05175596A JP34310391A JP34310391A JPH05175596A JP H05175596 A JPH05175596 A JP H05175596A JP 34310391 A JP34310391 A JP 34310391A JP 34310391 A JP34310391 A JP 34310391A JP H05175596 A JPH05175596 A JP H05175596A
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- JP
- Japan
- Prior art keywords
- layer
- buried
- inp
- semiconductor laser
- laser device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は,半導体レーザ装置,特
に1μm帯光通信に用いるのに好適なリッジ型埋め込み
構造を有する半導体レーザ装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor laser device, and more particularly to a semiconductor laser device having a ridge type buried structure suitable for use in 1 .mu.m band optical communication.
【0002】[0002]
【従来の技術】図4は,InGaAsP系リッジ型埋め
込み構造半導体レーザ装置の一般的な構造の主要部断面
を示す図である。2. Description of the Related Art FIG. 4 is a view showing a cross section of a main part of a general structure of an InGaAsP ridge type buried structure semiconductor laser device.
【0003】図中,21はn+ −InP基板,22はn
- −In0.6 Ga0.4 As0.9 P0. 1 活性層(λ=1.
55μm),23はp−InPクラッド層,24はp−
InP埋め込み層,25はn−InP埋め込み層,26
はp−InPクラッド層,27はp+ −In0.71Ga
0.29As0.66P0.34コンタクト層(λ=1.3μm)で
ある。In the figure, 21 is an n + -InP substrate and 22 is n.
- -In 0.6 Ga 0.4 As 0.9 P 0. 1 active layer (lambda = 1.
55 μm), 23 is a p-InP clad layer, and 24 is a p-
InP buried layer, 25 is n-InP buried layer, 26
Is a p-InP clad layer, 27 is p + -In 0.71 Ga
0.29 As 0.66 P 0.34 contact layer (λ = 1.3 μm).
【0004】活性層22は,基板21と同じ格子定数を
持ち,かつ発振波長1.55μmに相当する禁制帯幅を
持つIn0.6 Ga0.4 As0.9 P0.1 で構成されてい
る。活性層22直上のクラッド層23は,p−InPで
構成されている。活性層22およびクラッド層23は,
p−InP埋め込み層24およびn−InP埋め込み層
25によって埋め込まれている。The active layer 22 is composed of In 0.6 Ga 0.4 As 0.9 P 0.1 having the same lattice constant as the substrate 21 and a forbidden band width corresponding to an oscillation wavelength of 1.55 μm. The cladding layer 23 immediately above the active layer 22 is made of p-InP. The active layer 22 and the cladding layer 23 are
It is embedded by the p-InP burying layer 24 and the n-InP burying layer 25.
【0005】本従来例の他に,埋め込み層をpn接合型
のInPで構成したものの他に,埋め込み層にクラッド
層23よりも禁制帯幅が大きいZnSeTeを用いる構
造も提案されている。In addition to this conventional example, in addition to a structure in which the buried layer is made of pn junction type InP, a structure in which ZnSeTe having a larger forbidden band width than the clad layer 23 is used as the buried layer is also proposed.
【0006】[0006]
【発明が解決しようとする課題】半導体レーザ装置にお
いては,その発振閾値電流が小さいことが要求される。
発振閾値電流を小さくするためには,電流を活性層22
に集中する必要がある。しかし,従来の半導体レーザ装
置では,クラッド層23から埋め込み層24を通って漏
れ電流が流れてしまい,発振閾値電流を低下させること
が困難である,という問題があった。A semiconductor laser device is required to have a small oscillation threshold current.
In order to reduce the oscillation threshold current, the current is set to the active layer 22.
Need to focus on. However, the conventional semiconductor laser device has a problem that it is difficult to reduce the oscillation threshold current because a leakage current flows from the cladding layer 23 through the buried layer 24.
【0007】また,ZnSeTeを用いて埋め込む構造
の半導体レーザ装置においては,埋め込み層が基板(II
I −V族半導体)と全く異なる元素で構成されるII−V
I 族半導体であり,さらに混晶であるため,結晶性の優
れたエピタキシャル層を得ることが困難である,という
問題があった。In a semiconductor laser device having a structure in which ZnSeTe is used for burying, the burying layer is a substrate (II
II-V composed of elements completely different from I-V semiconductors)
Since it is a Group I semiconductor and is a mixed crystal, it is difficult to obtain an epitaxial layer with excellent crystallinity.
【0008】本発明は,上記の問題点を解決して,電流
がクラッド層から埋め込み層を通って流れるのを防止し
て,電流を活性層に集中できるようにし,発振閾値電流
を低下させることのできる半導体レーザ装置,特にリッ
ジ型埋め込み構造を有する半導体レーザ装置を提供する
ことを目的とする。The present invention solves the above-mentioned problems and prevents current from flowing from the cladding layer through the buried layer so that current can be concentrated in the active layer and lowers the oscillation threshold current. It is an object of the present invention to provide a semiconductor laser device capable of achieving the above, particularly a semiconductor laser device having a ridge-type buried structure.
【0009】[0009]
【課題を解決するための手段】上記の目的を達成するた
めに,本発明に係る半導体レーザ装置は,次のように構
成する。In order to achieve the above object, a semiconductor laser device according to the present invention is constructed as follows.
【0010】(1)活性層がリッジ型でかつ埋め込み構
造を有する半導体レーザ装置であって,埋め込み層が,
導電型が異なる基板と同じ材料で構成されており,活性
層直上のクラッド層が,埋め込み層を構成する材料の禁
制帯幅よりも小さい禁制帯幅を持つ材料で構成されてい
る。(1) A semiconductor laser device in which the active layer is a ridge type and has a buried structure, wherein the buried layer is
It is made of the same material as the substrate of different conductivity type, and the clad layer directly above the active layer is made of a material having a forbidden band width smaller than that of the material forming the buried layer.
【0011】より具体的には, (2)基板がn型InPで構成されており,埋め込み層
が,pn接合型のInPで構成されており,活性層直上
のクラッド層が,活性層を構成するInGaAsPの禁
制帯幅よりも大きな禁制帯幅となる組成のInGaAs
Pで構成されている。More specifically, (2) the substrate is made of n-type InP, the buried layer is made of pn junction type InP, and the clad layer immediately above the active layer constitutes the active layer. Of InGaAsP having a band gap larger than that of InGaAsP
It is composed of P.
【0012】または, (3)基板がn型InPで構成されており,埋め込み層
が,高抵抗のInPで構成されており,活性層直上のク
ラッド層が,活性層を構成するInGaAsPの禁制帯
幅よりも大きな禁制帯幅となる組成のInGaAsPで
構成されている。Or (3) the substrate is made of n-type InP, the buried layer is made of high-resistance InP, and the clad layer directly above the active layer is a band gap of InGaAsP which constitutes the active layer. It is composed of InGaAsP having a composition having a forbidden band width larger than the width.
【0013】[0013]
【作用】本発明に係るリッジ型埋め込み構造を有する半
導体レーザ装置は,埋め込み層を,導電型が異なる基板
と同じ材料で構成し,活性層直上のクラッド層を,埋め
込み層を構成する材料の禁制帯幅よりも小さい禁制帯幅
を持つ材料で構成する。In the semiconductor laser device having the ridge-type buried structure according to the present invention, the buried layer is made of the same material as that of the substrates having different conductivity types, and the clad layer immediately above the active layer is prohibited from the material of the buried layer. It is made of a material having a forbidden band width smaller than the band width.
【0014】この結果,埋め込み層は,基板と同じ材料
であるため,結晶性の優れたものを容易に得ることがで
きる。そして,図2に示すように,クラッド層と埋め込
み層との界面に,多数キャリアである正孔に対するポテ
ンシャルの障壁ができるから,クラッド層から埋め込み
層への正孔の流入を抑制することができるので,漏れ電
流を低減することが可能になる。その結果,発振閾値電
流を低下させることができる。As a result, since the buried layer is made of the same material as the substrate, it is possible to easily obtain a material having excellent crystallinity. Then, as shown in FIG. 2, a potential barrier for holes, which are majority carriers, is formed at the interface between the clad layer and the buried layer, so that the flow of holes from the clad layer to the buried layer can be suppressed. Therefore, it becomes possible to reduce the leakage current. As a result, the oscillation threshold current can be reduced.
【0015】[0015]
【実施例】(実施例1)図1は,実施例1を示す図であ
る。EXAMPLES Example 1 FIG. 1 is a diagram showing Example 1.
【0016】図中,11はn+ −InP基板,12はn
- −In0.6 Ga0.4 As0.9 P0. 1 活性層(λ=1.
55μm),13はp−In0.92Ga0.08As0.18P
0.82クラッド層(λ=1.0μm),14はp−InP
埋め込み層,15はn−InP埋め込み層,16はp−
InPクラッド層,17はp+ −In0.71Ga0.29As
0.66P0.34コンタクト層(λ=1.3μm)である。In the figure, 11 is n+-InP substrate, 12 is n
--In0.6Ga0.4As0.9P0. 1Active layer (λ = 1.
55 μm), 13 is p-In0.92Ga0.08As0.18P
0.82Clad layer (λ = 1.0 μm), 14 is p-InP
Buried layer, 15 is n-InP buried layer, 16 is p-
InP clad layer, 17 is p+-In0.71Ga0.29As
0.66P0.34The contact layer (λ = 1.3 μm).
【0017】以下,図1に示す,本発明に係るリッジ型
埋め込み構造を有する半導体レーザ装置の製造方法を説
明する。 n+ −InP基板11上に,MOVPE( Metal Or
ganic Vapor Phase Epitaxy ) 法を用いて,厚さ0.1
μmのn- −In0.6 Ga0.4 As0.9 P0.1 活性層
(λ=1.55μm)12および厚さ0.5μmのp−
In0.92Ga0.08As0.18P0.82クラッド層(λ=1.
0μm)13を成長する。A method of manufacturing the semiconductor laser device having the ridge type buried structure according to the present invention shown in FIG. 1 will be described below. On the n + -InP substrate 11, MOVPE (Metal Or
ganic Vapor Phase Epitaxy) method
μm n − −In 0.6 Ga 0.4 As 0.9 P 0.1 active layer (λ = 1.55 μm) 12 and 0.5 μm thick p−
In 0.92 Ga 0.08 As 0.18 P 0.82 cladding layer (λ = 1.
0 μm) 13 is grown.
【0018】 成長層表面に,例えば幅3μmのSi
O2 膜を付け,メサエッチングした後,p−InP埋め
込み層14およびn−InP埋め込み層15を,MOV
PE法により成長する。On the surface of the growth layer, for example, Si having a width of 3 μm
After attaching an O 2 film and performing mesa etching, the p-InP burying layer 14 and the n-InP burying layer 15 are subjected to MOV.
It grows by the PE method.
【0019】 SiO2 膜をエッチング除去した後,
MOVPE法により,p−InPクラッド層16および
p+ −In0.71Ga0.29As0.66P0.34コンタクト層
(λ=1.3μm)17を成長する。After removing the SiO 2 film by etching,
The p-InP clad layer 16 and the p + -In 0.71 Ga 0.29 As 0.66 P 0.34 contact layer (λ = 1.3 μm) 17 are grown by the MOVPE method.
【0020】クラッド層13の禁制帯幅は1.24eV
であり,埋め込み層14の禁制帯幅は1.35eVであ
る。したがって,クラッド層13と埋め込み層14との
界面に,正孔に対して0.7eV程度のポテンシャル障
壁が形成される。これにより,クラッド層13から埋め
込み層14への正孔の流入が抑制される。その結果,電
流を活性層12に集中させることができるので,発振閾
値電流を低下させることができる。The forbidden band width of the clad layer 13 is 1.24 eV.
Therefore, the forbidden band width of the buried layer 14 is 1.35 eV. Therefore, a potential barrier of about 0.7 eV for holes is formed at the interface between the clad layer 13 and the buried layer 14. This suppresses the inflow of holes from the clad layer 13 into the buried layer 14. As a result, the current can be concentrated in the active layer 12, so that the oscillation threshold current can be reduced.
【0021】(実施例2)図3は,実施例2を示す図で
ある。図中,11はn+ −InP基板,12はn- −I
n0.6 Ga0.4 As0.9 P0. 1 活性層(λ=1.55μ
m),13はp−In0.92Ga0.08As0.18P0.82クラ
ッド層(λ=1.0μm),16はp−InPクラッド
層,17はp+ −In 0.71Ga0.29As0.66P0.34コン
タクト層(λ=1.3μm),18は高抵抗InP埋め
込み層である。(Second Embodiment) FIG. 3 is a diagram showing a second embodiment.
is there. In the figure, 11 is n+-InP substrate, 12 is n--I
n0.6Ga0.4As0.9P0. 1Active layer (λ = 1.55μ
m) and 13 are p-In0.92Ga0.08As0.18P0.82Kura
Dead layer (λ = 1.0 μm), 16 is p-InP clad
Layer, 17 is p+-In 0.71Ga0.29As0.66P0.34Con
Tact layer (λ = 1.3 μm), 18 is filled with high resistance InP
It is a mixed layer.
【0022】実施例1においては,p−InP埋め込み
層14およびn−InP埋め込み層15によってpn接
合型の埋め込みを行ったが,本実施例では,高抵抗In
P埋め込み層18によって埋め込みを行っている。In the first embodiment, the pn junction type burying is performed by the p-InP burying layer 14 and the n-InP burying layer 15, but in this embodiment, the high resistance In
The P burying layer 18 is used for burying.
【0023】本実施例の構造においても,実施例1と同
様に,クラッド層13から埋め込み層18への正孔の流
入が抑制される。その結果,電流を活性層12に集中さ
せることができるので,発振閾値電流を低下させること
ができる。Also in the structure of this embodiment, like the first embodiment, the inflow of holes from the cladding layer 13 to the buried layer 18 is suppressed. As a result, the current can be concentrated in the active layer 12, so that the oscillation threshold current can be reduced.
【0024】[0024]
【発明の効果】本発明によれば,リッジ型埋め込み構造
を有する半導体レーザ装置において,電流がクラッド層
から埋め込み層を通って流れるのを防止することが可能
になるので,電流を活性層に集中することができるよう
になり,発振閾値電流を低下させることができる。According to the present invention, in a semiconductor laser device having a ridge type buried structure, it is possible to prevent a current from flowing from the cladding layer through the buried layer, so that the current is concentrated in the active layer. Therefore, the oscillation threshold current can be reduced.
【図1】実施例1を示す図である。FIG. 1 is a diagram showing a first embodiment.
【図2】クラッド層と埋め込み層との界面のバンド図で
ある。FIG. 2 is a band diagram of an interface between a clad layer and a buried layer.
【図3】実施例2を示す図である。FIG. 3 is a diagram showing a second embodiment.
【図4】従来例を示す図である。FIG. 4 is a diagram showing a conventional example.
11 n+ −InP基板 12 n- −In0.6 Ga0.4 As0.9 P0.1 活性層
(λ=1.55μm) 13 p−In0.92Ga0.08As0.18P0.82クラッド層
(λ=1.0μm) 14 p−InP埋め込み層 15 n−InP埋め込み層 16 p−InPクラッド層 17 p+ −In0.71Ga0.29As0.66P0.34コンタク
ト層(λ=1.3μm)11 n + -InP substrate 12 n --In 0.6 Ga 0.4 As 0.9 P 0.1 active layer (λ = 1.55 μm) 13 p-In 0.92 Ga 0.08 As 0.18 P 0.82 clad layer (λ = 1.0 μm) 14 p- InP buried layer 15 n-InP buried layer 16 p-InP clad layer 17 p + -In 0.71 Ga 0.29 As 0.66 P 0.34 Contact layer (λ = 1.3 μm)
Claims (3)
有する半導体レーザ装置であって, 埋め込み層が,導電型が異なる基板と同じ材料で構成さ
れており, 活性層直上のクラッド層が,埋め込み層を構成する材料
の禁制帯幅よりも小さい禁制帯幅を持つ材料で構成され
ていることを特徴とする半導体レーザ装置。1. A semiconductor laser device in which an active layer is a ridge type and has a buried structure, wherein the buried layer is made of the same material as a substrate having a different conductivity type, and the clad layer directly above the active layer is buried. A semiconductor laser device comprising a material having a forbidden band width smaller than a forbidden band width of a material forming the layer.
AsPの禁制帯幅よりも大きな禁制帯幅となる組成のI
nGaAsPで構成されていることを特徴とする半導体
レーザ装置。2. The substrate according to claim 1, wherein the substrate is made of n-type InP, the buried layer is made of pn junction type InP, and the clad layer immediately above the active layer is made of InGa.
A composition with a forbidden band larger than the forbidden band of AsP
A semiconductor laser device comprising nGaAsP.
AsPの禁制帯幅よりも大きな禁制帯幅となる組成のI
nGaAsPで構成されていることを特徴とする半導体
レーザ装置。3. The InGa according to claim 1, wherein the substrate is made of n-type InP, the buried layer is made of high-resistance InP, and the clad layer directly above the active layer constitutes the active layer.
A composition with a forbidden band larger than the forbidden band of AsP
A semiconductor laser device comprising nGaAsP.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34310391A JPH05175596A (en) | 1991-12-25 | 1991-12-25 | Semiconductor laser device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34310391A JPH05175596A (en) | 1991-12-25 | 1991-12-25 | Semiconductor laser device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05175596A true JPH05175596A (en) | 1993-07-13 |
Family
ID=18358968
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP34310391A Withdrawn JPH05175596A (en) | 1991-12-25 | 1991-12-25 | Semiconductor laser device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05175596A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009059916A (en) * | 2007-08-31 | 2009-03-19 | Sumitomo Electric Ind Ltd | Optical semiconductor device |
-
1991
- 1991-12-25 JP JP34310391A patent/JPH05175596A/en not_active Withdrawn
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009059916A (en) * | 2007-08-31 | 2009-03-19 | Sumitomo Electric Ind Ltd | Optical semiconductor device |
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Legal Events
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