JPH05175467A - Asic device - Google Patents

Abstract

PURPOSE:To provide an ASIC device whose clock skew is relaxed. CONSTITUTION:An ASIC device comprises a clock signal generation section 11, a register section 12 which latches serial data input from the outside in synchronization with a clock signal from the clock signal generation section 11, a random logic section 13 which processes data output from the register section 12 and a control section which controls the random clock logic 13. Since the register section 12 consists of a flip flop array which is laid out and concentrated to one portion of a chip, it is possible to allow a clock circuit to be concentrated into one corner of the chip. This construction makes it possible to relax the deviation of delay of the clock signal.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION The present invention relates to ASIC (application specific IC) devices.

[0002]

2. Description of the Related Art ASIC composed of a gate array or the like
Has reached the scale of tens of thousands to hundreds of thousands of gates due to the recent increase in the degree of integration of LSIs, and system-on-chip implementation is also possible.

[0003]

However, along with this, the malfunction of the circuit due to the deviation of the delay (signal delay) and the timing shift (skew) that cannot be detected even if the timing verification is performed becomes a problem. .. In particular, it is difficult to control the delay of the clock signal supplied to each part of the chip.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide an ASIC device with reduced clock skew.

[0005]

It is an object of the present invention to include a register unit for storing multi-bit data and a random logic unit for processing data output from the register unit, the register unit being a semiconductor. It is achieved by an ASIC, which is a flip-flop array centralized in a part of the chip.

[0006]

The register unit for storing multi-bit data is composed of a flip-flop array, and each flip-flop fetches data in synchronization with a clock signal.
Each flip-flop controls the flow of data according to the write signal and the read signal. Since these flip-flops are arranged so as to be concentrated on a part of the semiconductor chip, it is possible to concentrate the clock circuit on one corner of the chip, thereby alleviating the bias bias of the clock signal delay.

[0007]

1 is a block diagram of an ASIC device according to the present invention. In the figure, 11 is a clock signal generating unit, 12 is a register unit that takes in serial data input from the outside in synchronization with the clock signal from the clock signal generating unit 11, and 13 is processing the data output from the register unit 12. The random logic unit 14 and the control unit 14 control the random logic unit. As shown in Figure 1,
Since the circuits using the clock signal are concentrated on one corner of the chip, the bias deviation of the clock signal delay is alleviated.

The register unit 12 is composed of an array of leaf cells that can be sliced, that is, can accommodate multi-bit data of variable bit length.

FIG. 2 shows a circuit diagram of the leaf cell. As shown in the figure, the leaf cell is a data holding circuit that writes and reads data by adding a write (WR) signal and a read (RD) signal to a flip-flop, and a feedback signal from the output side. Is used to hold the current data. FIG. 3 is a symbolic representation of the leaf cell of FIG.

FIG. 4 shows a circuit diagram of a register in the case where leaf cells are combined for 4 bits so as to correspond to 4-bit data. Since each leaf cell does not share a data bus like normal memory and the leaf cell is a flip-flop type, it is possible for each cell to independently perform the operation of the data flow, and the parallel operation of the data is performed. Processing becomes possible. FIG. 5 is a symbolic representation of the register of FIG.

FIG. 6 shows another example of the ASIC device of the present invention. An example of this is a 16-bit barrel shifter consisting of 16 leaf cells, a multiplexer containing random logic circuits, and a data bus for carrying data circulating between them.

FIG. 7 shows still another example of the ASIC device of the present invention. This example includes a leaf cell array composed of cascade-connected leaf cells, a random logic circuit (stages 1 to 3) provided between the leaf cells, and a register file connected to the outputs and inputs of the leaf cell arrays. And form a pipelined data path. In this circuit, reading and writing can be controlled for each stage.

[0013]

According to the ASIC device of the present invention,
Since the register unit that stores multi-bit data is composed of a flip-flop array that is concentrated on a part of the semiconductor chip, it is possible to concentrate the clock circuit on one corner of the chip, and the bias of the delay of the clock signal Is alleviated. Therefore, according to the present invention, a critical pipeline-oriented high-speed circuit of clock operation can be realized as an ASIC device.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of an ASIC device of the present invention.

FIG. 2 is a circuit diagram of a leaf cell forming a register unit of the ASIC device of FIG.

FIG. 3 is a symbolic view of the circuit of FIG.

FIG. 4 is a circuit diagram of a register configured by combining leaf cells for 4 bits.

5 is a diagram symbolically representing the register in FIG. 4. FIG.

FIG. 6 is a circuit diagram of a 16-bit barrel shifter which is another embodiment of the present invention.

FIG. 7 is a circuit diagram of a pipelined data path according to still another embodiment of the present invention.

[Explanation of symbols]

 11 clock generation unit 12 register unit 13 random logic unit 14 control unit

Claims (1)

[Claims] 1. A register unit for storing multi-bit data, and a random logic unit for processing data output from the register unit, wherein the register unit is arranged centrally on a part of a semiconductor chip. And an ASIC device comprising a flip-flop array.