JPH05175410A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To obtain a semiconductor integrated circuit wherein the parasitic inductance generated in the interconnection from each bonding pad to each pin is equalized with respect to each bonding pad, and the dispersion of simultaneous switching noises is reduced. CONSTITUTION:A semiconductor chip 22 is turned by about 45 degrees with respect to a semiconductor-package main body 20 in this constitution. Thus, a long bonding wire 28, which is connected to a bonding pad 24 in the vicinity of the apex angle of the semiconductor chip 22, is connected to a short lead frame 26. Meanwhile, the relatively long lead frame 26 is connected to the short bonding wire 28, which is connected to the bonding pad 24 in the vicinity of the central part of each piece of the semiconductor chip 22. Therefore, the parasitic inductance generated in the interconnections, which are connected to each bonding pad 24, is equalized.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit. In particular, the present invention relates to a semiconductor integrated circuit having an improved positional relationship between a semiconductor package and a semiconductor chip mounted thereon.

[0002]

2. Description of the Related Art In recent years, the development of semiconductor integrated circuits has been remarkable.
Semiconductor integrated circuits are used in many industrial devices. In particular, the improvement of the operation speed has been remarkable and has been a driving force for the improvement of the performance of information equipment such as computers.

As described above, the problem of noise has become more serious as the operating speed of semiconductor integrated circuits increases.
Noise that has a particularly large influence is noise called simultaneous switching noise. This simultaneous switching noise is noise generated in the power supply line when a plurality of output buffers through which a large current flows simultaneously switch.

FIG. 2 shows an example of a circuit diagram of a typical output buffer. This example is an example of an output buffer of a CMOS type semiconductor integrated circuit, which is an inverter type output buffer in which PMOS type and NMOS type transistors are combined. FIG. 2 schematically shows the parasitic inductance L and the load capacitance CL in addition to the two transistors. The parasitic inductance L is an inductance caused by the lead frame of the semiconductor package and the bonding wire. The load capacitance CL is caused not only by the lead frame of the semiconductor package but also by the floating capacitance between the wirings in the semiconductor chip.

Now, in the output buffer A having such a configuration,
The voltage V at the point (shown in FIG. 2), that is, at the source point of the NMOS transistor, is expressed by the following equation.

V = L (di / dt) (1) where i is the current flowing through the parasitic inductance L. FIG. 3 shows an example of signal waveforms of the circuit shown in FIG.
FIG. 3 shows the input signal, the output signal and the signal waveform at the point A of the output buffer shown in FIG. For example, if there are N output buffers having the configuration shown in FIG. 2 in an integrated circuit, and if they change their outputs at the same time, the current flowing through the parasitic inductance L also becomes N times, so that the equation (1) is used. The noise level V is also N times higher. As described above, the simultaneous switching noise generated by simultaneously changing the outputs of the plurality of output buffers is caused by, for example, providing a large number of power supply pins near the output pins and reducing the current flowing per power supply pin. It was being reduced.

Due to the background as described above, the LS is usually used.
In the design of I, a design rule such as "add one power supply pin to n output pins" is provided to take measures against simultaneous switching noise.

However, the parasitic inductance of the power supply pin (most of which is generated in the lead frame and the bonding wire of the semiconductor package)
Varies greatly depending on the position of the pin in the semiconductor package. Figure 4 shows the QFP (Quad Flat P)
FIG. 2 is an exploded plan view showing a state of wiring between the bonding wire 10 and the lead frame 12 in the semiconductor package of package type (acge). This QFP type semiconductor package has a square shape, and therefore only the wiring of a quarter of the semiconductor package is shown in FIG. As shown in FIG. 4, in the normal QFP type semiconductor package, the length of both the lead frame 12 and the bonding wire 10 is short at the pin near the center of one side of the main body package body 14. The parasitic inductance due to is also relatively small. On the other hand, in the pin located near the apex angle of the semiconductor package body 14, both the lead frame 12 and the bonding wire 10 are relatively longer than the pins near the center of one side of the semiconductor package body 14. Therefore, the parasitic inductance due to the pin located near the apex becomes relatively large.

[0009]

In the conventional semiconductor integrated circuit, the size of the parasitic inductance associated therewith greatly differs depending on the position of the pin of the semiconductor package. Therefore, the output of the above-mentioned simultaneous switching noise also greatly differs depending on the position of each power supply pin. Therefore, as described above, uniformly applying a simple design rule such as "adding one power supply pin to n output pins" to the entire semiconductor integrated circuit depends on the position where the power supply pin is provided. , The noise level of the output pin in the vicinity was greatly changed.

However, if a design rule is set according to the position of each power supply pin and the effect of reducing simultaneous switching noise is to be made uniform, the degree of freedom in LSI design is greatly restricted, and the design is extremely difficult. There was a problem that it would be difficult. The present invention has been made in view of such a problem, and an object thereof is to obtain a semiconductor integrated circuit in which variations in the value of the parasitic inductance due to each pin are small.

[0011]

According to the present invention, in order to solve the above problems, a bonding wire connected to a bonding pad near the apex angle of a semiconductor chip is a bonding pad near the center of each side of the semiconductor chip. Is longer than the bonding wire connected to. on the other hand,
The lead frame further connected to the bonding wire connected to the bonding pad near the apex angle of the semiconductor chip is shorter than the lead frame further connected to the bonding wire connected to the bonding pad near the center of each side. There is.

Therefore, the inductance of the bonding wire and the lead frame connected to each bonding pad is made uniform for each bonding pad.

Further, in particular, in a semiconductor integrated circuit having a rectangular semiconductor package in which external terminals are aligned and arranged on the periphery thereof, and an inner end portion of a lead frame is aligned and arranged in a rectangular shape parallel to a semiconductor chip, As one means for achieving the above configuration, it is effective to adopt a configuration in which the semiconductor chip is rotated by about 45 degrees with respect to the semiconductor package. In this way, a semiconductor chip is almost
In the semiconductor integrated circuit rotated by 5 degrees, the inner end of the lead frame is a rectangle parallel to the semiconductor chip, and therefore the bonding wire near the apex is relatively longer than the bonding wire in the center of each side. There is. Therefore, if the above-mentioned configuration is adopted, the bonding pads near the apex of the semiconductor chip will have external terminals closer to them as compared with the bonding pads at the center of each side. Therefore, a long bonding wire and a short lead frame are connected to the bonding pad near the top of the semiconductor chip, and a short bonding wire and a long lead frame are connected to the bonding pad at the center of each side.

[0014]

The bonding pad near the apex angle of the semiconductor chip according to the present invention is connected with a bonding wire relatively long and a short lead frame as compared with the bonding pad near the central portion of each piece of the semiconductor chip.

Therefore, the inductance due to the bonding wire and the lead frame connected to the bonding pads of the semiconductor chip in the present invention can be made uniform for each bonding pad of the semiconductor chip.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan exploded sectional view of a semiconductor integrated circuit according to an embodiment of the present invention. Similar to FIG. 4, FIG. 1 shows only a quarter of the semiconductor integrated circuit due to the symmetry. As shown in FIG. 1, in this embodiment, the semiconductor chip 22 is mounted on the semiconductor package body 20 with a tilt of approximately 45 degrees. As a result, the apex portion of the semiconductor chip 22 has a structure close to the central portion of each side of the semiconductor package body 20. Each bonding pad 24 on the semiconductor chip 22 is wire bonded to one end of a lead frame 26 by a bonding wire 28. One end of the lead frame 26 connected to the bonding pad 24 on the semiconductor chip 22 by this wire bonding is arranged in parallel with the row of the bonding pads 24 of the semiconductor chip 22 as in the conventional case. Further, the other end of the lead frame 26 is exposed to the outside of the semiconductor package body 20 and forms an external terminal.

As described above, one end of the lead frame 26 to be wire-bonded has the semiconductor chip 2 as in the conventional case.
The bonding wires 28 are arranged in parallel with the rows of the bonding pads 24 on the upper surface of the semiconductor chip 22. Therefore, the bonding wire 28 is relatively long with respect to the bonding pads 24 near the apex of the semiconductor chip 22, and the bonding wires 28 near the center of each side. The bonding wire 28 is shorter for the bonding pad 24. On the other hand, as shown in FIG. 1, a relatively short lead frame 26 is connected to a relatively long bonding wire 28 connected to the bonding pad 24 located near the apex of the semiconductor chip 22. There is. Therefore, according to the present embodiment, the length of the bonding wire 28 is relatively longer than that of the bonding pad 24 near the apex of the semiconductor chip 22 as in the conventional case, and the length of the bonding pad 24 near the center of each side is smaller. Although relatively short, the short lead frame 26 is connected to the long bonding wire 28, and the relatively long lead frame 26 is connected to the short bonding wire 28. As a result, for each bonding pad 24 on the semiconductor chip 22, the inductance caused by the bonding wire 28 and the lead frame 26 connected to the bonding pad 24 can be made uniform. A feature of this embodiment is that the semiconductor chip 22 is tilted at 45 degrees with respect to the semiconductor package body 20 so that each vertex of the semiconductor chip 22 is close to the center of each side of the semiconductor package body 20. That is what I did. With such a configuration, each apex portion of the semiconductor chip 22 is closer to the external terminal group arranged in the peripheral portion of the semiconductor package body 20, and the central portion of each side of the semiconductor chip 22 is the peripheral portion of the semiconductor package body 20 ( The external terminal group arranged in) is relatively distant from the external terminal group.

As is apparent from comparison with the configuration of the conventional semiconductor integrated circuit shown in FIG. 4, the semiconductor integrated circuit according to the present embodiment shown in FIG. Are the same. That is, one end of the lead frame 26 to be wire-bonded,
That is, the inner end groups are aligned and arranged so as to form a rectangle surrounding the semiconductor chip 22, and each side of the rectangle is parallel to each side of the semiconductor chip 22. Therefore,
The relative position between the bonding pad 24 on the semiconductor chip 22 and one end (inner end) of the lead frame does not change at all, only by rotating the wire bonding position by 45 degrees. Therefore, wire bonding that requires precise control can be performed accurately as in the conventional case. That is, according to the present embodiment, the inductance caused by the bonding wire 28 and the lead frame 26 connected to each bonding pad 24 can be made uniform by simply changing the length of each lead frame 25 constituting the external terminal. The effect is that it can be done very easily.

[0020]

As described above, according to the present invention, a relatively short lead frame is connected to a relatively long bonding wire and a relatively short lead frame is connected to a relatively short bonding wire. Since the longer lead frames are connected to each other, it is possible to easily make the inductances caused by the bonding wires and the lead frames uniform. Therefore, since the parasitic inductance existing in each output buffer is made uniform, the level 1 of the simultaneous switching noise is also made uniform in each output buffer.

In addition, "power pin 1 for n output pins
By applying a simple design rule such as “adding individual pieces”, simultaneous switching noise can be effectively reduced. In this way, simultaneous switching noise can be reduced by a simple design rule.
This has an effect that a smooth design work can be carried out without restricting the degree of freedom of design. as a result. LS
The noise characteristic of the main body of I is also improved.

[Brief description of drawings]

FIG. 1 is an exploded plan sectional view showing wiring from a semiconductor chip of a semiconductor integrated circuit which is an embodiment of the present invention.

FIG. 2 is an explanatory circuit diagram illustrating generation of simultaneous switching noise.

FIG. 3 is a waveform explanatory view showing waveforms of respective parts of the circuit shown in FIG.

FIG. 4 is a plan exploded sectional view showing wiring from a semiconductor chip of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 20 Semiconductor Package Main Body 22 Semiconductor Chip 24 Bonding Pad 26 Lead Frame 28 Bonding Wire

Claims (2)

[Claims] 1. A semiconductor integrated circuit comprising: a rectangular semiconductor chip; and a lead frame having an outer end portion forming an external terminal and an inner end portion connected to a bonding pad of the semiconductor chip by wire bonding. The bonding wire connected to the bonding pad near the apex angle of the semiconductor chip is relatively longer than the bonding wire connected to the bonding pad near the center of each side, The semiconductor integrated circuit is characterized in that the lead frame connected to the bonding wire to be connected is relatively shorter than the lead frame connected to the bonding wire connected to the bonding pad near the center of each side. 2. The semiconductor integrated circuit according to claim 1, wherein the lead frame group having the inner end row arranged in a rectangular shape surrounding the rectangular semiconductor chip, and the outer terminal row surrounding the lead frame group. A rectangular semiconductor package arranged in line, wherein the rectangular inner end row is parallel to the rectangular semiconductor chip, and the rectangular inner end row and the rectangular semiconductor chip parallel to each other are: The semiconductor integrated circuit according to claim 1, wherein the rectangular semiconductor package rotates about 45 degrees, and the apex angle portion of the rectangular semiconductor chip is close to the center of each side of the rectangular semiconductor package.