JPH05175330A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05175330A JPH05175330A JP34268391A JP34268391A JPH05175330A JP H05175330 A JPH05175330 A JP H05175330A JP 34268391 A JP34268391 A JP 34268391A JP 34268391 A JP34268391 A JP 34268391A JP H05175330 A JPH05175330 A JP H05175330A
- Authority
- JP
- Japan
- Prior art keywords
- locos
- active element
- substrate
- crystal defect
- edge
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】この発明は半導体装置の製造方法
に関し、特に、LOCOS構造を素子分離として用いる
半導体装置において生じるLOCOS端のSi基板上に
発生する欠陥起因のリーク電流を低減することに適する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly, it is suitable for reducing a leak current caused by a defect generated on a Si substrate at a LOCOS end which occurs in a semiconductor device using a LOCOS structure as element isolation. It is a thing.
【0002】[0002]
【従来の技術】Si基板上に能動素子を形成する場合、
素子間を分離する方法としてLOCOS構造が広く用い
られる。2. Description of the Related Art When forming an active element on a Si substrate,
A LOCOS structure is widely used as a method for separating elements.
【0003】図3は、LOCOS形成及び能動素子拡散
層形成後のSi基板断面を示す。FIG. 3 shows a cross section of a Si substrate after formation of LOCOS and formation of an active element diffusion layer.
【0004】図において、1はSi基板,2はLOCO
S形成の際に選択的にSi基板が酸化された酸化膜,3
は能動素子形成領域,5は能動素子領域に形成された不
純物拡散層である。In the figure, 1 is a Si substrate and 2 is a LOCO.
An oxide film in which the Si substrate is selectively oxidized during S formation, 3
Is an active element forming region, and 5 is an impurity diffusion layer formed in the active element region.
【0005】[0005]
【発明が解決しようとする課題】ところで、上記のLO
COS構造形成過程で、選択的に基板を、熱処理で酸化
する際に、酸化膜2と、Si基板1間にはたらく応力に
よりSi基板中の結晶が乱され、特にLOCOS端にお
いて、結晶欠陥が生じる。By the way, the above-mentioned LO
When the substrate is selectively oxidized by heat treatment in the COS structure formation process, the stress acting between the oxide film 2 and the Si substrate 1 disturbs the crystals in the Si substrate, and crystal defects particularly occur at the LOCOS edge. .
【0006】図3中の4がLOCOS端に発生した結晶
欠陥である。Reference numeral 4 in FIG. 3 is a crystal defect generated at the LOCOS edge.
【0007】その後、能動素子形成領域3に能動素子を
形成しその能動素子を動作させる場合結晶欠陥部分の4
を通して、拡散層5よりSi基板1へのリーク電流が発
生するという問題点があった。After that, when an active element is formed in the active element formation region 3 and the active element is operated, 4 of crystal defect portions are formed.
There is a problem that a leak current from the diffusion layer 5 to the Si substrate 1 is generated.
【0008】[0008]
【課題を解決するための手段】この発明は、上記の課題
を解決するために、LOCOS形成後能動素子形成前
に、Si基板をエッチングすることで、LOCOS端の
結晶欠陥部分を取り除き、その後能動素子領域を形成す
ることを特徴とするものである。In order to solve the above-mentioned problems, the present invention removes the crystal defect portion at the LOCOS end by etching the Si substrate after the formation of the LOCOS and before the formation of the active element, and thereafter, the active portion is formed. It is characterized in that an element region is formed.
【0009】[0009]
【作用】上記の手順において、LOCOS端の結晶欠陥
を、能動素子形成前にエッチングにより取り除くこと
で、能動領域の拡散層中のリーク電流経路を低減出来
き、能動素子動作時のリーク電流を低減できる。In the above procedure, the crystal defects at the LOCOS end are removed by etching before forming the active element, so that the leak current path in the diffusion layer in the active region can be reduced and the leak current during the operation of the active element can be reduced. it can.
【0010】[0010]
【実施例】以下この考案の実施例について図面を参照し
て説明する。Embodiments of the present invention will be described below with reference to the drawings.
【0011】図1〜図2はこの発明の一実施例の製造フ
ローに従った素子断面図である。1 to 2 are sectional views of elements according to the manufacturing flow of an embodiment of the present invention.
【0012】図1はLOCOS形成後の断面図であり、
図においてSi基板1中のLOCOS酸化膜2の端部の
能動素子形成領域3に結晶欠陥4が発生している。FIG. 1 is a sectional view after formation of LOCOS.
In the figure, crystal defects 4 occur in the active element formation region 3 at the end of the LOCOS oxide film 2 in the Si substrate 1.
【0013】LOCOS形成後にSi基板を結晶欠陥の
及ぶ深さまでエッチングしその後能動素子の拡散層5を
形成する。その断面図が図2である。After the LOCOS is formed, the Si substrate is etched to a depth reaching the crystal defects, and then the diffusion layer 5 of the active element is formed. The sectional view is FIG.
【0014】上記製造フローによれば、能動素子の拡散
層内にLOCOS形成時に発生するLOCOS端の結晶
欠陥が取り込まれることがなく、能動素子動作時のリー
ク電流を低減出来る。According to the above manufacturing flow, the crystal defect at the LOCOS end generated during the formation of LOCOS is not taken into the diffusion layer of the active element, and the leak current during the operation of the active element can be reduced.
【0015】エッチングはフッ酸希釈液を用いることが
できる。また、反応性イオンエッチング等、ドライエッ
チングで行うこともできる。For the etching, a dilute solution of hydrofluoric acid can be used. It is also possible to carry out dry etching such as reactive ion etching.
【0016】[0016]
【発明の効果】この発明は以上のように、LOCOS形
成後能動素子形成前にSi基板をエッチングすること
で、LOCOS端に発生する結晶欠陥を取り除き、能動
素子動作時のリーク電流を低減出来る。As described above, according to the present invention, by etching the Si substrate after the formation of the LOCOS and before the formation of the active element, the crystal defects generated at the LOCOS edge can be removed and the leak current during the operation of the active element can be reduced.
【図1】 本発明による製造方法を説明するためのLO
COS形成後のSi基板断面図FIG. 1 is an LO for explaining a manufacturing method according to the present invention.
Cross-sectional view of Si substrate after COS formation
【図2】 本発明の欠陥部除去後のSi基板断面図FIG. 2 is a cross-sectional view of a Si substrate after the defect portion of the present invention is removed.
【図3】 従来のLOCOS形成及び能動素子拡散層形
成後のSi基板断面図FIG. 3 is a sectional view of a Si substrate after conventional LOCOS formation and active element diffusion layer formation.
1 Si基板 2 LOCOS酸化膜 3 能動素子形成領域 4 結晶欠陥 5 拡散層 1 Si substrate 2 LOCOS oxide film 3 active element formation region 4 crystal defect 5 diffusion layer
Claims (2)
で、素子間分離にLOCOS構造を採用する半導体装置
の製造方法において、 LOCOS端に発生するSi基板上の欠陥を、能動素子
形成前に除去することを特徴とする半導体装置の製造方
法。1. In a method of manufacturing a semiconductor device that employs a LOCOS structure for element isolation in the process of forming an active element on a Si substrate, defects on the Si substrate generated at the LOCOS edge are formed by the active element formation. A method for manufacturing a semiconductor device, characterized in that it is removed before.
したフッ酸あるいは反応性イオンエッチングによってS
i基板をエッチングすることでLOCOS端の欠陥を除
去することを特徴とする半導体装置の製造方法。2. The method according to claim 1, wherein S is formed by diluting hydrofluoric acid or reactive ion etching before forming an active element.
A method of manufacturing a semiconductor device, characterized in that a defect at a LOCOS edge is removed by etching an i substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34268391A JPH05175330A (en) | 1991-12-25 | 1991-12-25 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP34268391A JPH05175330A (en) | 1991-12-25 | 1991-12-25 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05175330A true JPH05175330A (en) | 1993-07-13 |
Family
ID=18355690
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP34268391A Pending JPH05175330A (en) | 1991-12-25 | 1991-12-25 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05175330A (en) |
-
1991
- 1991-12-25 JP JP34268391A patent/JPH05175330A/en active Pending
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