JPS58132947A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS58132947A JPS58132947A JP1601682A JP1601682A JPS58132947A JP S58132947 A JPS58132947 A JP S58132947A JP 1601682 A JP1601682 A JP 1601682A JP 1601682 A JP1601682 A JP 1601682A JP S58132947 A JPS58132947 A JP S58132947A
- Authority
- JP
- Japan
- Prior art keywords
- region
- oxide film
- film
- silicon nitride
- nitride film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Abstract
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関するもので、特に素
子間分離された半導体島領域内に結晶欠陥の発生の少な
い半導体装置の製造方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device in which crystal defects are less likely to occur in semiconductor island regions separated between elements.
素子間分離に酸化膜を用いる方法はpn接合分離に比べ
て半導体素子の面積が小さくでき、高密度化に適し、ま
た高進化、低消費電力化にも非常に有利である。酸化膜
分離構造を形成する方法としては選択酸化法が広く用い
られているが、選択酸化に伴なって半導体島領域に発生
する結晶欠陥が問題となっていた。The method of using an oxide film for element isolation allows the area of the semiconductor element to be smaller than pn junction isolation, is suitable for higher density, and is very advantageous for higher evolution and lower power consumption. A selective oxidation method is widely used as a method for forming an oxide film isolation structure, but crystal defects generated in semiconductor island regions due to selective oxidation have been a problem.
第1図(a)〜(C)は従来より行なわれている酸化膜
分離の工程断面図を示すものである。まず同図(−)の
ように、シリコン基板1の上に下敷シリコン酸化膜2、
及びシリコン窒化膜3を形成した後、レジスト4を半導
体島領域を形成する箇所を残して部分的に開口する。次
に同図Φ)のように、レジスト4をマスクとしてシリコ
ン窒化膜3をプラズマエツチングにより除去し、嘔らに
下敷シリコン酸化膜2をフッ酸系のエツチング液でエツ
チング除去する。続いてシリコン基板1を異方性スパッ
タエツチングにより所望の深さだけエツチングする。FIGS. 1A to 1C show cross-sectional views of conventional oxide film separation processes. First, as shown in the figure (-), an underlying silicon oxide film 2 is placed on a silicon substrate 1.
After forming the silicon nitride film 3, the resist 4 is partially opened leaving a portion where a semiconductor island region will be formed. Next, as shown in FIG. Φ), the silicon nitride film 3 is removed by plasma etching using the resist 4 as a mask, and the underlying silicon oxide film 2 is etched away using a hydrofluoric acid-based etching solution. Subsequently, the silicon substrate 1 is etched to a desired depth by anisotropic sputter etching.
次に同図(C)のように、レジスト4を除去した後シリ
コン窒化膜3をマスクとして選択酸化を行ない、分離酸
化膜6を形成する。然る後、分離酸化膜形成に際し成長
したシリコン窒化膜3上のシリコン酸化膜を除去し、さ
らにシリコン窒化膜3を除去することにより酸化膜分離
構造を完成する。Next, as shown in FIG. 4C, after removing the resist 4, selective oxidation is performed using the silicon nitride film 3 as a mask to form an isolation oxide film 6. Thereafter, the silicon oxide film on the silicon nitride film 3 grown during the formation of the isolation oxide film is removed, and the silicon nitride film 3 is further removed to complete the oxide film isolation structure.
以上説明した従来例において、第1図(C)に見られる
ように、素子形成される半導体島領域6に選択酸化時の
ストレスにより結晶欠陥7が発生し、半導体島領域6に
形成される素子の電気的特性を著しく劣化させる原因と
なる。この結晶欠陥発生の要因となる選択酸化時のスト
レスを無くすことは非常に難しく、結晶欠陥発生は避は
難い。In the conventional example described above, as shown in FIG. 1(C), crystal defects 7 are generated in the semiconductor island region 6 where an element is formed due to stress during selective oxidation, and the element formed in the semiconductor island region 6 is This causes a significant deterioration of the electrical characteristics of the It is very difficult to eliminate stress during selective oxidation, which is a factor in the generation of crystal defects, and the generation of crystal defects is unavoidable.
本発明は上記欠点にかんがみなされたもので、結晶欠陥
の少ない良好な酸化膜分離構造を有する半導体装置の製
造方法を提供せんとするものであ形成し、この領域に結
晶欠陥を集中吸収させ、半導体島領域には欠陥を発生さ
せないように酸化膜分離構造を有する半導体の製造方法
を提供するもので、以下本発明の構成を実施例を用いて
詳細に説明する。The present invention has been made in view of the above-mentioned drawbacks, and it is an object of the present invention to provide a method for manufacturing a semiconductor device having a good oxide film isolation structure with few crystal defects. The present invention provides a method for manufacturing a semiconductor having an oxide film isolation structure so as to prevent defects from occurring in a semiconductor island region, and the structure of the present invention will be explained in detail below using examples.
第2図(a)〜(C)は本発明の一実施例による酸化膜
分離構造を有する半導体装置の製造方法を示す工程断面
図である。同図(a)は分離酸化膜を選択酸化法により
形成する前の断面図を示すものである。FIGS. 2A to 2C are process cross-sectional views showing a method of manufacturing a semiconductor device having an oxide film isolation structure according to an embodiment of the present invention. FIG. 5A shows a cross-sectional view before the isolation oxide film is formed by selective oxidation.
シリコン基板11の半導体島領域14となる表面には、
下敷シリコン酸化膜12及びシリコン窒化膜13が形成
されており、素子間分離酸化膜を形成する箇所に所望の
深さの開口部16・17が形成されている。半導体島と
ならない領域16の表面にはシリコン窒化膜13のみが
形成されている。On the surface of the silicon substrate 11 that will become the semiconductor island region 14,
An underlying silicon oxide film 12 and a silicon nitride film 13 are formed, and openings 16 and 17 of desired depth are formed at locations where element isolation oxide films are to be formed. Only silicon nitride film 13 is formed on the surface of region 16 that does not become a semiconductor island.
同図(b)はシリコン窒化膜13をマスクにして選択酸
化を行ない開口部16及び17にそれぞれ素子間分離酸
化膜18・19を形成した構造を示す。FIG. 2B shows a structure in which selective oxidation is performed using the silicon nitride film 13 as a mask to form element isolation oxide films 18 and 19 in the openings 16 and 17, respectively.
ここで、シリコン窒化膜13をマスクとして選択酸化を
行なう際、シリコン窒化膜によるシリコン基板中へ加わ
るストレスを緩和するために、シリコン窒化膜13の下
に下敷シリコン酸化膜12を挿入する手段が用いられる
が、半導体島とならないシリコン基板表面16上には下
敷シリコン酸化膜が挿入されていない。この為、シリコ
ン基板領域16には非常に多くの結晶欠陥20が発生す
る。Here, when performing selective oxidation using the silicon nitride film 13 as a mask, a method is used to insert the underlying silicon oxide film 12 under the silicon nitride film 13 in order to alleviate the stress applied to the silicon substrate by the silicon nitride film. However, no underlying silicon oxide film is inserted on the silicon substrate surface 16 that does not become a semiconductor island. Therefore, a large number of crystal defects 20 occur in the silicon substrate region 16.
一方、半導体島領域14のシリコン基板表面1上には下
敷シリコン酸化膜が挿入されているのでシリコン基板へ
加わるストレスが緩和され、かつ島領域14に発生すべ
き欠陥も隣接の欠陥多数発生領域16に吸収されて島領
域14は結晶欠陥の少ない非常に良好な基板となること
ができる。On the other hand, since the underlying silicon oxide film is inserted on the silicon substrate surface 1 of the semiconductor island region 14, the stress applied to the silicon substrate is alleviated, and defects that should occur in the island region 14 are removed from the adjacent defect-prone region 16. The island region 14 can become a very good substrate with few crystal defects.
第2図は本発明に係る第2の実施例を示すもので、シリ
コン基板の開口部側面にもシリコン窒化膜を形成して選
択酸化を行ない分離酸化膜を形成するものである。同図
(a)のように、半導体島領域34及び半導体島となら
ない領域32の側面にシリコン窒化膜33を形成する。FIG. 2 shows a second embodiment of the present invention, in which a silicon nitride film is also formed on the side surface of the opening in the silicon substrate and selective oxidation is performed to form an isolation oxide film. As shown in FIG. 3A, a silicon nitride film 33 is formed on the side surfaces of the semiconductor island region 34 and the region 32 that will not become a semiconductor island.
半導体島領域34の上面反び側面はシリコン酸化膜36
を介してシリコン窒化膜33が形成されている。一方、
半導体島とならない領域32の側面にはシリコン酸化膜
が挿入されていない。同図[有])はシリコン窒化膜3
6をマスクとして選択酸化法により分離酸化膜36形成
後の構造を示す。A silicon oxide film 36 is formed on the upper and curved side surfaces of the semiconductor island region 34.
A silicon nitride film 33 is formed therebetween. on the other hand,
No silicon oxide film is inserted into the side surfaces of the region 32 that will not become a semiconductor island. The same figure [with]) shows silicon nitride film 3.
The structure after the isolation oxide film 36 is formed by the selective oxidation method using 6 as a mask is shown.
以上の如く、本実施例によれば側面にシリコン酸化膜3
5が挿入されていない半導体島とならない領域32には
、シリコン窒化膜36によるストレスを受けて非常に多
数の結晶欠陥37が発生し、半導体島領域34で発生す
べき欠陥を吸収する効果をもつ。また島領域34の側面
にはシリコン窒化膜33が形成されているので、分離酸
化膜36は横方向の酸化の入り込みがほとんどなく、寸
法精度の良い微細な酸化膜分離構造を形成できる。As described above, according to this embodiment, the silicon oxide film 3 is formed on the side surface.
In the region 32 which does not become a semiconductor island where 5 is not inserted, a large number of crystal defects 37 are generated due to the stress caused by the silicon nitride film 36, which has the effect of absorbing defects that should occur in the semiconductor island region 34. . Furthermore, since the silicon nitride film 33 is formed on the side surface of the island region 34, there is almost no lateral oxidation in the isolation oxide film 36, and a fine oxide film isolation structure with good dimensional accuracy can be formed.
以上、本発明によれば大集積半導体装置の歩奉りを向上
出来るので半導体製造工程上非常に効果のあるものであ
る。As described above, according to the present invention, it is possible to improve the performance of large-scale integrated semiconductor devices, and therefore it is very effective in the semiconductor manufacturing process.
第1図(a)〜(C)は従来の酸化膜分離構造を有する
半導体装置の製造方法を示す工程断面図、第2図(a)
〜(b)は本発明の一実施例に係る酸化膜分離構造を有
する半導体装置の製造方法を示す工程断面図、第3図(
a)〜中)は本発明の他の実施例を示す工程断面図を示
す。
14.34・・・・・島領域、12 、35・・・・・
シリコン酸化膜、13.33・・・・・・シリコン窒化
酸、15゜32・・・・・・欠陥吸収領域。
代理人の氏名 弁理士 中 尾 敏 男 ほか1名II
図
4
((1)
tbノ
(C) 7
第 2 因
ta)
” (b)1(a) to 1(C) are process cross-sectional views showing a method of manufacturing a semiconductor device having a conventional oxide film isolation structure, and FIG. 2(a)
-(b) are process cross-sectional views showing a method for manufacturing a semiconductor device having an oxide film isolation structure according to an embodiment of the present invention, and FIG.
a) to middle) show process cross-sectional views showing other embodiments of the present invention. 14.34...Island area, 12, 35...
Silicon oxide film, 13.33...Silicon nitride oxide, 15°32...Defect absorption region. Name of agent: Patent attorney Toshio Nakao and one other person II
Figure 4 ((1) tbノ(C) 7 2nd cause ta) ” (b)
Claims (1)
を介して第1シリコン窒化膜を形成し、素子間分離領域
内の所定部分には第2のシリコン窒化膜を形成する工程
と、前記第1.第2のシリコン窒化膜をマスクとして選
択酸化を行ない前記型の製造方法。forming a first silicon nitride film via a silicon oxide film on the semiconductor island region where the device is to be formed, and forming a second silicon nitride film in a predetermined portion within the device isolation region; 1. A method of manufacturing the above-mentioned type by performing selective oxidation using the second silicon nitride film as a mask.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1601682A JPS58132947A (en) | 1982-02-03 | 1982-02-03 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1601682A JPS58132947A (en) | 1982-02-03 | 1982-02-03 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS58132947A true JPS58132947A (en) | 1983-08-08 |
Family
ID=11904771
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1601682A Pending JPS58132947A (en) | 1982-02-03 | 1982-02-03 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS58132947A (en) |
-
1982
- 1982-02-03 JP JP1601682A patent/JPS58132947A/en active Pending
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