JPH05173984A - Method for synchronous control between plural processing units - Google Patents

Abstract

PURPOSE:To perform fine control over a parallel processing system which has plural processing units. CONSTITUTION:In a step S7, the processing units are synchronized each time a loop ends. In a step S10, the value of an interval timer is read in as a timer value. In a step 8, the interval timer is preset. In a step 11, the timer value is transferred to the other processing unit. In a step 12, the minimum timer value is selected. In a step 13, the value obtained by subtracting the selected timer value from a comparison value is used as the 1st comparison value of a next loop. In an interruption processing routine, the comparison value is put back to the preset value (2 milliseconds) previously set in a step 9.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention has a plurality of processing units that perform the same predetermined processing in synchronization with a clock, and only when the processing results of the plurality of processing units are the same, the matched processing is performed. The present invention relates to a parallel processing system for generating a result as a control signal to the outside, and in particular, a synchronous control between a plurality of processing units in a parallel processing system in which the plurality of processing units operate in synchronization with clocks supplied from different clock oscillators. Regarding the method.

[0002]

2. Description of the Related Art A multiprocessor system is a system having a plurality of processing units. A parallel processing system is one of the multiprocessor systems. A parallel processing system is a system in which a plurality of processing units are caused to perform the same predetermined processing and only when the processing results of the plurality of processing units match, the matched processing results are generated as a control signal to the outside. That is. A parallel processing system is also called a parallel redundant system. Such a parallel processing system is generally required for reliability and is used in a control system involving human life. For example, in the field of car electronics, a parallel processing system is an anti-lock braking system (hereinafter referred to as AB
S) Used in control circuits. That is, the brake control is a very dangerous control system, and therefore reliable control is required. As is well known, the ABS control circuit is a control circuit that prevents the wheels from locking when a sudden brake is applied to obtain an optimum braking action. The ABS control circuit will be described below as an example.

First, an outline of the ABS control circuit will be described. The car has a body and wheels. When the vehicle is running, the vehicle body and wheels are moving at non-zero vehicle body speed and wheel speed, respectively. When running normally,
Of course, the vehicle speed and the wheel speed are the same. In other words, the slip ratio is substantially zero. Here, the slip ratio is a value indicating how much the wheel speed has decreased with respect to the vehicle speed, and is represented by (vehicle speed-wheel speed) / vehicle speed.

However, when the brake pedal is suddenly depressed,
The wheel goes to the lock and the wheel speed goes to zero, but the body speed does not suddenly become zero due to inertia. In this state, the vehicle cannot suddenly stop due to inertia due to slippage, resulting in a very long braking distance. Therefore, when the slip ratio becomes equal to or higher than a predetermined ratio, by performing control so as to loosen the brake, the slip of the vehicle can be eliminated and the vehicle can be stopped in a short time with a short braking distance.

The ABS control circuit performs this control. Therefore, the ABS control circuit needs to constantly monitor the vehicle speed and the wheel speed. To this end, the ABS control circuit incorporates a detection signal from a wheel sensor mounted on the vehicle tire. The ABS control circuit has two processing units. In each processing unit, the vehicle speed and the wheel speed are calculated from the incorporated detection signal, and the slip is calculated from the calculated vehicle speed and the wheel speed. Seeking a rate. These calculations are repeated in a cycle of a predetermined time. That is, in the two processing units, exactly the same programs are stored in their ROMs, and their CPUs repeatedly perform processing in accordance with this program at predetermined time intervals. That is, it takes a predetermined time to execute the program, and when the process reaches the end point of the program, the process returns to the beginning of the program again, and the process according to the program is restarted. This predetermined time is called a loop time. This loop time is, for example, 6 milliseconds. When the slip ratio obtained during each loop time is equal to or higher than a predetermined ratio, a control signal is sent to the solenoid valve of the hydraulic brake system to drive the solenoid valve to loosen the hydraulic pressure of the brake. As mentioned above, this control signal is generated only when the processing results of the two processing units match.

This control signal may be generated in units of loop time. However, when the loop time is used as a unit, the loop time is as long as 6 milliseconds, so the control of the hydraulic pressure of the brake becomes rough. In order to perform this control finely (finely), a control signal is generated in units of time obtained by dividing the loop time by a predetermined number. As a specific example, 3 is selected as the predetermined number, and therefore the unit time is 2 milliseconds. That is, chopping is performed every 2 milliseconds.

In order to perform such precise control, conventionally, each processing unit always compares a preset comparison value (corresponding to 2 milliseconds) with the value of the interval timer. When these values match, an interrupt is generated and the interval timer is preset. This causes an interrupt to occur every 2 milliseconds. This interrupt count is counted in the interrupt processing routine. After returning from the interrupt processing routine to the main processing routine, the number of times of this interrupt is checked, and when it reaches 3, the loop time is created by returning to the beginning of the main processing routine.

In the conventional ABS control circuit, two processing units are supplied with a clock from one clock generator. That is, the two processing units operate in synchronization with the same clock. This is because it is necessary to operate the two processing units with exactly the same operation. In other words, the two processing units have exactly the same clock. In this case, since the two processing units are always synchronized, no special processing for synchronizing is necessary.

However, since the two processing units are driven in synchronization with the clock supplied from one clock generator, if the clock generator fails, the two processing units stop their operations at the same time. , That is, it goes down. In this case, it is meaningless to have a parallel redundant configuration, and high reliability cannot be maintained.
Further, if two processing units go down at the same time, fail-safe cannot be performed as described later.

In order to solve this problem, the present inventor has
I thought it would be better to operate the two processing units with clocks from different clock oscillators. However, it is virtually impossible to obtain a clock oscillator capable of oscillating a clock having exactly the same clock frequency. Further, a highly accurate clock oscillator that can oscillate a clock having almost the same clock frequency is expensive. Therefore, in this case, the two processing units will operate with clocks having clock frequencies that are approximately equal to each other, but with a slight error. In other words, the two processing units will each have different clocks. In such two processing units operating with clocks having different clock frequencies, the time indicated by each clock gradually shifts as time passes, and the error accumulates. If the cumulative value of this error becomes large, it becomes impossible to match the processing results of the two processing units.

Therefore, the inventor of the present application has proposed a method for synchronizing two processing units, that is, a method for adjusting the times indicated by the clocks of the two processing units.
Filed as No. 49.

The proposed conventional synchronization control method will be described below with reference to FIGS. 5 and 6. Here, it is assumed that the loop time LT corresponds to 6 milliseconds and the preset comparison value CM corresponds to 2 milliseconds. The two processing units will be referred to as a first processing unit CPU1 and a second processing unit CPU2, respectively. The first processing unit CP is higher than the first clock frequency of the first clock supplied to the first processing unit CPU1.
It is assumed that the second clock frequency of the second clock supplied to U2 is slightly higher. Therefore, the second clock (second interval timer IT2) of the second processing unit CPU2 advances slightly faster than the first clock (first interval timer IT1) of the first processing unit CPU1. Become. In addition, the first and second processing units CPU1 and CPU2 respectively include the first and second processing units.
Read-only memory, which stores exactly the same program. This program consists of a main processing routine (Fig. 5 (a)) and an interrupt processing routine (Fig. 5).
(B)). First and second processing unit C
Each of the PU1 and the CPU2 repeats the main processing routine and the interrupt processing routine three times during each loop time LT. In this synchronous control method, as will become clear as the description proceeds, the first processing unit CPU1 which is slow in advance is synchronized in order to synchronize the first and second processing units CPU1 and CPU2.
The time of the second clock of the second processing unit CPU2, which advances faster than the time of the first clock, is adjusted.

In FIG. 6, the first line shows the value of the first interval timer IT1 of the first processing unit CPU1 and the second line shows the interrupt timing of the first processing unit CPU1. Then, in the third line, the second processing unit C
Shows the value of the second interval timer IT2 of PU2,
The fourth line shows the interrupt timing of the second processing unit CPU2.

First, the first and second processing units CP
The loop time LT is started by presetting the first and second interval timers IT1 and IT2 of U1 and CPU2. From this point, the first main processing routine starts in each of the first and second processing units CPU1 and CPU2. During the processing of the first main processing routine (step S1), the first and second processing units CPU1 and CPU2 respectively compare the values of the first and second interval timers IT1 and IT2 with the comparison value. .. As described above, since the second interval timer IT2 advances faster than the first interval timer IT1, the value of the second interval timer IT2 and the comparison value match first.
At the time of this coincidence, the first interrupt 1 is generated in the main processing routine of the second processing unit CPU2. The period from the start time of the loop time LT to the occurrence time of the first interrupt 1 corresponds to 2 milliseconds of the second clock of the second processing unit CPU2. After the occurrence of the first interrupt, the second processing unit CPU2 performs the processing of the first interrupt processing routine (FIG. 5B). In this interrupt processing routine, first, the number of interrupts is counted (step S2).
Then, the second interval timer IT2 is preset (step S3).

Subsequently, the first interval timer I
The value of T1 and the comparison value match, and at the time of this match, the first interrupt 1 occurs in the main processing routine of the first processing unit CPU1. The period from the start time of the loop time LT to the generation time of the first interrupt 1 corresponds to 2 milliseconds of the first clock of the first processing unit CPU1. Similar to the case of the second processing unit CPU2, after the occurrence of the first interrupt, the processing of the first interrupt processing routine (FIG. 5B) is performed in the first processing unit CPU1.
In this interrupt processing routine, the number of interrupts is first counted (step S2), and then the first interval timer IT1 is preset (step S3).

In this way, the first and second processing units CPU1 and CPU2 perform the first interrupt processing routine process (step S4), and first the second processing unit CPU2 interrupt processing routine is executed. After the processing is completed, the first processing unit CPU continues.
The processing of the interrupt processing routine 1 ends. Here, it is assumed that the processing time of the interrupt processing routine of the first processing unit CPU1 is x milliseconds. In each of the first and second processing units CPU1 and CPU2, when the processing of the interrupt processing routine is completed, the process returns to the main processing routine (FIG. 5A) and the second main processing routine is executed.

In the same manner, the second and third interrupts are generated in each of the first and second processing units CPU1 and CPU2 every 2 milliseconds, and the second and third interrupt processing routines are executed. Is processed.
In this third interrupt processing routine, "3" is counted as the number of interrupts. After the processing of the third interrupt processing routine is completed, each of the first and second processing units CPU1 and CPU2 returns to the main processing routine again. Here, first, the second processing unit CPU2 returns to the main processing routine, and the number of interrupts is "3" (YES in step S5), so the number of interrupts is reset to "0" (step S6), and then the first The second processing unit CPU2 transfers the synchronization signal to the first processing unit CPU1 in order to synchronize with the first processing unit CPU1 (step S7). Then, the second processing unit CPU2 enters the waiting state. Then,
The first processing unit CPU1 returns to the main processing routine and the number of interrupts is "3" (YE in step S5).
S), reset the number of interrupts to "0" (step S6)
Then, in order to synchronize with the second processing unit CPU2, the first processing unit CPU1 transfers a synchronization signal to the second processing unit CPU2 (step S7).

In both the first and second processing units CPU1 and CPU2, the synchronization signal generated by itself and the synchronization signal from the other are confirmed (Y in step S7).
ES) and the first and second processing units CPU1 and CPU2 preset the first and second interval timers IT1 and IT2, respectively (step S8). As a result, the first and second processing units CPU1 and CPU2 are synchronized and the next loop time LT starts.

Here, as shown in FIG. 6, the actual loop time LT in the first processing unit CPU1 is
Note that the first clock has (6 + x) milliseconds instead of 6 milliseconds. Of course, the actual loop time LT in the second processing unit CPU2 is longer than (6 + x) milliseconds in the second clock. At any rate, as is apparent from the above description, it is possible to set the time of the second clock of the fast second processing unit CPU2 to the time of the first clock of the slow first processing unit CPU1.

As described above, since the two processing units operate in synchronization with the clocks from the different clock oscillators respectively, even if the clock oscillator on the side of the processing unit on one side fails, the clock on the other side fails. As long as the oscillator is operating normally, the processing unit clocked by this clock oscillator will operate normally.
In this case, the synchronization signal is not sent out from the inoperable processing unit no matter how much time is waited, so it was confirmed that this synchronization signal was not sent even after waiting a predetermined time in the processing unit operating normally. At this point, it is determined that the other processing unit has failed. As a result, the processing unit that is operating normally can perform processing that releases the brake control by the ABS control circuit and returns to normal brake control. That is, fail safe can be performed.

[0021]

In the above-mentioned conventional synchronous control method, the actual loop time is added by the interrupt processing time (x milliseconds) even though the loop time is set to 6 milliseconds. It becomes (6 + x) milliseconds. The loop time error based on the interrupt processing time accumulates in proportion to the braking time. On the other hand, the program stored in the read-only memory ROM is preprogrammed so as to obtain the optimum braking action when the loop time is 6 milliseconds. Therefore, the ABS control circuit adopting the conventional synchronous control method cannot perform precise ABS control due to accumulation of loop time errors.

The drawbacks of such a conventional synchronous control method are not only appearing only in the ABS control circuit, but also appearing in other parallel processing systems (parallel redundant systems).

Therefore, an object of the present invention is to provide a synchronous control method for a plurality of processing units, which enables a parallel processing system having a plurality of processing units to perform precise control.

[0024]

According to the method for controlling synchronization between a plurality of processing units according to the present invention, each has a dedicated clock oscillator, and a predetermined loop time is synchronized with a clock signal supplied from the clock oscillator. The process of performing the interrupt process a predetermined number of times is repeated, and the clocking operation for clocking the clock signal preset at each start time of the loop time and each interrupt process is started, and the clocked value matches the predetermined comparison value. When there are a plurality of processing units that newly perform the interrupt processing, when the last interrupt processing in the loop time of each processing unit is completed, the processing units are synchronized with each other, In the synchronous control method for matching the start time points of the loop times of all the processing units, the processing units are Immediately after the start of the interrupt processing, as the comparison value, a value obtained by dividing the loop time by the number of times of the interrupt processing, and immediately after the start of the loop time as the comparison value, in parallel in all the processing units. It is characterized in that the smallest one of the time count values at the time of ending the interrupt processing at the end of the last loop time executed is set to a value obtained by subtracting from the predetermined comparison value.

[0025]

Embodiments of the present invention will now be described with reference to the drawings.

FIG. 2 is a block diagram showing a parallel processing system to which the synchronous control method according to the present invention can be applied. In the present embodiment, the illustrated parallel processing system is an ABS control circuit.

The ABS control circuit has first and second processing units CPU1 and CPU2. The first and second processing units CPU1 and CPU2 respectively include first and second clock oscillators CO1 and C2.
First and second clocks having first and second clock frequencies are supplied from O2.

The first and second processing units CPU1 and CPU2 respectively output the first and second synchronization signals via the first and second synchronization signal lines 11 and 12, respectively, as described later. First processing unit CPU
2 and CPU1. The first and second processing units CPU1 and CPU2 are connected to each other via a data bus 13. As will be described later, first and second timer values are transferred from the first and second processing units CPU1 and CPU2 to the second and first processing units CPU2 and CPU1 via the data bus 13, respectively. To be done.

The first and second processing units CPU1 and CPU2 output first and second control signals, respectively. The first and second control signals are ANDed by the AND circuit 14 and then sent to the actuator (solenoid valve). That is, in the AND circuit 14, the first
Only when the control signal of 1 and the second control signal match, the matched control signal is sent to the actuator.

The first and second processing units CPU1 and CPU2 respectively include first and second read-only memories (not shown) in which exactly the same programs are stored. Therefore, the first and second processing units CPU1 and CPU2 respectively include the first and second clock oscillators CO1 and CO2.
The same predetermined processing is performed in synchronism with the first and second clocks supplied from 2. Assumptions made to explain the prior art are also made here. That is, it is assumed that the loop time LT corresponds to 6 milliseconds and the comparison value CM preset in the register (described later) corresponds to 2 milliseconds. The first processing unit CPU2 is higher than the first clock frequency of the first clock supplied to the first processing unit CPU1.
It is assumed that the second clock frequency of the second clock supplied to the is slightly higher. Therefore, the first clock (first interval timer IT of the first processing unit CPU1
The second clock (second interval timer IT2) of the second processing unit CPU2 advances slightly faster than 1).

FIG. 1 shows programs stored in the first and second read-only memories. Like the program shown in FIG. 5, the program shown in FIG. 1 has a main processing routine (FIG. 1A) and an interrupt processing routine (FIG. 1B). Each of the first and second processing units CPU1 and CPU2 repeats the main processing routine and the interrupt processing routine three times during each loop time LT.

In FIG. 1, steps similar to those in FIG. 5 showing a program for realizing the conventional synchronization control method are designated by the same reference numerals, and the description thereof will be omitted for simplification of the description. 1 is different from FIG. 5 in that step S9 for storing a preset value as a comparison value in a register is added to the interrupt processing routine, and step S1 for reading the timer value in the main processing routine.
0, step S11 for transferring the timer value to the other CPU, step S12 for selecting the smaller timer value of the own CPU and the other CPU as the timer value TM, and the timer value TM from the preset value as the comparison value. That is, step S13 of storing the value obtained by subtracting the value in the register is added.

The synchronization control method according to the present invention will be described below with reference to FIGS. 1, 2 and 3.

In the main processing routine, step S
7, first and second processing units CPU1 and CP
If the synchronization signal is confirmed with both U2, the first and second processing units CPU1 and CPU2 change the values of the first and second interval timers IT1 and IT2, respectively, to the first and second timer values. TM1 and T
After being read as M2 (step S10), the first and second timer values TM1 and TM2 are preset (step S8). Then, the first and second processing units CPU1 and CPU2 respectively read the read first and second timer values TM1 and TM2 via the data bus 13 (FIG. 2). The data is transferred to the processing units CPU2 and CPU1 (step S11). In the first and second processing units CPU1 and CPU2, respectively, the first and second timer values TM
The smaller value of 1 and TM2 is selected as the timer value TM (step S12). In this example, since the first timer value TM1 is smaller than the second timer value TM2, the first timer value TM1 is selected as the timer value TM.

In each of the first and second processing units CPU1 and CPU2, the timer value TM is subtracted from the preset comparison value CM, and the value obtained by the subtraction is stored in a register (not shown) as a new comparison value CM. (Step S13). That is, a value obtained by subtracting the timer value TM from the preset comparison value CM is set as the first comparison value CM for the next loop time LT.

On the other hand, the comparison value CM of the second and third times
Respectively, during the first and second interrupt handling,
In step S9 of the interrupt processing routine, a preset value (corresponding to 2 milliseconds) is set.

As a result, as shown in FIG. 3, the time from the start time of the loop time LT to the first interrupt generation time is equal to 2 milliseconds minus the timer value TM. Also, the time from the first interrupt occurrence time to the second interrupt occurrence time and the time from the second interrupt occurrence time to the third interrupt occurrence time are equal to 2 milliseconds. The time from the occurrence of the third interrupt to the start of the next loop time LT, that is, the interrupt processing time, is equal to the timer value TM. As a result, each loop time LT is exactly equal to 6 ms on the clock of the slower CPU.

In the above embodiment, an example in which the synchronization control method according to the present invention is realized by software has been described. However, as described below, the synchronization control method according to the present invention may be realized by hardware.

FIG. 3 shows first and second processing units CPU1 and CPU for realizing the synchronous control method according to the present invention.
2 shows an example of the configuration.

Each of the first and second processing units CPU1 and CPU2 has an interval timer 21 for performing a time counting operation and a register 22 for storing a comparison value CM. Conventionally, the comparison value CM stored in the register 22 is a fixed value, but in the present invention, it is not a fixed value but is selectively set as described later. The interval timer 21 is preset as described later. The value of the interval timer 21 and the comparison value CM are compared by the comparator 23, and when these values match, the comparator 23 outputs a value match signal. This value matching signal is supplied to the interrupt processing unit 24 as an interrupt signal. Further, the value coincidence signal presets the interval timer 21 via the OR gate 25. In response to this value match signal, the counter 26 counts the number of interrupts. The comparator 27 compares the number of interruptions with a predetermined number (“3” in this example), and if these numbers match, the comparator 27 outputs a number match signal. This number coincidence signal is latched by the latch circuit 28. Further, the counter 26 is reset by the number coincidence signal.

When the number match signal is latched, the latch circuit 2
8 supplies the latched signal to the AND gate 29. An interrupt processing end signal is supplied from the interrupt processing unit 24 to the AND gate 29. Therefore, the AND gate 29 passes the interrupt processing end signal supplied after the number of interrupts reaches "3". This AND gate 29
The signal passed through is sent to another CPU as a synchronizing signal and is also supplied to the AND gate 3. In response to the passed interrupt processing end signal, the register 31 holds the value of the interval timer 21. This held value is
It is equal to the timer value corresponding to the interrupt processing time. The timer value held in the register 31 is transferred to another CPU via the data bus 13. On the other hand, the register 32 holds the timer value transferred from another CPU.

The AND gate 30 is supplied with the synchronization signal transferred from another CPU. Therefore, when the AND gate 30 receives a synchronization signal from both the own CPU and another CPU, the AND gate 30 supplies the synchronization timing signal to the interval timer 21 via the OR gate 25 to preset the interval timer 21. Further, the latch circuit 28 is reset by this synchronization timing signal.

The minimum value selection circuit 33 includes two registers 31.
A smaller value is selected from the timer values held in and 32, and the selected timer value TM is output. Subtractor 3
Reference numeral 4 subtracts the timer value TM from a preset value (this value corresponds to 2 milliseconds, "10" in this example) and outputs the subtraction result. One of the subtraction result and the preset value is selected by the selector 35, and the selected value is the comparison value CM.
Is stored in the register 22 as The selector 35 has
A signal obtained by delaying the latched signal output from the latch circuit 28 by a predetermined delay time by the delay circuit 36 is supplied as a selection instruction signal. Here, the reason why the latched signal output from the latch circuit 28 is not directly supplied to the selector 35 as the selection instruction signal but the delayed signal from the delay circuit 36 is used as the selection instruction signal of the selector 35 is as follows. The range of the predetermined delay time of the delay circuit 36 will be described later in detail. In any case, the selector 35 selects the subtraction result as the selected value when the selection instruction signal indicates the logical high level H, and preset as the selected value when the selection instruction signal indicates the logical low level L. Select a value.

The hardware synchronization control method of the present invention will be described below with reference to FIGS. 2, 3 and 4.

If the synchronization signal is confirmed by the AND gate 30 in both the first and second processing units CPU1 and CPU2, the first and second processing units C
PU1 and CPU2 respectively register the values of the first and second interval timers IT1 and IT2 as the first and second timer values TM1 and TM2, respectively.
After reading 1 and 32, the first and second timer values TM1 and TM2 are preset. Then, the first and second processing units CPU1 and CPU2
Respectively read the read first and second timer values TM1 and TM2 through the data bus 13 (FIG. 2) into the second and first processing units CPU2 and CP, respectively.
Transfer to U1. First and second processing unit CPU
In the CPU 1 and the CPU 2, the minimum value selector 33 selects the smaller one of the first and second timer values TM1 and TM2 as the timer value TM. In this example, the first timer value TM1 is the second timer value TM
Since it is smaller than 2, the first timer value TM1 is selected as the timer value TM.

In each of the first and second processing units CPU1 and CPU2, the timer value TM is subtracted from the comparison value CM preset by the subtractor 34, and the value obtained by the subtraction is transferred to the register 2 via the sector 35.
2 is stored as a new comparison value CM. That is, a value obtained by subtracting the timer value TM from the preset comparison value CM is set as the first comparison value CM for the next loop time LT.

Here, regarding the storage timing of storing the subtracted value from the subtractor 34 as a new comparison value CM in the register 22 via the ector 35, the delay circuit 36 will be described.
Will be described in association with the predetermined delay time. This storage timing needs to satisfy the following conditions. The storage timing is before the time of "CM = CM-TM" in FIG. At the time of “CM = CM-TM” in FIG. 3, the selector 3
5 means that the subtractor 34 side is selected. In order to satisfy these two conditions, the predetermined delay time Td set in the delay circuit 36 needs to satisfy the range represented by the following mathematical formula 1.

[0048]

[Equation 1]

On the other hand, the comparison value CM for the second and third times
Are respectively set to values (“10” corresponding to 2 milliseconds) preset by the selector 35 during the first and second interruption processing in the interruption processing unit 24.

As a result, as shown in FIG. 3, the time from the start of the loop time LT to the occurrence of the first interrupt is equal to 2 milliseconds minus the timer value TM. Also, the time from the first interrupt occurrence time to the second interrupt occurrence time and the time from the second interrupt occurrence time to the third interrupt occurrence time are equal to 2 milliseconds. The time from the occurrence of the third interrupt to the start of the next loop time LT, that is, the interrupt processing time, is equal to the timer value TM. As a result, each loop time LT is exactly equal to 6 ms on the clock of the slower CPU.

In the above-described embodiment, the synchronization control method is AB
Although the case of application to the S control circuit has been described, the present invention can be applied to a system that requires high reliability in the field of car electronics and must avoid runaway, such as a four-wheel steering control circuit and a traction control circuit. further,
The synchronous control method of the present invention can be applied to a system that requires reliability other than the field of car electronics, such as an aircraft control system.

Further, in the above embodiment, the number of processing units is two.
I explained the case of parallel processing system that includes 3
It is similarly applicable to a parallel processing system having more than one processing unit.

[0053]

As described above, according to the present invention,
Each time the loop ends, synchronization is made between multiple processing units, the timer value of each processing unit is transferred, and the value with the minimum timer value subtracted from the comparison value is compared for the first time in the next loop. By setting a value, the interrupt interval can always be made the same, and the loop time can also be created by interrupt processing, so control output can be performed within interrupt processing, and more precise control for parallel processing systems. Can be done.

[Brief description of drawings]

FIG. 1 is a flowchart showing a program stored in a read-only memory of each processing unit to implement a synchronous control method according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a parallel processing system to which the present invention is applied.

FIG. 3 is a time chart for explaining a synchronization control method according to an embodiment of the present invention.

FIG. 4 is a functional block diagram of each processing unit constituting the parallel processing system.

FIG. 5 is a flowchart showing a program stored in a read-only memory of each processing unit to realize a conventional synchronization control method.

FIG. 6 is a time chart for explaining a conventional synchronization control method.

[Explanation of symbols]

 S1 Main processing step in the main processing routine S2 Interrupt count step S3 Timer preset step S5 Interrupt count determination step S6 Interrupt count reset step S7 Synchronization confirmation step S8 Timer preset step S9 Comparison value setting step S10 Timer value reading step S11 Timer value transfer Step S12 Timer value selection step S13 Comparison value setting step

Claims (1)

[Claims] 1. Each has a dedicated clock oscillator, and in synchronism with a clock signal supplied from this clock oscillator, a process of performing an interrupt process a predetermined number of times within a predetermined loop time is repeated, and the loop time and There is a plurality of processing units that newly perform the interrupt processing when the clocking operation preset for each start time of each interrupt processing starts a clocking operation for clocking the clock signal and the measured time value matches a predetermined comparison value. When the last interrupt processing in the loop time of each processing unit is completed, the processing units are synchronized with each other,
In the synchronous control method of matching the start time points of the loop times of all the processing units, the processing unit divides the loop time by the number of times of the interrupt processing as the comparison value immediately after the start of the interrupt processing. Value, and as the comparison value immediately after the start of the loop time, the smallest one of the measured values at the end of the interrupt processing at the end of the last loop time executed in parallel in all the processing units. Is a value obtained by subtracting from the predetermined comparison value.