JPS59127164A - Multi-system synchronizing device - Google Patents

Abstract

PURPOSE:To ensure the overall synchronization of systems and at the same time to attain synchronizing operation of a system as long as just one of processors is nondefective, by defining one of clocks which are owned properyly by plural processors respectively as a system shared clock. CONSTITUTION:A clock signal 28 produced by a clock generating circuit 21 is supplied to a counter 22, and to a clock feed line 10 through a buffer gate 26. While the output of the counter 22 is supplied to a comparator 23. If the coincidence is obtained between this output and the set value 24 which is proper to each of plural processors, a coincidence signal 29 is delivered. This signal 29 triggers a one-shot multivibrator 25, and the gate 26 of the clock 28 is opened by the output of the multivibrator 25. The output of the comparator 23 is also delivered to a shared clock setting line 11 to reset the counter 22 which is provided in each of those processors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a system consisting of a plurality of devices that operate with their own clocks, and in particular, to a system that operates all the devices synchronously and uses the clock of one device. When stopped, the lock supply device is capable of continuing operation using the clock of another device.

[Prior art]

A system that uses multiple processing devices for specific processing or control, such as a multiprocessor system that processes a large amount of data in a divided and distributed manner, or a multiplex system that aims for high reliability. It is used in various fields.

In this type of system, when a system outputs to its service target, it executes processing based on information at a fixed time and does not output at a fixed time.In other words,
In many cases, a system cannot function normally unless synchronization is established between multiple processing devices.

Conventionally, the following methods have been used to synchronize such systems.

(1) Provide a common lock for the system.

(2) Synchronize when executing an input/output instruction, when starting a major task, or using an interrupt.

However, in method (1), the common lock connects the entire system into one, and an abnormality in the common lock may cause
There were drawbacks such as the possibility of system failure. There is a method to avoid this, such as Japanese Patent Publication No. 52-22219, but this also involves duplicating common locks and switching to the other when one stops. , are essentially the same, and cannot deal with power outages in clock devices, malfunctions in switching devices, etc.

Furthermore, in the case of method (2), an increase in the processing time difference is inevitable due to synchronization deviations and the accumulation of minute errors in the clock frequency.
The system was always operated in accordance with the delay system, leaving problems with processing performance, responsiveness, etc.

[Purpose of the invention]

An object of the present invention is to use one of the clocks unique to each of the plurality of processing units as a system shared clock in a functionally distributed multi-system or redundant multi-system in which a series of processing is performed by a plurality of processing units. By doing so, it is an object of the present invention to provide a multi-system synchronization device that can synchronize the entire system and enable synchronized operation of the system as long as at least one of the processing devices is healthy or has a lock.

[Summary of the invention]

In the present invention, a pulse counter of each clock source is provided for each clock source of a plurality of processing devices, and when the counter value of this clock source reaches a preset value, the device provided with this counter By issuing a synchronization signal to the processing device, the multiple processing devices that make up the system will always operate based on the clock signal issued by one processing device, and if the clock of the device that is sending the clock stops, In this case, another device takes over and supplies the system clock within a certain period of time to ensure continued operation of the system.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an example in which the present invention is applied to a parallel intermediate duplex system.

The processing units (hereinafter referred to as CTR) 12 and CTR 13 each have the same function, perform arithmetic processing based on input information from the plant, and output control outputs 15 and 16 to the output collation switch 14.
Output to. The output collation switch 14 has CTRs 12 and 13.
The outputs of the controller 10 are compared, and the signal determined to be a reasonable output is output as the control output 17. In FIG. 1, 10 is a shared clock supply line, and 11 is a shared clock setting line. Further, FIG. 2 shows a clock supply circuit inside the CTRs 12, 13 or the output collation switch 14, 14', etc. In FIG. 2, one of the clock signals 28 generated by the clock generation circuit 21 is input to the counter 22, and the other is supplied to the clock supply line 10 through the buffer gate 26.

On the other hand, the output of the counter 22 is input to the comparator 23,
When it matches the setting value 24 unique to each of the plurality of processing devices,
A coincidence signal 29 is output. The coincidence signal 29 triggers the one-shot multi 25 wo), and the output of the one-shot multi 25 triggers the buffer gate 26 of the clock 28.
opens.

The output of the comparator 29 is further connected to the shared clock setting line 11.
and resets the counters 22 inside all of the plurality of processing devices.

As a result of the above operation, only one processing device among the plurality of processing devices whose set value can match the value of its internal counter 22 always supplies the clock signal to the clock supply line. In addition, if the clock of a processing device that was supplying the clock stops due to some abnormality, the one-shot multi 25 Fito IJ will no longer be activated, the clock buffer gate 26 of this processing device will be prohibited, and other healthy processing will be disabled. Since the device's counter 22 is not reset, it will continue to count up to the set value and the system's clock will now be provided by a healthy processing unit.

FIG. 3 is a time chart showing the above operation. That is, by the internal clock of CTR12,
At time 30, when the unique set point 24 of CTR,12 is reached, a synchronization signal 30 is output and the counters of both CTR,12,13 are reset. At this time, the one-shot multi 25 is triggered and the clock of the CTR 12 is supplied to the clock supply line 10 as the system clock.

Assuming that the clock of CTR 12 stops at time 32, the counter of CTR 13 is not reset, so when time 33 is reached, it matches the unique setting value 24 of CTR 13, and the synchronization signal 29 is output from CTRI 3. , C
Reset the counters of TR, 12, and 13. and,
When the one-shot multi 25 of the CTR 13 is triggered, the buffer gate 26 is opened and the internal clock of the CTR 13 is supplied as the system clock. Operation continues in this manner.

In FIG. 2, the clock supply line 10 and the setting line 11 are provided independently, but in another embodiment as shown in FIG. 4, the two lines mentioned above can be shared by one line. is also possible. However, at this time, the system clock becomes the synchronization signal 29 shown in FIG.

In addition, in consideration of breakage of the clock line, etc., we have made it redundant.
It is also possible to triplex.

In addition, in the figure, 31 is a time, 40.41 is a clock, and 50 is a driver.

〔Effect of the invention〕

According to the present invention, it is possible to improve the processing performance, responsiveness, and operating rate of the system.

Further, when the system is expanded, additional devices can be easily synchronized, so expandability is improved, and backup clocks can be added in accordance with the expansion, improving reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram when the present invention is applied to a parallel matching duplex system, FIG. 2 is a circuit diagram of the main part of the present invention,
Figure 3 is an operation timing chart of the circuit in Figure 2;
The figure is a block diagram of a modification of the present invention. DESCRIPTION OF SYMBOLS 10... Clock supply line, 11... Shared clock setting line, 21... Clock generation circuit, 22... Counter, 23... Comparator, 24... Setting value, 26...
buffer gate. Kaya 1st $22 3rd mouth N, 4. Eye lθ 342-

Claims (1)

[Claims] 1. In a multi-system that performs parallel processing using a plurality of processing devices, a shared clock, a shared clock co-supply line, and a shared clock setting line are provided for synchronizing the entire system. Multi-system synchronization device. 2. In claim 1, each of the plurality of processing devices uses its own internal clock, thereby making the shared clock a distributed clock and achieving %N8.
What is claimed is: 1. A multi-system synchronization device, characterized in that the system is comprised of processing units, and is provided with i,1:N backup type multiplexed clock supply means. 3. In the description of claim 2, in the order processing device having its own internal clock, each device has a counter that counts its own clock, and a plurality of counting units of this counter. a circuit that generates a pulse when a uniquely set value is reached between the processing devices; and a buffer gate that allows the clock to be output to the shared clock supply line by the output of the pulse generation circuit. A multi-system synchronization device characterized by: 4. In claim 3, the pulses from the pulse generation circuits of the plurality of processing devices are outputted as a reset signal for the counters of all the processing devices via a shared clock setting line, and set individually. A multi-system synchronization device characterized in that the processing unit with the smallest value is used as the shared clock of the system.