JPH05173950A - Bus acquisition control system - Google Patents

Abstract

PURPOSE:To prevent overrun or underrun of data transfer due to too long bus acquisition time of a control board by providing a bus request control part. CONSTITUTION:A timer register 18 and a DMA control part 11 are provided. A bus request monitor timer part 16 which takes a DMA request signal 12 and a DMA permission signal 13 as the input and outputs a bus request output permission signal 17 in case that the DMA permission signal 13 is not validated within the set time of the timer counted value is provided. A bus request control part 4 which outputs a bus acquisition request signal 6 having a low priority level at the time of input of the DMA request signal 12 and outputs another bus acquisition request signal 8 having a high priority level at the time of input of a bus request output permission signal 17 and outputs the DMA permission signal 13 at the time of input of one of use permission signals 5 and 7 having low and high priority levels respectively outputted from an information processor 1 is provided. Thus, overrun or underrun of data transfer is prevented.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus acquisition control system, and more particularly to a bus acquisition control system for various control boards constituting an information processing apparatus.

[0002]

2. Description of the Related Art A control board connected to a conventional information processing apparatus has a DMA control section for performing DMA control and outputting a DMA request signal as a bus acquisition control method, and a D control section.
The bus request control unit inputs the MA request signal, outputs a predetermined one bus acquisition request signal, and inputs the bus use permission signal to acquire the bus.

[0003]

In the conventional bus acquisition control method for the control board described above, there is only one bus acquisition request signal output from the bus request control unit, and the priority is fixed or round robin. (Round-robin sche
Due to the duling, you cannot get the right to use the bus until you wait for your turn.

Therefore, with respect to the control board which cannot wait the time until the right to use the bus is obtained, there is a drawback that an error such as overrun or underrun of data transfer occurs if the bus is waited for a certain time or more.

[0005]

A bus acquisition control system according to the present invention, in a control board connected to an information processing device,
A timer register for setting a timer count value from an information processing device to a bus request monitoring timer unit in the control board, a DMA control unit for outputting a DMA request signal for performing DMA, and a DMA request signal and a DMA permission signal are input. However, when the DMA request signal is not valid within the set time of the timer count value, the bus request monitoring timer section that outputs a bus request output enable signal and the DMA request signal are input, the bus acquisition request of a low priority is input. When a signal is output and the bus request output permission signal is input, another high priority bus acquisition request signal is output, and either of the two bus use permission signals output from the information processing device is output. Enter one, DM
And a bus request control unit that outputs an A permission signal.

Further, the bus acquisition control system of the present invention is, in a control board connected to an information processing apparatus, a timer register for setting a timer count value from the information processing apparatus to a bus request monitoring timer unit in the control board. DM for outputting a DMA request signal for performing DMA
An A control unit, a bus request monitoring timer unit that inputs a DMA request signal and a DMA permission signal, and outputs a bus request output permission signal when the DMA permission signal is not valid within the set time of the timer count value; When the DMA request signal is input, a low priority bus acquisition request signal is output, and when the bus request output enable signal is input, the output of the low priority bus acquisition request signal is invalidated and another high priority bus acquisition request signal is output. A bus request control unit is provided which outputs a priority bus acquisition request signal and outputs a DMA permission signal when the bus use permission signal output from the information processing device is input.

Furthermore, the bus acquisition control system of the present invention is, in a control board connected to an information processing apparatus, a timer switch for manually setting a timer count value to a bus request monitoring timer section in the control board, and a DMA. DM for outputting a DMA request signal for performing
An A control unit, a bus request monitoring timer unit that inputs a DMA request signal and a DMA permission signal, and outputs a bus request output permission signal when the DMA permission signal is not valid within the set time of the timer count value; When the DMA request signal is input, a low priority bus acquisition request signal is output, and when the bus request output permission signal is input, another high priority bus acquisition request signal is output, and the information processing device outputs A bus request control unit that outputs a DMA permission signal when either one of the two output bus use permission signals is input is provided.

Finally, in the bus acquisition control method of the present invention, in the control board connected to the information processing device, a timer switch for manually setting a timer count value in the bus request monitoring timer section in the control board, DM for outputting a DMA request signal for performing DMA
An A control unit, a bus request monitoring timer unit that inputs a DMA request signal and a DMA permission signal, and outputs a bus request output permission signal when the DMA permission signal is not valid within the set time of the timer count value; When the DMA request signal is input, a low priority bus acquisition request signal is output, and when the bus request output enable signal is input, the output of the low priority bus acquisition request signal is invalidated and another high priority bus acquisition request signal is output. A bus request control unit is provided which outputs a priority bus acquisition request signal and outputs a DMA permission signal when the bus use permission signal output from the information processing device is input.

[0009]

The present invention outputs the low priority bus acquisition request signal from the control board and outputs the high priority bus acquisition request signal when the bus use permission signal is not obtained within a certain time, thereby waiting for the bus acquisition time. To prevent overrun and underrun of data transfer due to overwaiting.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be described below with reference to the accompanying drawings. 1 to 4 are hardware configuration diagrams of the bus acquisition control system in the control board. (1) The bus acquisition control system of FIG. 1 will be described below.

When a data transfer request is generated from the input / output control unit 14 in the control board 3, the input / output data transfer request signal 15 becomes valid and is output to the DMA control unit 11. Then, the DMA request signal 12 from the DMA control unit 11 becomes valid and is output to the bus request control unit 4 and the bus request monitoring timer unit 16. Then, the bus request control unit 4 first validates and outputs the low priority bus acquisition request signal 6 from the low priority request unit 9. Further, the bus request monitoring timer unit 16 starts counting the timer. The timer value at this time is set through the system bus 2 by an input / output command from the information processing device 1. Next, if the DMA permission signal 13 is not valid within the time set in the timer register 18, the bus request monitoring timer unit 16 determines that the high priority bus request output permission signal 1
7 is output. Then, the bus request control unit 4 validates and outputs the high priority bus acquisition request signal 8 from the high priority request unit 10. When the bus use permission signal 5 or 7 is input to either of the two bus acquisition request signals 6 and 8 output from the bus request control unit 4, the request unit 9 or 10 to DM
The A permission signal 13 is output, and acquisition of the bus is established.

As described above, according to the present invention, the timer register 1 is output after the low priority bus acquisition request signal 6 is output.
When the bus use permission signal 5 is not obtained within the fixed time set to 8, the high priority bus acquisition request signal 8 is output and the bus use permission signal 7 is promptly obtained. You will not be kept waiting too long.

When the low priority bus use permission signal 5 is input to the bus request control unit 4 within the count time set in the timer register 18, the low priority request unit 9 outputs the DMA permission signal 13. And the bus is won. (2) The bus acquisition control system of FIG. 2 will be described below.

When a data transfer request is generated from the input / output control unit 14 in the control board 3, the input / output data transfer request signal 15 becomes valid and is output to the DMA control unit 11. Then, the DMA request signal 12 from the DMA control unit 11 becomes valid and is output to the bus request control unit 4 and the bus request monitoring timer unit 16. Then, the bus request control unit 4 first validates and outputs the low priority bus acquisition request signal 6 from the low priority request unit 9. Further, the bus request monitoring timer unit 16 starts counting the timer.
The timer value at this time is set through the system bus 2 by an input / output command from the information processing device 1. Next, if the DMA permission signal 13 is not valid within the time set in the timer register 18, the bus request monitoring timer unit 16 outputs the high priority bus request output permission signal 17. Then, the bus request control unit 4 outputs the bus request switching signal 20 to the low priority request unit 9, invalidates the low priority bus acquisition request signal 6 output from the low priority request unit 9, and outputs the high priority request. The unit 10 validates and outputs the high priority bus acquisition request signal 8. When the high-priority bus use permission signal 7 is input to the high-priority bus acquisition request signal 8 output from the bus request control unit 4, the input high-priority request unit 10 outputs the DMA permission signal 13 Is output and the bus is acquired.

When the low priority bus use permission signal 5 is input to the bus request control unit 4 within the count time set in the timer register 18, the low priority request unit 9 outputs the DMA permission signal 13. And the bus is won. (3) The bus acquisition control system of FIG. 3 will be described below.

When a data transfer request is generated from the input / output control unit 14 in the control board 3, the input / output data transfer request signal 15 becomes valid and is output to the DMA control unit 11. Then, the DMA request signal 12 from the DMA control unit 11 becomes valid and is output to the bus request control unit 4 and the bus request monitoring timer unit 16. Then, the bus request control unit 4 first validates and outputs the low priority bus acquisition request signal 6 from the low priority request unit 9. Further, the bus request monitoring timer unit 16 starts counting the timer.
For the timer value at this time, the control board 3 is connected to the system bus 2
Timer switch 2 on the control board 3 before connecting to
Set manually by 1. Next, the timer switch 21
If the DMA permission signal 13 is not validated within the time set to, the bus request monitoring timer unit 16 outputs the high priority bus request output permission signal 17. Then, the bus request control unit 4 validates and outputs the high priority bus acquisition request signal 8 from the high priority request unit 10. When the bus use permission signal 5 or 7 is input to either of the two bus acquisition request signals 6 and 8 output from the bus request control unit 4, the request unit 9 or The DMA enable signal 13 is output from 10 and the acquisition of the bus is established.

When the low priority bus use permission signal 5 is input to the bus request control unit 4 within the count time set in the timer switch 21, the low priority request unit 9 outputs the DMA permission signal 13. And the bus is won. (4) The bus acquisition control system of FIG. 4 will be described below.

When a data transfer request is generated from the input / output control unit 14 in the control board 3, the input / output data transfer request signal 15 becomes valid and is output to the DMA control unit 11. Then, the DMA request signal 12 from the DMA control unit 11 becomes valid and is output to the bus request control unit 4 and the bus request monitoring timer unit 16. Then, the bus request control unit 4 first validates and outputs the low priority bus acquisition request signal 6 from the low priority request unit 9. Further, the bus request monitoring timer unit 16 starts counting the timer.
For the timer value at this time, the control board 3 is connected to the system bus 2
Timer switch 2 on the control board 3 before connecting to
Set manually by 1. Next, the timer switch 21
If the DMA permission signal 13 is not validated within the time set to, the bus request monitoring timer unit 16 outputs the high priority bus request output permission signal 17. Then, the bus request control unit 4 outputs the bus request switching signal 20 to the low priority request unit 9, invalidates the low priority bus acquisition request signal 6 output from the low priority request unit 9, and outputs the high priority request. The unit 10 validates and outputs the high priority bus acquisition request signal 8. When the high priority bus use permission signal 7 is input to the high priority bus acquisition request signal 8 output from the bus request control unit 4, the input high priority request unit 10 to D
The MA permission signal 13 is output, and acquisition of the bus is established.

When the low priority bus use permission signal 5 is input to the bus request control unit 4 within the count time set in the timer switch 21, the low priority request unit 9 outputs the DMA permission signal 13. And the bus is won.

[0020]

As described above, according to the present invention, (1) the bus request control section has two request sections having different bus acquisition priorities, and the bus request is controlled by the timer register and the bus request monitoring timer section. The output of the high priority bus acquisition request signal output from the control unit is controlled. (2) The bus request control unit has two request units with different bus acquisition priorities, and the timer register and the bus request monitoring timer unit output two bus acquisition request signals output from the bus request control unit. Control switching. (3) The bus request control unit has two request units with different bus acquisition priorities, and a high priority bus acquisition request signal output from the bus request control unit by the timer switch and the bus request monitoring timer unit. Control the output of. (4) The bus request control unit has two request units with different bus acquisition priorities, and the timer switch and the bus request monitoring timer unit output two bus acquisition request signals output from the bus request control unit. Control switching. If a wait time occurs in bus acquisition of the control board by any of the above four methods, a high priority bus acquisition request signal is output after a certain period of time set in the timer register or timer switch, and the bus acquisition By shortening the time, it is possible to prevent the overrun or underrun of the data transfer which occurs due to the bus acquisition time of the control board being kept waiting too long.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of a first embodiment of the present invention.

FIG. 2 is a block circuit diagram of a second embodiment of the present invention.

FIG. 3 is a block circuit diagram of a third embodiment of the present invention.

FIG. 4 is a block circuit diagram of a fourth embodiment of the present invention.

[Explanation of symbols]

 1 Information processing device 2 System bus 3 Control board 4 Bus request control unit 5 Low priority bus use permission signal 6 Low priority bus acquisition request signal 7 High priority bus use permission signal 8 High priority bus acquisition request signal 9 Low priority Degree request section 10 high priority request section 11 DMA control section 12 DMA request signal 13 DMA enable signal 14 input / output control section 15 input / output data transfer request signal 16 bus request monitoring timer section 17 high priority bus request output enable signal 18 timer Register 19 Timer set value output signal 20 Bus request switching signal 21 Timer switch

Claims (4)

[Claims] 1. In a control board connected to an information processing apparatus, a timer register for setting a timer count value from an information processing apparatus to a bus request monitoring timer section in the control board, and a DMA request signal for performing DMA. A DMA control unit for outputting and a bus request monitoring timer unit for inputting a DMA request signal and a DMA permission signal and outputting a bus request output permission signal when the DMA permission signal is not valid within the set time of the timer count value. When the DMA request signal is input, a low priority bus acquisition request signal is output, and when the bus request output permission signal is input, another high priority bus acquisition request signal is output, When either one of the two bus use permission signals output from the device is input, the DMA permission signal is input. And a bus request control unit that outputs a signal. 2. A control board connected to an information processing apparatus, comprising a timer register for setting a timer count value from the information processing apparatus to a bus request monitoring timer unit in the control board, and a DMA request signal for performing DMA. A DMA control unit for outputting and a bus request monitoring timer unit for inputting a DMA request signal and a DMA permission signal and outputting a bus request output permission signal when the DMA permission signal is not valid within the set time of the timer count value. When the DMA request signal is input, a low priority bus acquisition request signal is output, and when the bus request output enable signal is input, the output of the low priority bus acquisition request signal is invalidated and another Bus acquisition request signal that is output from the information processing device And a bus request control unit that outputs a DMA enable signal when the bus acquisition control method is input. 3. A control board connected to an information processing device, wherein a timer switch for manually setting a timer count value to a bus request monitoring timer section in the control board and a DMA request signal for performing DMA are output. A DMA control unit, a bus request monitoring timer unit that inputs a DMA request signal and a DMA permission signal, and outputs a bus request output permission signal when the DMA permission signal is not valid within the set time of the timer count value; When the DMA request signal is input, a low priority bus acquisition request signal is output, and when the bus request output permission signal is input, another high priority bus acquisition request signal is output, and the information processing device outputs The DMA enable signal is output when either of the two output bus enable signals is input. And a bus request control unit for controlling bus acquisition control. 4. A control board connected to an information processing device, wherein a timer switch for manually setting a timer count value to a bus request monitoring timer section in the control board and a DMA request signal for performing DMA are output. A DMA control unit, a bus request monitoring timer unit that inputs a DMA request signal and a DMA permission signal, and outputs a bus request output permission signal when the DMA permission signal is not valid within the set time of the timer count value; When the DMA request signal is input, a low priority bus acquisition request signal is output, and when the bus request output enable signal is input, the output of the low priority bus acquisition request signal is invalidated and another high priority bus acquisition request signal is output. The priority bus acquisition request signal is output, and the bus use permission signal output from the information processing device is input. Then, a bus request control unit for outputting a DMA permission signal, and a bus acquisition control method.