JPH05167570A - Clock reproduction circuit - Google Patents

Abstract

PURPOSE:To enable a small-scaled circuit configuration which is suitable for the reception of a burst signal in a low noise power density ratio against reception energy state by controlling the frequency characteristic of a loop filter and the modulation sensitivity characteristic of a digital control oscillator at the time of the pull-in of the burst signal. CONSTITUTION:A base band signal is sampled by the timing of the output signal from a digital control oscillator 53 in a data identification device 51 and an A/D conversion is performed for the signal. Next, an edge detector 52 detects the data change point of a digital signal, the phase of the output signal of the detector 52 and the output signal of the oscillator 53 are compared in a phase comparator 54 and the output signal according to the phase difference is outputted. The output signal of the comparator 54 is imparted as a control input to the oscillator 53 through a loop filter 55. At the time of the pull-in of the burst signal, the frequency characteristic of the filter 55 and the modulation sensitivity characteristic of the oscillator 53 are converted to a characteristic capable of performing a high speed pull-in by a control circuit 56. After the pull-in is performed, the original characteristics are returned. Thus, a circuit suitable for a high speed operation can be obtained.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock recovery circuit of digital signal processing type which is used in a receiver such as a digital mobile communication system and which gives a timing for demodulating a digital signal and identifying data. ..

In the mobile radio communication systems of recent years, the allocated frequency bands are almost used, and it is becoming difficult to cope with the increase in the number of systems and users, and therefore the reallocation of frequency bands is difficult. Is needed. However, simply reallocating the frequency cannot cope with the future increase, and therefore the communication system itself is shifting from the analog system to the digital system. In particular, in car telephones, the π / 4 shift QPSK modulation method and TDMA (Time Diction
vision Multiple Access) A combination of communication methods is about to be adopted. In this TDMA communication, since a signal is intermittently transmitted as a burst, the demodulator on the receiving side needs to operate intermittently to pull in the burst signal at high speed.
Therefore, the clock recovery circuit used in the demodulator is also required to be of a type capable of intermittent operation and high-speed pull-in.

[0003]

2. Description of the Related Art A clock recovery circuit of a conventional digital signal demodulator is roughly divided into a configuration in which an A / D conversion mechanism is not included in a PLL feedback loop as typified by FIG. The PLL feedback loop as described above is divided into two types, that is, a configuration including an A / D conversion mechanism.

The clock recovery circuit of FIG. 6 is of a feedforward type, and this feedforward type clock recovery circuit has a reception energy-to-noise power density ratio Eb / N.
o is relatively good reception (average lower limit is 6-8d)
B), that is, used for receiving a burst signal in a reception state in which noise is relatively small, and has a configuration in which the A / D conversion mechanism is not included in the PLL feedback loop.

On the other hand, the clock recovery circuit of FIG. 7 is a double sampling type clock recovery circuit composed of a digital signal processing type PLL circuit which is often used for receiving continuous signals in satellite communication, and has a relatively small Eb / No. It is used to receive continuous signals in bad reception conditions (average lower limit is 1 to 2 dB).
It is configured to include a / D conversion mechanism.

In the feedforward type clock recovery circuit shown in FIG.
Is converted into binary digital data with the edge detector 22
The data change point of the output signal of the comparator 20 is detected by the phase detector 24 and the phase difference between the output signal of the edge detector 22 and the output signal of the digital control oscillator 22 is detected by the phase comparator 24.
The PLL circuit has a basic configuration in which the detected phase difference of the phase comparator 24 is applied as a control input to the digitally controlled oscillator 23 through the loop filter 25. Then, the output of the digitally controlled oscillator 23 is input to the A / D converter 1 through the phase shifter 31, and the phase shifter 31 adjusts the sampling timing of the A / D converter 1 to obtain an appropriate timing of the eye pattern. I am trying to sample in.

In this feedforward type clock recovery circuit, in order to pull in the burst signal at a high speed, the control circuit 26 operates the initial phase matching circuit 27 at the time of pulling in, and the initial phase matching circuit 27 causes the digital control oscillator 23 to operate. Is forcibly matched with the phase of the output signal of the comparator 20, and the frequency characteristic of the loop filter 25 and the modulation sensitivity characteristic of the digitally controlled oscillator 23 are changed by the control circuit 26 so that they can be pulled at high speed.

On the other hand, in the double sampling clock recovery circuit of FIG. 7, the analog baseband signal is a multi-bit binary encoded digital signal by the A / D converter 1 by the output signal of the digitally controlled oscillator 23. Is converted to. The phase difference between the output signal of the A / D converter 1 and the output signal of the digitally controlled oscillator 23 is the phase comparator 2
4 and the detected phase difference is detected by the loop filter 2
5, it becomes a signal for controlling the digitally controlled oscillator 23.

The double-sampling type clock recovery circuit has the structure of such a general PLL circuit and is suitable for receiving a continuous wave. However, in order to pull in a burst signal at a high speed, a loop is usually used at the time of pulling in. The time constant of is switched from a long state to a short state. For example, at the time of pull-in, the control circuit 26 stops the control by the PLL loop of the digitally controlled oscillator 23 to make free-run oscillation, and during that time, the kick-off circuit 41 shifts the phase by about π (rad) from the average for several symbols. It is detected whether or not, and if it deviates by nearly π, the phase of the digitally controlled oscillator 23 is shifted by π so as to avoid the state that takes the longest time to pull in (generally called hang-up), and the control circuit 26 , The frequency characteristics of the loop filter 25 and the digitally controlled oscillator 2
By changing the modulation sensitivity characteristic of No. 3, the time constant of the loop filter 25 is shortened, and the pull-in time is shortened. After the pull-in is completed, the frequency characteristic of the loop filter 25 and the modulation sensitivity characteristic of the digitally controlled oscillator 23 are changed so as to lengthen the loop time constant, and the baseband signal is sampled by the A / D converter 1 at an appropriate timing of the eye pattern. To be done.

[0010]

In the former feedforward type clock recovery circuit, it is necessary to match the output signal of the digitally controlled oscillator 23 with the sampling timing of the A / D converter 1 by the phase shifter 31, and this adjustment is troublesome. It is not possible to compensate for timing shift due to temperature change, and it is suitable for receiving burst signals, but it is used in low Eb / No state such as satellite communication. It has a drawback in that it is not suitable for.

In the latter double-sampling type clock regenerating circuit, the A / D converter 1 in the feedback loop requires a certain time for conversion, and in fact, the other demodulation function processing circuit is the A / D converter. Since it enters between the converter 1 and the phase comparator 24, the delay time in the loop increases, so that the pull-in is surely delayed, and the conversion speed of the A / D converter 1 is 2 samples per symbol. The resolution is low and the pull-in is slow, the kick-off circuit 41 requires time to estimate the initial phase, and the pull-in is slow. It is suitable for use in a low Eb / No state, but originally it is continuous. It is a configuration for waves and is not suitable for receiving burst signals. In order to be able to receive burst signals, the control for that becomes complicated and the circuit scale becomes large. It, such as has become a drawback.

The present invention has been made in view of the above technical problems, and its object is to obtain a low Eb / N.
An object of the present invention is to provide a clock recovery circuit suitable for receiving a burst signal in the on-state and which can be composed of a small-scale circuit.

[0013]

FIG. 1 is an explanatory view of the principle of the present invention. In the present invention, a digitally controlled oscillator 53 for generating a sampling timing signal given to a data discriminator 51 for A / D converting a baseband signal.
And an edge detector 52 for detecting a data change point of the digital signal output from the data discriminator 51, a phase of the output signal of the edge detector 52 and a phase of the output signal of the digital control oscillator 53 are compared, and the phase difference is obtained. A phase comparator 54 that outputs a corresponding output signal, a loop filter 55 that applies the output signal of the phase comparator 54 to the digital control oscillator 53 as a control input, a frequency characteristic of the loop filter 55 and / or a modulation of the digital control oscillator 53. And a control circuit 56 for controlling the sensitivity characteristic. When the burst signal is pulled in, the control circuit 56 changes the frequency characteristic of the loop filter 55 and / or the modulation sensitivity characteristic of the digitally controlled oscillator into one that can be pulled in at high speed. A clock recovery circuit is provided.

In the above clock recovery circuit, the digitally controlled oscillator has a ratio of the frequency of the signal given to the data discriminator 51 and the frequency of the signal given to the phase comparator 52 to n.
(N is a value of 2 or more): 1 can be configured. In the clock recovery circuit described above, the digital control oscillator 5 is controlled under the control of the control circuit 56 at the time of pulling in.
An initial phase matching circuit for forcibly matching the phase of the output signal of No. 3 with the phase of the output signal of the discriminator 51 may be further provided. In the clock recovery circuit described above, an analog voltage control oscillator is used instead of the digital control oscillator 53, and the control signal from the loop filter 55 is D / A.
It can be configured such that the voltage is converted into an analog signal by the converter and then input to the voltage controlled oscillator.

[0015]

The baseband signal is sampled by the data discriminator 51 at the timing of the output signal from the digitally controlled oscillator 53 and A / D converted. An edge detector 52 detects a data change point of the digital signal output from the data discriminator 51, and a phase comparator 54 compares the phases of the output signal of the edge detector 52 and the output signal of the digital control oscillator 53. Output an output signal corresponding to the phase difference. The output signal of the phase comparator 54 is the loop filter 5
5 is supplied as a control input to the digitally controlled oscillator 53, and thereby a PLL circuit is configured to sample the baseband signal by the data discriminator 51 at an appropriate timing of the eye pattern.

When the burst signal is pulled in, the control circuit 56 controls the frequency characteristics of the loop filter 55 and / or
Alternatively, the modulation sensitivity characteristic of the digitally controlled oscillator is changed to a characteristic that allows high-speed pull-in, and after pull-in, the original characteristic is restored, thereby suppressing jitter in a steady state.

Further, by making the frequency of the sampling timing signal supplied from the digitally controlled oscillator 53 to the data discriminator larger than that of the signal for phase comparison, a multi-sampling type can be realized, and the time resolution can be increased to be suitable for high speed operation. You can make it

Further, by providing the initial phase matching circuit, the pull-in time at the pull-in can be further shortened.

Instead of the digitally controlled oscillator 53, an analog voltage controlled oscillator can be used. In this case, the control input of the voltage controlled oscillator is D / A converter
If the output value can be corrected during the A / A conversion, the characteristics can be compensated for environmental changes such as ambient temperature changes and power supply changes.

[0020]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 2 shows a 4-sample type clock recovery circuit as an embodiment of the present invention. In FIG. 2, A / D
The converter 1 samples the baseband signal (a) and
It is a circuit which performs D / D conversion and outputs as a parallel 8-bit digital signal (b), and operates as a discriminator of a demodulator.

The digital control oscillator 3 is a circuit for generating a clock (e) for giving a sampling timing to the A / D converter 1, and a sampling clock (e) [frequency fs] which is four times the symbol timing frequency f _SYM. = 4f _SYM ] is input to the A / D converter 1, and a clock (d) twice the symbol timing frequency f _SYM [frequency f = 2f _SYM ] is generated to the phase comparator 4 described later. input. The digitally controlled oscillator 3 is configured so that its modulation sensitivity characteristic (controlled frequency and phase) can be changed by control from the control circuit 6.

The edge detector 2 is a circuit which detects an edge of the digital output signal (b) of the A / D converter 1 and outputs a 1-bit edge detection signal (c). The edge detection signal (c) Are input to the phase comparator 4. Phase comparator 4
Is a circuit for comparing the phases of the clock (d) from the digitally controlled oscillator 3 and the edge detection signal (c) from the edge detector 2 and outputting a phase difference detection signal (f) corresponding to the phase difference.

The loop filter 5 is a circuit for low-pass filtering the detection signal from the phase comparator 4 and inputting it to the digitally controlled oscillator 3 as a control signal. In this embodiment, it is constructed using an up / down counter. This loop filter 5
Is configured so that its frequency characteristic can be changed under the control of the control circuit 6. In other words, lengthening or shortening the time constant (that is, widening or narrowing the band)
can do.

The operation of this embodiment circuit will be described below with reference to the time chart of FIG. In FIG. 3, (a)
Is a baseband signal in the embodiment circuit, and (b) is A /
The digital signal output from the D converter 1, (c) the edge detection signal output from the edge detector 2, (d) the 2f _SYM clock output from the digitally controlled oscillator 3, (e) the digital control A sampling timing clock of 4f _SYM output from the oscillator 3, (f) a phase difference detection signal output from the phase comparator 4, (g) a count value of the up / down counter in the loop filter 5, and (h) a loop. This is a control signal output from the filter 5 to the digitally controlled oscillator 3.

The baseband signal (a) is converted into an A / D converter 1
Then, A / D conversion is performed at the timing of the sampling timing clock (e), and a data change point is detected by the edge detector 2 from the digital output signal (b) of the A / D converter 1. The phase comparator 4 detects the phase difference between the edge detection signal (c) of the edge detector 2 and the clock (d) of the digitally controlled oscillator 3. This phase difference detection signal (c)
Will depend on the circuit configuration, but will be as shown in FIG. 3, for example. That is, the pulse is negative when the phase difference is delayed and positive when the phase difference is advanced at the timing of edge detection.

This phase difference detection signal (f) is passed through a loop filter. Output signal (h) of this loop filter 5
Is a pulse that is output when the count value (g) that changes stepwise inside the up-down counter exceeds a certain value when the loop filter 5 is configured with an up-down counter, the digital control oscillator 3 When this output signal (h) is input, changes its oscillation frequency and phase. In the example of FIG. 3, the period t which has been changed to the period t ′ for the input of the output signal (h) is changed to the period t ′, and the period t ′> t. Here, the PLL circuit operates such that the falling timing of the symbol clock (d) for phase comparison becomes an appropriate sampling timing of the eye pattern and the phase is synchronized therewith.

A signal for notifying the start timing of the frame when the burst signal is input is input to the control circuit 6, and the pull-in timing of the burst signal can be known. At the time of this pull-in, under the control of the control circuit 6, the band of the loop filter 5 is widened, and the controlled frequency and phase of the digitally controlled oscillator 3 are largely changed to converge to an appropriate sampling timing in a short time. .. Then, after a few symbols, the band of the loop filter 5 is gradually narrowed, and at the same time, the amount of change in the controlled frequency and phase of the digitally controlled oscillator 3 is reduced to suppress the jitter in the steady state.

With the circuit configuration as described above, the phase comparator 4 need only be a circuit for comparing the phases of 1-bit signals with each other, and the circuit scale can be made smaller than in the conventional case.

Various modifications are possible in carrying out the present invention. For example, in the above-described embodiment, the four-sample clock recovery circuit that samples the baseband signal at four times the symbol timing is used, but the present invention is not limited to this, and is supplied to the A / D converter 1. The frequency ratio of the sampling timing clock (e) to the phase comparison clock (D) supplied to the phase comparator 4 may be, for example, 2: 1 and may be of a two-sample type. For example, a multi-sample type with a ratio of n (n is a value of 2 or more): 1 can be used.

FIG. 4 shows another embodiment of the present invention.
This embodiment is a multi-sample type / initial phase matching type clock reproduction circuit in which the above-mentioned frequency ratio is n: 1. Differs from the previous embodiment, the output clock from the digital control oscillator 3, the clock frequency of the clock frequency to the A / D converter 1 is n · f _SYM, to the phase comparator 4 f _SYM
And that the initial phase matching circuit 8 is provided.

The initial phase matching circuit 8 receives the edge detection signal (c) from the edge detector 2, and when receiving a command from the control circuit 6 at the time of pulling in the burst signal, the digital signal at the beginning of the frame detected by the edge detector 2 is received. Output clock (e) of the digitally controlled oscillator 3 at the edge phase of
Operates to forcibly match the phase of.

FIG. 5 shows another embodiment of the present invention. This embodiment is different from the above-mentioned embodiment in that an analog type voltage controlled oscillator 13 is used instead of the digital controlled oscillator 3, and the control input to the voltage controlled oscillator 13 is changed to a loop according to this change. D / A converter 14 for converting a digital signal of the filter 5 into an analog signal
Is provided. The D / A converter 14 is a control circuit 1
By controlling from 4, it is possible to multiply the output value of the loop filter 5 by a coefficient or add a correction value, thereby changing the circuit characteristics in response to environmental changes such as ambient temperature changes and power supply voltage changes. You can automatically compensate.

[0033]

As described above, according to the present invention, it is possible to provide the clock recovery circuit suitable for receiving the burst signal in the low Eb / No state. Further, the circuit scale of such a clock recovery circuit can be reduced.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a block diagram showing a 4-sample type clock recovery circuit as an embodiment of the present invention.

FIG. 3 is a diagram showing a time chart of signals of respective parts of the embodiment circuit.

FIG. 4 is a block diagram showing a multi-sample initial phase matching type clock recovery circuit as another embodiment of the present invention.

FIG. 5 is a block diagram showing an analog voltage controlled oscillator (analog VCO) control type clock recovery circuit as another embodiment of the present invention.

FIG. 6 is a block diagram showing a conventional feedforward type clock recovery circuit.

FIG. 7 is a block diagram showing a conventional double-sampling clock recovery circuit.

[Explanation of symbols]

 1 A / D converter 2, 22 Edge detector 3, 23 Digitally controlled oscillator 4 24 Phase comparator 5, 25 Loop filter 6, 26 Control circuit 8, 27 Initial phase matching circuit 13 Analog voltage control oscillator 14 D / A Converter 21 Phase shifter 41 Kick-off circuit

Claims (4)

[Claims] 1. A digitally controlled oscillator (53) for generating a sampling timing signal applied to a data discriminator (51) for A / D converting a baseband signal, and a data change point of a digital signal output from the data discriminator. An edge detector (52) for detecting the phase difference, a phase comparator (54) for comparing the output signal of the edge detector and the phase of the output signal of the digitally controlled oscillator, and outputting an output signal according to the phase difference, A loop filter (55) for applying an output signal of the phase comparator to the digital control oscillator as a control input, and a control circuit (56) for controlling the frequency characteristic of the loop filter and / or the modulation sensitivity characteristic of the digital control oscillator. ) And the control circuit when pulling in the burst signal, the loop filter frequency characteristics and / or Clock recovery circuit configured to vary the modulation sensitivity characteristics of barrel controlled oscillator capable fast tuning. 2. The digitally controlled oscillator is configured such that a ratio of a frequency of a signal supplied to the discriminator to a frequency of a signal supplied to the phase comparator is n (n is a value of 2 or more): 1. The clock recovery circuit according to claim 1. 3. The initial phase matching circuit according to claim 1, further comprising an initial phase matching circuit forcibly adjusting the phase of the output signal of the digitally controlled oscillator to the phase of the output signal of the discriminator under the control of the control circuit during pull-in. The clock recovery circuit described in 2. 4. An analog voltage controlled oscillator is used in place of the digital controlled oscillator, and a control signal from the loop filter is converted into an analog signal by a D / A converter and then input to the voltage controlled oscillator. The clock recovery circuit according to claim 1, configured as described above.