JP2012089980A - Data determination circuit, receiver and data determination method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reliably detect an isolated pulse without enlarging the circuit scale of a data determination circuit.SOLUTION: A threshold determination section receives successive digital codes generated by oversampling an analog data signal indicating a data string of binary data, outputs a threshold signal indicating an increment value if negative digital codes come in succession and outputs a threshold signal indicating a decrement value if positive digital codes come in succession. An isolated pulse determination section adds the value indicated by the threshold signal to the digital code to generate a corrected digital code, and uses successive corrected digital codes to detect an isolated pulse. A binary determination section uses signs of the successive digital codes to determine the logic of the binary data. A data selection section outputs the logic of the isolated pulse as the logic of the binary data when the isolated pulse is detected, and outputs the logic of the binary data determined by the binary determination section when the isolated pulse is not detected.

Description

  The present invention relates to a data determination circuit for determining the logic of data and a receiver having the data determination circuit.

  In general, when a data string is transmitted through a transmission line, the waveform of an analog data signal representing the data string is distorted and the aperture of the eye pattern is reduced. If the opening degree of the eye pattern is small, the data logic may be erroneously determined. The opening degree of the eye pattern is obtained by changing a threshold value for determining the logic of data (see, for example, Patent Document 1). In order to prevent erroneous determination of the logic of data, a method of increasing the eye pattern opening degree by controlling the amplitude of data according to the tendency of the pattern of the data string is known (for example, patents). Reference 2). Also, a technique is known in which a digital code is generated by over-sampling an analog data signal, and the logic of the original data is determined based on a change pattern of the sign of the digital code (see, for example, Patent Document 3). ).

JP-A-8-181638 JP 2005-130172 A JP 2010-130366 A

  For example, when logic 1 data appears in a data string followed by logic 0 data, the aperture of the eye pattern decreases due to inter-symbol interference (ISI), etc., and logic 1 (isolated pulse) is determined. It becomes difficult to do. In order to detect an isolated pulse with certainty, it is necessary to add an equivalent circuit or the like for reducing intersymbol interference, which increases the circuit scale of the data determination circuit.

  In one embodiment of the present invention, the data determination circuit sequentially receives a digital code generated by over-sampling an analog data signal representing a data string of binary data, and is a negative digital corresponding to logic 0 of the binary data. When a code continues, a threshold signal indicating an increase value is output. When a positive digital code corresponding to logic 1 of binary data continues, a threshold signal indicating a decrease value is output. A threshold value determination unit that outputs a threshold signal indicating zero when the digital code of Randomly appears, and generates a correction digital code by adding a value indicated by the threshold signal to the digital code, among a plurality of consecutive correction digital codes, When the sign of the center correction digital code is different from the sign of other correction digital codes, the center correction digital code is detected as an isolated pulse. An isolated pulse determination unit, a binary determination unit that obtains the logic of binary data based on the transition of the sign of a continuous digital code, and an isolated pulse supplied from the isolated pulse determination unit when an isolated pulse is detected And a data selection unit that outputs the logic of the binary data obtained by the binary determination unit when no isolated pulse is detected.

  An isolated pulse can be reliably detected by increasing or decreasing the value of the digital code when the code of the digital code is continuous. Thereby, an isolated pulse can be detected with a simple circuit, and the circuit scale of the data determination circuit can be reduced.

2 illustrates an example of a data determination circuit according to an embodiment. The example of the data determination circuit in another embodiment is shown. The relationship between the binary data represented by the analog data signal and the digital code is shown. The example of the threshold value determination part shown in FIG. 2 is shown. The example of the isolated pulse determination part shown in FIG. 2 is shown. 6 shows an example of the pulse detector shown in FIG. 6 shows an example of the operation of the isolated pulse determination unit shown in FIG. 6 shows another example of the operation of the isolated pulse determination unit shown in FIG. The example of the phase detection part shown in FIG. 2 is shown. 10 illustrates an example of the sub-phase detector illustrated in FIG. 9. 11 shows an example of a phase detected by the sub phase detector shown in FIG. 11 shows an example of the operation of the sub-phase detector shown in FIG. The example of the phase filter shown in FIG. 2 is shown. The example of the binary determination part shown in FIG. 2 is shown. 15 illustrates an example of the operation of the binary determination unit illustrated in FIG. 14. The example of the data selection part shown in FIG. 2 is shown. An example of a simulation waveform of an eye pattern of an analog data signal before a digital code is sampled is shown. 3 shows an example of a jitter tolerance simulation waveform of the data determination circuit shown in FIG. The example of the threshold value determination part in another embodiment is shown. The example of the threshold value determination part in another embodiment is shown. The example of the threshold value determination part in another embodiment is shown. The example of the data determination circuit in another embodiment is shown. The example of the data determination circuit in another embodiment is shown. The example of the isolated pulse determination part shown in FIG. 23 is shown. The example of the pulse detector shown in FIG. 24 is shown. 24 shows an example of the operation of the data determination circuit shown in FIG. The example of operation | movement of another isolated pulse determination part is shown. The example of the receiver in which the data determination circuit mentioned above is mounted is shown.

  Hereinafter, embodiments will be described with reference to the drawings.

  FIG. 1 shows an example of a data determination circuit DDC in one embodiment. The data determination circuit DDC includes a threshold determination unit 1, an isolated pulse determination unit 2, a binary determination unit 3, and a data selection unit 4. The m-bit (for example, 5 bits) digital code Di supplied to the threshold value determination unit 1, the isolated pulse determination unit 2, and the binary determination unit 3 is obtained by over-sampling an analog data signal representing a binary data string. Generated and represents discrete digital values. The data string is transmitted from the transmitter using an NRZ (Non-Return to Zero) code. For example, the sampling rate of the data signal Di is twice the data rate of the binary data string. The data determination circuit DDC determines the logic of the data string using a blind CDR (Clock and Data Recovery) technique. For example, the digital code Di is treated as a negative value when the most significant bit is “0”, and treated as a positive value when the most significant bit is “1”. The negative digital code Di corresponds to the logic 0 of the binary data, and the positive digital code Di corresponds to the logic 1 of the binary data.

  The threshold determination unit 1 sequentially receives the digital code Di, and outputs a threshold signal VTH indicating an increase value when the negative digital code Di continues. The threshold determination unit 1 outputs a threshold signal VTH indicating a decrease value when positive digital codes are continuous. The threshold determination unit 1 outputs a threshold signal VTH indicating zero when a negative digital code and a positive digital code appear randomly.

  The isolated pulse determination unit 2 includes an adder 2a and a pulse detector 2b. The adder 2a adds the value indicated by the threshold signal VTH to the digital code Di to generate a corrected digital code CDi. When the threshold signal VTH indicates an increase value, the value of the correction digital code CDi is larger than the value of the digital code Di. When the threshold signal VTH indicates a decrease value, the value of the correction digital code CDi is smaller than the value of the digital code Di. When the threshold signal VTH indicates zero, the value of the correction digital code CDi is equal to the value of the digital code Di.

  The pulse detector 2b, for example, corrects the central correction when the sign of the central correction digital code CDi2 is different from the sign of the other correction digital codes CDi1, CDi3 among the three consecutive correction digital codes CDi1, CDi2, CDi3. The digital code CDi2 is detected as an isolated pulse, and an isolated pulse detection signal PLS is output. An isolated pulse can be easily detected by comparing the most significant bits of the correction digital codes CDi1, CDi2, and CDi3.

  For example, the binary determination unit 3 obtains the logic of the binary data indicated by the analog data signal based on the transition of the sign of three consecutive digital codes Di, and outputs it as selection data SELD. When the isolated pulse determination unit 2 outputs the isolated pulse detection signal PLS, the data selection unit 4 determines the logic of the detected isolated pulse as the logic of binary data, and outputs it as output data DOUT. When the isolated pulse determination unit 2 does not output the isolated pulse detection signal PLS, that is, when no isolated pulse is detected, the data selection unit 4 changes the logic of the selection data SELD obtained by the binary determination unit 3 to the binary data logic. And output as output data DOUT.

  For example, when logic 1 data appears in a data string followed by logic 0 data (logic 1 isolated pulse), the value of the digital code Di indicating logic 1 data is a digital indicating a data string in which logic 1 continues. It tends to be smaller than the value of the code Di. Similarly, when logic 0 data appears in a data string followed by logic 1 data (logic 0 isolated pulse), the value of the digital code Di indicating the logic 0 data indicates a data string in which logic 0 continues. It tends to be larger than the value of the digital code Di. At this time, the opening degree of the eye pattern becomes small, and the logic of the data string is easily detected erroneously.

  In this embodiment, by adding an increase value or a decrease value to the value of the digital code Di to generate the corrected digital code CDi, the apparent aperture of the eye pattern can be increased, and an isolated pulse can be reliably detected by the corrected digital code CDi. Can be detected. For example, when the digital code Di is represented by 5 bits (32 types), the increase value is “+3” and the decrease value is “−3”.

  As described above, even when the aperture of the eye pattern is reduced due to the continuation of the code of the digital code Di, the isolated pulse can be reliably detected with a simple circuit by increasing or decreasing the value of the digital code Di. , Mistakes in data logic judgment can be reduced. For this reason, an equivalent circuit for reducing the intersymbol interference of the analog data signal and the digital code Di is not required, or a complicated equivalent circuit is not required. As a result, the circuit scale of the data determination circuit DDC and the circuit scale of a receiver or the like on which the data determination circuit DDC is mounted can be reduced, and power consumption can be reduced.

  FIG. 2 shows an example of the data determination circuit DDC in another embodiment. The same elements as those described in the above-described embodiment are denoted by the same reference numerals, and detailed description thereof will be omitted.

  The data determination circuit DDC of this embodiment includes a threshold determination unit 10, an isolated pulse determination unit 20, a phase detection unit 30, a binary determination unit 40, a determination timing generation unit 50, and a data selection unit 60. The m-bit (for example, 5 bits) digital code Di supplied to the threshold value determination unit 10, the isolated pulse determination unit 20, the phase detection unit 30, and the binary determination unit 40 is an analog data signal representing a binary data string. Generated by over-sampling and shows discrete digital values. For example, the digital code Di is generated by converting an analog data signal into a digital value by an AD converter.

  For example, the sampling rate of the digital code Di is twice the data rate of the binary data string. In other words, when the interval of binary data represented by the analog data signal is 1 UI (unit interval), the interval of the digital code Di is 0.5 UI. The relationship between the binary data represented by the analog data signal and the digital code Di is shown in FIG. The digital code Di is treated as a negative value when the most significant bit is “0”, and treated as a positive value when the most significant bit is “1”.

  The threshold determination unit 10 outputs a threshold signal VTH for increasing the digital code Di when continuously receiving the predetermined number of negative digital codes Di, and continuously receives the predetermined number of positive digital codes Di. Sometimes, a threshold signal VTH for decreasing the digital code Di is output. An example of the threshold determination unit 10 is shown in FIG. In the following description, the value of the threshold signal VTH is also referred to as a threshold value VTH. In the digital code Di, when the same code continues, the isolated pulse can be easily determined by increasing or decreasing the value of the digital code Di.

  Here, the isolated pulse indicates one positive digital code Di appearing in the continuous negative digital code Di or one negative digital code Di appearing in the continuous positive digital code Di. When a negative value is represented by “0” and a positive value is represented by “1”, for example, “1” included in the digital code Di column “01000”, “00100”, “00010” and the digital code Di “0” included in the columns “10111”, “11011”, and “11101” is an isolated pulse.

  The isolated pulse determination unit 20 increases or decreases the digital code Di according to the threshold value VTH, and determines whether the plurality of digital codes Di that are supplied in order are positive or negative. The isolated pulse determination unit 20 outputs one of the isolated pulse detection signals FPLS, MPLS, and BPLS according to the position of the isolated pulse when the isolated pulse is included in the plurality of digital codes Di determined to be positive or negative. The pulse median values FPCV, MPCV, and BPCV indicating the sign of are output. The pulse median values FPCV, MPCV, and BPCV are output corresponding to the isolated pulse detection signals FPLS, MPLS, and BPLS, respectively. An example of the isolated pulse determination unit 20 is shown in FIGS.

  The phase detection unit 30 receives the digital code Di, and when the sign of two adjacent digital codes Di changes from positive to negative or from negative to positive, the position (phase) where the sign of the line segment connecting the two digital codes Di changes. ) And output as a cross position signal PINST. In the following description, the position (phase) indicated by the cross position signal PINST is also referred to as a cross position PINST. An example of the cross position PINST is shown in FIG. Examples of the phase detector 30 are shown in FIGS.

  The determination timing generation unit 50 includes a phase filter 510 and an adder 520. The phase filter 510 calculates the average of the cross positions PINST output in order from the phase detection unit 30, and outputs the average as the average cross position signal PAV. In the following description, the average value indicated by the average cross position signal PAV is also referred to as an average cross position PAV. The average cross position PAV indicates substantially the middle (boundary) of the position indicating two consecutive binary data (“0”, “1” or “1”, “0”). An example of the phase filter 510 is shown in FIG.

  Adder 520 adds 0.5 UI to average cross position PAV indicating the boundary of the binary data, and outputs estimated position signal PPICK indicating the center position (estimated value) of the binary data represented by the analog data signal. The estimated position signal PPICK indicates the center position of the binary data represented by the analog data signal, and indicates the timing for determining the logic of the binary data. In the following description, the center position of the data indicated by the estimated position signal PPICK is also referred to as an estimated position PPICK. An example of the estimated position PPICK is shown in FIG.

  The binary determination unit 40 receives three digital codes Di included in the range of 1 UI, and for each UI based on the cross position signal PINST from the phase detection unit 30 and the estimated position signal PPICK from the determination timing generation unit 50. The logic of the binary data represented by the analog data signal is determined. The binary determination unit 40 outputs the determined binary data logic as selection data SELD. An example of the binary determination unit 40 is shown in FIG.

  When the isolated pulse detection signals FPLS, MPLS, and BPLS are not output, the data selection unit 60 selects the selection data SELD from the binary determination unit 40 and outputs it as output data DOUT. When any one of the isolated pulse detection signals FPLS, MPLS, and BPLS is output, the data selection unit 60 selects the corresponding pulse median value (any one of FPCV, MPCV, and BPCV), and outputs the selected data as output data DOUT. . An example of the data selection unit 60 is shown in FIG.

  FIG. 3 shows the relationship between the binary data represented by the analog data signal and the digital code Di. The analog data signal is indicated by a thick curve, and the digital code Di is indicated by a white circle. As described above, the sampling rate of the data signal Di is twice the data rate of the binary data string. For this reason, when the interval of binary data represented by the analog data signal is 1 UI, the interval of the digital code Di is 0.5 UI. Three digital codes Di are included in the range of 1 UI. In other words, the digital code Di at the boundary of 1 UI is shared by two adjacent UIs.

  Although not particularly limited, the data signal Di has 5 bits to indicate the voltage level of the analog data signal in 32 ways. The binary numbers on the vertical axis in FIG. 3 indicate only even numbers out of 32 values. The digital code Di is represented by 16 positive values whose most significant bit is logic 0 and 16 negative values whose most significant bit is logic 1. In the following description, the positive digital code Di may be represented by “0” and the negative digital code Di may be represented by “1”.

  The cross position signal PINST generated by the phase detection unit 30 illustrated in FIG. 2 is, for example, 3 bits, and the cross position PINST indicates one of the phase regions obtained by dividing 1 UI into 8 equal parts. The average cross position signal PAV indicating the average of the cross position PINST is 3 bits as in the cross position PINST. The estimated position PPICK is obtained by adding 0.5 UI (“100” in binary) to the cross position PINST. The estimated position signal PPICK is 3 bits, for example, and represents the position from the start point of each 1 UI in units of 1/8 UI.

  The data determination circuit DDC obtains a digital code Di indicating the logic of the binary data indicated by the analog data signal from the three digital codes Di included in each 1 UI (FIG. 3A). Then, the data determination circuit DDC determines the most significant bit of the obtained digital code Di as the logic of the binary data indicated by the analog data signal, and outputs it as output data DOUT (FIG. 3B). FIG. 3 shows an example in which the threshold value VTH is set to “0”, and the value of the most significant bit of the digital code Di is used as it is for logical determination.

  FIG. 4 illustrates an example of the threshold determination unit 10 illustrated in FIG. The threshold determination unit 10 includes a code determination unit SIGN, n holding units FF, and a threshold control unit 110. “N” is an integer of 2 or more. The threshold control unit 110 includes a NOR circuit, an AND circuit, and a selector 120. The sign determination unit SIGN obtains the sign of the digital code Di and outputs it as the most significant bit MSB. The most significant bit MSB indicates the sign of the digital code Di, and is negative when “0” and positive when “1”. For this reason, the code determination unit SIGN may output the most significant bit MSB of the digital code Di to the holding unit FF. The most significant bits MSB output from the code determination unit SIGN are sequentially held in the holding units FF connected in series. For example, the holding unit FF is formed by a flip-flop circuit. The code determination unit SIGN and the holding unit FF may be formed outside the threshold determination unit 10.

  The NOR circuit activates the selection signal SEL0 to logic 1 when the outputs of the n holding units FF are all “0”. The activation of the selection signal SEL0 indicates that the signs of n consecutive digital codes Di are all negative. The AND circuit activates the selection signal SEL1 to logic 1 when the outputs of the n holding units FF are all “1”. The activation of the selection signal SEL1 indicates that the signs of n consecutive digital codes Di are all positive. When the outputs of the n holding units FF include both “1” and “0”, the selection signals SEL0 and SEL1 are both deactivated to logic 0.

  The selector 120 receives the logical value of the selection signal SEL1 as upper bits, receives the logical value of the selection signal SEL0 as lower bits, and outputs the value received at the input terminal corresponding to the received 2-bit value as the threshold value VTH. Note that the selection signals SEL0 and SEL1 are not activated, so the input terminal 11 is not selected.

  For example, when the selection signal SEL0 is activated, the input terminal 01 is selected, and the value “+ VTH” is output as the threshold value VTH. When the selection signal SEL1 is activated, the input terminal 10 is selected, and the value “−VTH” is output as the threshold value VTH. When both the selection signals SEL0 and SEL1 are inactivated, the input terminal 00 is selected and a threshold value VTH of “0” is output. In this example, the threshold signal VTH is 3 bits. As will be described later, the value “+ VTH” is an increase value for generating the corrected digital code CDi by increasing the digital code Di, for example, “+3”. As will be described later, the value “−VTH” is a decrease value for decreasing the digital code Di to generate the corrected digital code CDi, and is “−3”, for example.

  FIG. 5 shows an example of the isolated pulse determination unit 20 shown in FIG. The isolated pulse determination unit 20 includes an adder 210, a sign determination unit SIGN, five holding units FF, and three pulse detectors 220, 230, and 240. For example, the holding unit FF is formed by a flip-flop circuit.

  The adder 210 adds the threshold value VTH to the digital code Di to generate a corrected digital code CDi, and outputs the generated corrected digital code CDi to the code determination unit SIGN. Here, the threshold value VTH added to the digital code Di is generated using a plurality of digital codes Di generated before the digital code Di received by the adder 210.

  The sign determination unit SIGN outputs the sign of the corrected digital code CDi. The code output from the code determination unit SIGN is sequentially held in the holding unit FF connected in series, and is sequentially output as the code bit values SB1, SB2, SB3, SB4, and SB5 of the correction digital code CDi.

  The pulse detector 220 receives the sign bit values SB1 to SB3, and activates the isolated pulse detection signal FPLS to logic 1 when the sign bit values SB1 to SB3 include isolated pulses ("010" or "101"). When the sign bit values SB1-SB3 are not isolated pulses, the isolated pulse detection signal FPLS is held at logic zero. The pulse detector 230 receives the sign bit values SB2-SB4 and activates the isolated pulse detection signal MPLS to logic 1 when the sign bit values SB2-SB4 are isolated pulses. When the sign bit values SB2-SB4 are not isolated pulses, the isolated pulse detection signal MPLS is held at logic 0. The pulse detector 240 receives the sign bit values SB3-SB5, and activates the isolated pulse detection signal BPLS to logic 1 when the sign bit values SB3-SB5 are isolated pulses. When the sign bit values SB3 to SB5 are not isolated pulses, the isolated pulse detection signal BPLS is held at logic 0.

  The sign bit values SB2, SB3, and SB4 are output as pulse median values FPCV, MPCV, and BPCV indicating the median value of isolated pulses. Examples of pulse detectors 220, 230, and 240 are shown in FIG. The operation of the isolated pulse determination unit 20 is shown in FIGS.

  FIG. 6 shows an example of the pulse detectors 220, 230, and 240 shown in FIG. The pulse detector 220 includes two AND circuits 221 and 222 and an OR circuit 223 that receives the outputs of the AND circuits 221 and 222. The AND circuit 221 receives the inverted logic of the sign bit values SB1 and SB3 and the sign bit value SB2, and detects an isolated pulse pattern “010”. The AND circuit 222 receives the sign bit values SB1 and SB3 and the inverted logic of the sign bit value SB2 and detects the isolated pulse pattern “101”. The OR circuit 224 activates the isolated pulse detection signal FPLS to logic 1 when the sign bit value MSB2 is an isolated pulse.

  The pulse detector 230 includes two AND circuits 231 and 232 and an OR circuit 233 that receives the outputs of the AND circuits 231 and 232. The pulse detector 240 includes two AND circuits 241 and 242 and an OR circuit 243 that receives the outputs of the AND circuits 241 and 242. The pulse detectors 230 and 240 are the same circuit as the pulse detector 220 except that the input signal and the output signal are different.

  FIG. 7 shows an example of the operation of the isolated pulse determination unit 20 shown in FIG. FIG. 7 shows an operation when the threshold value VTH is “0”. A thick solid line indicates an analog data signal, and a white circle indicates a digital code Di. Actually, the waveform of the analog data signal is a curve, but here, it is represented by a straight line for the sake of brevity.

  When the threshold value VTH is “0”, the adder 210 shown in FIG. 5 outputs the digital code Di as the corrected digital code CDi. For this reason, the sign bit values SB1-SB5 are equal to the value of the most significant bit of the digital code Di. Each sign bit value SB1-SB5 indicates “0” when the digital code Di is negative (−), and indicates “1” when the digital code Di is positive (+). When the data determination circuit DDC determines the logic of the binary data represented in the analog data signal based on the three digital codes Di2, Di3, Di4, the isolated pulse determination unit 20 includes the preceding and following digital codes Di1, Di5. The isolated pulse is detected using the five code bit values SB1-SB5 corresponding to the digital codes D1-Di5.

  7A and 7D, the isolated pulse determination unit 20 detects that the digital code Di2 corresponding to the sign bit value SB2 is an isolated pulse, and sets the isolated pulse detection signal FPLS to logic 1. 7B and 7E, the isolated pulse determination unit 20 detects that the digital code Di3 corresponding to the sign bit value SB3 is an isolated pulse, and sets the isolated pulse detection signal MPLS to logic 1. 7C and 7F, the isolated pulse determination unit 20 detects that the digital code Di4 corresponding to the sign bit value SB4 is an isolated pulse, and sets the isolated pulse detection signal BPLS to logic 1.

  In the example shown in FIG. 7, since the aperture of the eye pattern is 0.5 UI or more, an isolated pulse is reliably detected. For example, the opening degree of the eye pattern is represented by a period in which the sign of the analog data signal is positive or a period in which the sign of the analog data signal is negative. In FIG. 7, the opening degree of the eye pattern is represented by the length of the base of the triangle formed by the zero point (0) that is the boundary between the negative value and the positive value and the waveform of the analog data signal.

  FIG. 8 shows another example of the operation of the isolated pulse determination unit 20 shown in FIG. Detailed descriptions of the same operations as those in FIG. 7 are omitted. FIG. 8 shows an operation when the threshold value VTH is “−3” or “+3”. A thick solid line indicates an analog data signal, and a white circle indicates a digital code Di. A black circle indicates a corrected digital code CDi obtained by adding a threshold value VTH to the digital code CDi, and a thick broken line indicates an apparent analog data signal corresponding to the corrected digital code CDi.

  For example, when the aperture of the eye pattern becomes smaller than 0.5 UI due to inter-symbol interference (ISI), the isolated pulse determining unit 20 cannot detect the isolated pulse. In order to prevent this, the threshold value determination unit 10 shown in FIG. 4 changes the threshold value VTH in order to increase the opening degree of the eye pattern when a predetermined number of digital codes Di having the same code are generated continuously. .

  When the negative digital code Di continues, the threshold value VTH is set to “+3”. The adder 210 shown in FIG. 5 adds “+3” to the digital code Di to generate a corrected digital code CDi. As a result, as shown in FIGS. 8A, 8B, and 8C, the positive correction digital code CDi2 (or CDi3, CDi4) is generated from the negative digital code Di2 (or Di3, DI4). The apparent opening degree of the eye pattern is increased. Then, isolated pulses can be detected as in FIGS. 7A, 7B, and 7C.

  On the other hand, when the positive digital code Di continues, the value of the threshold value VTH is set to “−3”. The adder 210 adds “−3” to the digital code Di to generate a corrected digital code CDi. As a result, as shown in FIGS. 8D, 8E, and 8F, the negative correction digital code CDi2 (or CDi3, CDi4) is generated from the positive digital code Di2 (or Di3, DI4). The opening degree of the eye pattern is increased. Then, isolated pulses can be detected as in FIGS. 7D, 7E, and 7F.

  FIG. 9 shows an example of the phase detector 30 shown in FIG. The phase detector 30 includes three holding units FF, two sub phase detectors 310 and 320, an adder 330, and a selector 340. For example, the holding unit FF is formed by a flip-flop circuit. The holding unit FF is connected in series, holds the 5-bit digital code Di in order, and outputs the digital codes DiA, DiB, and DiC.

  The sub-phase detector 310 outputs a transition signal TRAN1 when the codes of the digital codes DiA and DiB are different, obtains the phase of the zero cross point where the line segment connecting the digital codes DiA and DiB and the zero point intersect, and the obtained phase Is output as the phase signal U1. Similarly, the sub-phase detector 320 outputs the transition signal TRAN2 when the codes of the digital codes DiB and DiC are different, and obtains the phase of the zero cross point where the line segment connecting the digital codes DiB and DiC and the zero point intersect, The obtained phase is output as the phase signal U2.

  The phase signal U1 indicates a relative phase based on the position of the digital code DiA having the earliest time among the digital codes DiA, DiB, and DiC included in one UI. The phase signal U2 indicates a relative phase based on the position of the digital code DiB located at the center in 1 UI.

  For example, the phase signals U1 and U2 are 3 bits and indicate which of the four areas obtained by dividing 0.5 UI into four equal parts includes the zero cross point. When each of the phase signals U1 and U2 is “000” in binary, the zero cross point is between 0 UI and 0.125 UI. When each of the phase signals U1 and U2 is “001” in binary, the zero cross point is between 0.125 UI and 0.25 UI. When each of the phase signals U1 and U2 is “010” in binary, the zero cross point is between 0.25 UI and 0.375 UI. When each of the phase signals U1 and U2 is “011” in binary, the zero cross point is between 0.375 UI and 0.5 UI.

  The adder 330 adds 0.5 UI (“100” in binary) to the phase signal U2 and outputs the result as the phase signal U20. Specifically, the phase signal U20 is one of binary numbers “100”, “101”, “110”, and “111”. When the phase signal U20 is based on the position of the digital code DiA that is the starting point of 1 UI, the zero cross point is between 0.5 UI and 0.625 UI, between 0.625 UI and 0.75 UI, and from 0.75 UI. Indicates between 0.875 UI and 0.875 UI to 1 UI. That is, the phase signal U20 output from the adder 330 indicates a relative phase with respect to the position of the digital code DiA.

  The selector SEL outputs the phase signal U1 as the cross position signal PINST when receiving the transition signal TRAN1. When the selector SEL receives the transition signal TRAN2, the selector SEL outputs the phase signal U2 as the cross position signal PINST.

  FIG. 10 shows an example of the sub-phase detector 310 shown in FIG. The sub phase detector 310 includes a combiner 312 and a cross position detector 314. 9 receives digital codes DiB and DiC instead of digital codes DiA and DiB, and outputs phase signal U2 and transition signal TRAN2 instead of phase signal U1 and transition signal TRAN1. Except for this, it is the same circuit as the sub phase detector 310.

  The combiner 312 includes multipliers MUL1 and MUL2 and adder / subtracters ADD1, ADD2, ADD3, and ADD4. In FIG. 10, the values of the digital codes DiA and DiB are “A” and “B” for easy understanding. The multiplier MUL1 multiplies the value of the digital code DiA by 4 and outputs “4A”. The multiplier MUL2 multiplies the value of the digital code DiB by 4 and outputs “4B”.

  The adder / subtractor ADD1 subtracts the digital code DiB from the digital code DiA and outputs "A-B". The adder / subtractor ADD2 subtracts “A−B” from the value “4A” and outputs “3A + B”. The adder / subtractor ADD3 adds the value “B” to the value “A” and outputs “A + B”. The adder / subtractor ADD4 adds the value “4B” to the value “A−B” and outputs “A + 3B”.

  The cross position detector 314 generates the phase signal U1 and the transition signal TRAN1 based on the values output from the combiner 312. The operation of the cross position detector 314 is shown in FIGS.

  FIG. 11 shows an example of a phase detected by the sub phase detector 310 shown in FIG. “A” and “B” with circles in the drawing are values of the digital codes DiA and DiB shown in FIG. FIG. 11 shows the operation of the sub-phase detector 320 by setting “A” and “B” as the values of the digital codes DiB and DiC supplied to the sub-phase detector 320 shown in FIG.

  The value of 0.25 UI in the line segment connecting “A” and “B” is an average value “(A + B) / 2” of values “A” and “B”. The value of 0.125 UI in the line segment connecting “A” and “B” is the average value “(3A + B) / 2” of the values “A” and “(A + B) / 2”. The value of 0.375 UI in the line segment connecting “A” and “B” is the value “(A + B) / 2” and the average value of “B” (A + 3B) / 2 ”. The values “(A + B) / 2”, “(3A + B) / 2”, and “(A + 3B) / 2” are values “(A + B)”, “3A + B”, “A + 3B” output from the combiner 312 shown in FIG. "Is shifted by 1 bit lower side, respectively.

  Based on the above, when the value “A” is negative, the value “B” is positive, and the value “(3A + B) / 2” is positive, the cross position detector 314 shown in FIG. It is determined that it is between 0.125 UI, and the phase signal U1 is set to “000” in binary (FIG. 11A). When the value “A” is negative, the value “B” is positive, the value “(3A + B) / 2” is negative, and the value “(A + B) / 2” is positive, It is determined that it is between 0.125 UI and 0.25 UI, and the phase signal U1 is set to “001” in binary (FIG. 11B).

  The cross position detector 314 has a zero cross point when the value “A” is negative, the value “B” is positive, the value “(A + B) / 2” is negative, and the value “(A + 3B) / 2” is positive. Is determined to be between 0.25 UI and 0.375 UI, and the phase signal U1 is set to “010” in binary (FIG. 11C). The cross position detector 314 indicates that when the value “A” is negative, the value “B” is positive, and the value “(A + 3B) / 2” is negative, the zero cross point is between 0.375 UI and 0.5 UI. The phase signal U1 is set to “011” in binary (FIG. 11 (d)).

  The cross position detector 314 determines that the zero cross point is between 0 UI and 0.125 UI when the value “A” is positive, the value “B” is negative, and the value “(3A + B) / 2” is negative. The phase signal U1 is set to “000” in binary (FIG. 11 (e)). When the value “A” is positive, the value “B” is negative, the value “(3A + B) / 2” is positive, and the value “(A + B) / 2” is negative, It is determined that it is between 0.125 UI and 0.25 UI, and the phase signal U1 is set to “001” in binary (FIG. 11 (f)).

  The cross position detector 314 detects the zero cross point when the value “A” is positive, the value “B” is negative, the value “(A + B) / 2” is positive, and the value “(A + 3B) / 2” is negative. Is determined to be between 0.25 UI and 0.375 UI, and the phase signal U1 is set to “010” in binary (FIG. 11 (g)). The cross position detector 314 indicates that when the value “A” is positive, the value “B” is negative, and the value “(A + 3B) / 2” is positive, the zero cross point is between 0.375 UI and 0.5 UI. Then, the phase signal U1 is set to “011” in binary (FIG. 11 (h)).

  FIG. 12 shows an example of the operation of the sub-phase detector 310 shown in FIG. The operation when the zero-cross point exists, that is, the operation when the codes of the digital codes DiA and DiB are different is the same as described in FIG. The sub-phase detector 310 activates the transition signal TRAN1 to logic 1 together with the output of the phase signal U1 when a zero-cross point exists.

  When the codes of the digital codes DiA and DiB are the same, there is no zero cross point. For this reason, the sub-phase detector 310 deactivates the transition signal TRAN1 to logic 0. When the transition signal TRAN1 is logic 0, the value of the phase signal U1 is invalidated. The operation shown in FIG. 12 is performed by replacing the digital codes DiA and DiB, the phase signal U1 and the transition signal TRAN1 with the digital codes DiB and DiC, the phase signal U2 and the transition signal TRAN2, so that the sub-phase detector 320 shown in FIG. The operation is shown.

  FIG. 13 shows an example of the phase filter 510 shown in FIG. The phase filter 510 includes amplifiers 511 and 512 and integrators 514 and 516. The amplifier 511 amplifies the value of the cross position signal PINST with a gain K1 and outputs the amplified signal. The amplifier 512 amplifies the output of the amplifier 511 with a gain K2 and outputs it.

  The integrator 514 integrates the output of the amplifier 512 and outputs the integration result to the integrator 516. The integrator 516 integrates the output of the amplifier 511 and the output of the integrator 516, and outputs the integration result as an average cross position signal PAV. The output of each integrator 514, 516 is fed back to itself. From the above, the phase filter 510 generates an average cross position PAV obtained by averaging the values of the cross positions PINST.

  FIG. 14 illustrates an example of the binary determination unit 40 illustrated in FIG. The binary determination unit 40 includes a code determination unit SIGN, three holding units FF, exclusive OR circuits 410, 412, and 414, comparators 420 and 422, an AND circuit 430, an OR circuit 432, and selectors 440, 442, and 444. is doing. For example, the holding unit FF is formed by a flip-flop circuit.

  The sign determination unit SIGN determines the sign of the digital code Di and outputs it as a sign bit value MSB. Since the sign of the digital code Di is represented by the most significant bit, for example, the sign determination unit SIGN may output the most significant bit MSB of the digital code Di.

The holding unit FF sequentially holds the code MSB supplied from the code determination unit SIGN, and outputs the code MSB as code bit values MSB2, MSB3, and MSB4. The sign bit values MSB2, MSB3, and MSB4 indicate the signs of the three digital codes Di2, Di3, and Di4 shown in FIGS. The binary determination unit 40 determines the logic of the binary data indicated by the analog data signal in 1 UI.
The exclusive OR circuit 410 outputs logic 0 when the sign bit values MSB2 and MSB3 are the same, that is, when the signs of the digital codes Di2 and Di3 are the same. The exclusive OR circuit 410 outputs logic 1 when the sign bit values MSB2 and MSB3 are different, that is, when the codes of the digital codes Di2 and Di3 are different. The exclusive OR circuit 412 outputs logic 0 when the sign bit values MSB3 and MSB4 are the same, that is, when the signs of the digital codes Di3 and Di4 are the same. The exclusive OR circuit 412 outputs logic 1 when the sign bit values MSB3 and MSB4 are different, that is, when the signs of the digital codes Di3 and Di4 are different.

  The exclusive OR circuit 414 outputs a logic 0 when the logics output from the exclusive OR circuits 410 and 412 are the same. In other words, the exclusive OR circuit 414 outputs logic 0 when the codes of the digital codes Di2, Di3, and Di4 are the same, or when the codes of the digital code Di3 are different from the codes of the digital codes Di2 and Di4. The exclusive OR circuit 414 outputs a logic 1 when the logics output from the exclusive OR circuits 410 and 412 are different. That is, the exclusive OR circuit 414 outputs logic 1 when the code of the digital code Di2 is different from the code of the digital code Di3 or Di4, or when the code of the digital code Di4 is different from the code of the digital code Di2 or Di4. To do.

  The comparator 420 outputs a logic 1 when the value of the cross position signal PINST is larger than the value of the estimated position signal PPICK, and outputs a logic 0 when the value of the cross position signal PINST is smaller than the value of the estimated position signal PPICK. The comparator 422 outputs a logic 1 when the value of the estimated position signal PPICK is smaller than 0.5 UI (binary “100”), and outputs a logic 0 when the value of the estimated position signal PPICK is larger than 0.5 UI. Output.

  AND circuit 430 outputs a logic 1 to select bit value MSB1 by selector 440 when the output of exclusive OR circuit 414 and the output of comparator 420 are both logic 1. The AND circuit 430 outputs a logic 0 to select the bit value MSB2 by the selector 440 when either the output of the exclusive OR circuit 414 or the output of the comparator 420 is a logic 0.

  The OR circuit 432 outputs logic 1 to select the bit value MSB2 by the selector 442 when the output of the exclusive OR circuit 414 is logic 0 or the output of the comparator 420 is logic 1. The OR circuit 432 outputs logic 0 to select the bit value MSB3 by the selector 442 when the output of the exclusive OR circuit 414 is logic 1 and the output of the comparator 420 is logic 0.

  The selector 440 selects one of the sign bit values MSB 2 and MSB 3 according to the logic output from the AND circuit 430 and outputs the selected bit value to the selector 444. The selector 442 selects one of the sign bit values MSB 3 and MSB 4 according to the logic output from the OR circuit 432 and outputs the selected bit value to the selector 444.

  The selector 444 outputs the code bit value MSB2 or MSB3 supplied via the selector 440 as selection data SELD when the output of the comparator 420 is logic 1, that is, when the estimated position PPICK is smaller than 0.5 UI. . The selector 444 outputs the sign bit value MSB3 or MSB4 supplied via the selector 442 as the selection data SELD when the output of the comparator 420 is logic 0, that is, when the estimated position PPICK is larger than 0.5 UI. .

  FIG. 15 illustrates an example of the operation of the binary determination unit 40 illustrated in FIG. In FIG. 15A, the cross position PINST is smaller than 0.5 UI, and the sign bit value MSB2 is different from the sign bit values MSB3 and MSB4. At this time, the exclusive OR circuit 414 shown in FIG. When the estimated position PPICK is before the cross position PINST, the sign bit value MSB2 is output as the selection data SELD (FIG. 15 (a)). When the estimated position PPICK is behind the cross position PINST and is smaller than 0.5 UI, the sign bit value MSB3 is output as the selection data SELD (FIG. 15B). When the estimated position PPICK is larger than 0.5 UI, the sign bit value MSB4 is output as the selection data SELD (FIG. 15 (c)).

  In FIG. 15B, the estimated position PPICK is larger than 0.5 UI, and the sign bit value MSB4 is different from the sign bit values MSB2 and MSB3. At this time, the exclusive OR circuit 414 outputs a logic one. When the estimated position PPICK is smaller than 0.5 UI, the sign bit value MSB2 is output as the selection data SELD (FIG. 15 (d)). When the estimated position PPICK is larger than 0.5 UI and before the cross position PINST, the sign bit value MSB3 is output as the selection data SELD (FIG. 15 (e)). When the estimated position PPICK is behind the cross position PINST, the sign bit value MSB4 is output as the selection data SELD (FIG. 15 (f)).

  In FIG. 15C, the sign bit values MSB2, MSB3, and MSB4 are the same. At this time, the exclusive OR circuit 414 outputs a logic 0, and the 0 input of the selector 440 and the 1 input of the selector 442 are always selected. Regardless of the estimated position PPICK, the sign bit value MSB3 is always output as the selection data SELD (FIG. 15 (g)).

  In FIG. 15D, the sign bit value MSB3 is different from the sign bit values MSB2 and MSB4. At this time, the exclusive OR circuit 414 outputs logic 0. Therefore, similarly to FIG. 15C, the sign bit value MSB3 is always output as the selection data SELD (FIG. 15H).

  FIG. 16 illustrates an example of the data selection unit 60 illustrated in FIG. The data selection unit 60 includes an OR circuit 610, a NOR circuit 612, a selector 620, a comparator 630, and an inverter 640. The selector 620 includes AND circuits 621, 622, 623, 624 and an OR circuit 625.

  The OR circuit 610 outputs a logic 1 to the AND circuits 621 and 623 when one of the isolated pulse detection signals FPLS and BPLS is activated to a logic 1. The NOR circuit 612 outputs a logic 0 to invalidate the AND circuit 624 when any of the isolated pulse detection signals FPLS, MPLS, and BPLS is activated to a logic 1. Comparator 630 outputs a logic 1 when the value of estimated position signal PPICK is greater than 0.5 UI, and outputs a logic 0 when the value of estimated position signal PPICK is less than 0.5 UI.

  AND circuit 621 outputs the logic of pulse median value FPCV to OR circuit 625 when OR circuit 610 and inverter 640 output logic 1. That is, when one of the isolated pulse detection signals FPLS and BPLS is activated and the value of the estimated position signal PPICK is smaller than 0.5 UI, the pulse median value FPCV is selected. The AND circuit 622 outputs the logic of the pulse median value MPVV to the OR circuit 625 when the isolated pulse detection signal MPLS is activated.

  AND circuit 623 outputs the logic of pulse median value BPCV to OR circuit 625 when OR circuit 610 and comparator 630 output logic 1. That is, when one of the isolated pulse detection signals FPLS and BPLS is activated and the value of the estimated position signal PPICK is larger than 0.5 UI, the pulse median value BPCV is selected.

  The AND circuit 624 inhibits the supply of the selection data SELD to the OR circuit 625 when any of the isolated pulse detection signals FPLS, MPLS, and BPLS is activated, that is, when an isolated pulse is detected. The AND circuit 624 supplies the selection data SELD to the OR circuit 625 when all the isolated pulse detection signals FPLS, MPLS, and BPLS are inactivated, that is, when no isolated pulse is detected. Note that the data pattern shown in FIG. 15D is also detected as an isolated pulse by the isolated pulse determination unit 20. For this reason, the AND circuit 624 prohibits the supply of the selection data SELD to the OR circuit 625. The OR circuit 625 outputs, as output data DOUT, any of the pulse median values FPCV, MPCV, BPCV, or selection data SELD received from the AND circuits 621, 622, 623, 624.

  FIG. 17 shows an example of the simulation waveform of the eye pattern of the analog data signal before the digital code Di is sampled. For example, the analog data signal has a frequency of 5 GHz, an amplitude of 1.6 V, and a channel loss of 12 dB. A waveform indicated by a thick solid line is an example of an isolated pulse pattern (“010”).

  When the isolated pulse is determined without using the threshold determining unit 10, that is, when the threshold signal VTH is not added to the digital code Di in the isolated pulse determining unit 20 shown in FIG. 5, the eye pattern of the waveform indicated by a thick solid line Has an opening degree of 0.4 UI. At this time, an isolated pulse cannot be detected. On the other hand, when the threshold value signal VTH is set to, for example, “+2” (0.1 V) using the threshold determination unit 10, the eye pattern opening degree can be regarded as equivalent to 0.8 UI. . Thereby, the isolated pulse determination unit 20 can reliably detect the isolated pulse.

  FIG. 18 shows an example of a simulation waveform of jitter tolerance of the data decision circuit DDC shown in FIG. Since the data determination circuit DDC having the threshold determination unit 10 can reliably detect an isolated pulse as shown in FIG. 17, data determination errors can be reduced. As a result, the amount of jitter (solid line) can be made larger than the limit value MASK (one-dot chain line), and the jitter tolerance can be improved as compared with a conventional data determination circuit (dashed line) that does not have the threshold determination unit 10.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Further, by generating the corrected digital code CDi using the threshold signal VTH, as shown in FIG. 8, it is possible to detect an isolated pulse even when the digital codes Di1-Di5 are all negative or all positive. In other words, as shown in FIG. 17, an isolated pulse can be reliably detected even when the aperture of the eye pattern is smaller than 0.5 UI.

  FIG. 19 shows an example of the threshold determination unit 10A in another embodiment. The same elements as those described in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. The data determination circuit DDC equipped with the threshold determination unit 10A is the same as the data determination circuit DDC illustrated in FIG. 2 except that the threshold determination unit 10A is provided instead of the threshold determination unit 10 illustrated in FIG. is there.

  The threshold determination unit 10A includes n holding units FF and an averaging unit 110A. “N” is an integer of 2 or more. The averaging unit 110A includes an adder 120A and a multiplier 130A. For example, the holding unit FF is formed by a flip-flop circuit. The holding units FF are connected in series and hold m-bit digital codes Di (for example, 5 bits) in order. The adder 120A adds the digital code Di output from the holding unit FF, and outputs the addition result to the multiplier 130A. For example, the number of bits of the addition result is “m + (n−1)”.

  The multiplier 130A multiplies the addition result by G (−k / n) and outputs the result as a threshold signal VTH. The average value of the digital code Di is obtained by multiplying the addition result by 1 / n. The threshold signal VTH is generated by multiplying the average value by a coefficient k. For example, when the coefficient k is 1/8, the multiplier 130A multiplies the average value of the digital code Di by −1/8 and outputs it as the threshold value VTH. By generating the threshold value VTH by multiplying the average value of the digital code Di by G, it is possible to generate a threshold value VTH that continuously changes in accordance with the transition of the digital code Di. Thereby, an isolated pulse can be detected more reliably and data determination errors can be reduced. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 20 illustrates an example of the threshold determination unit 10B according to another embodiment. The same elements as those described in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. The data determination circuit DDC equipped with the threshold determination unit 10B is the same as the data determination circuit DDC illustrated in FIG. 2 except that the threshold determination unit 10B is provided instead of the threshold determination unit 10 illustrated in FIG. is there.

  The threshold determination unit 10B includes n holding units FF, n multipliers 131B, 132B, 133B, and 134B, and an adder 120B connected to the output of each holding unit FF. “N” is an integer of 2 or more. For example, the holding unit FF is formed by a flip-flop circuit. The holding units FF are connected in series and hold m-bit digital codes Di (for example, 5 bits) in order.

  The multiplier 131B multiplies the value output from the corresponding holding unit FF by G1 (−k1 / n times), and outputs the multiplication result to the adder 120B. The multiplier 132B multiplies the value output from the corresponding holding unit FF by G2 (−k2 / n times), and outputs the multiplication result to the adder 120B. The multiplier 133B multiplies the value output from the corresponding holding unit FF by G3 (−k3 / n), and outputs the multiplication result to the adder 120B. The multiplier 134B multiplies the value output from the corresponding holding unit FF by G4 (−k4 / n), and outputs the multiplication result to the adder 120B. For example, the magnitudes of the coefficients k1, k2, k3, and k4 are k1> k2> k3> k4. Thereby, the weighting of the relatively new digital code Di can be increased, and the weighting of the relatively old digital code Di can be decreased.

  The adder 120B adds the output values from the multipliers 131B, 132B, 133B, and 134B, and outputs the addition result as a threshold value VTH. In this embodiment, the new digital code Di can increase the influence when the value of the threshold value VTH is obtained. As a result, isolated pulses can be detected more reliably and data determination errors can be reduced. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 21 illustrates an example of the threshold determination unit 10C in another embodiment. The same elements as those described in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. The data determination circuit DDC equipped with the threshold determination unit 10C is the same as the data determination circuit DDC illustrated in FIG. 2 except that the threshold determination unit 10C is provided instead of the threshold determination unit 10 illustrated in FIG. is there.

  The threshold determination unit 10C includes an integrator 110C and a multiplier 130C. The integrator 110C includes an adder 120C and a holding unit FF. For example, the holding unit FF is formed by a flip-flop circuit. The adder 120C adds the m-bit digital code Di and the previous digital code Di held in the holding unit FF, and outputs the addition result to the holding unit FF. The multiplier 130C multiplies the integrated value of the digital code Di output from the holding unit FF by Ga (for example, −1/8), and outputs the result as a threshold value VTH. The threshold determination unit 10C illustrated in FIG. 21 operates in the same manner as the threshold determination unit 10A illustrated in FIG. 19 except that the influence of the old digital code Di is included in the value of the threshold VTH. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 22 shows an example of the data determination circuit DDC in another embodiment. The same elements as those described in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. The data determination circuit DDC of this embodiment has an isolated pulse determination unit 20D and a decoder 70D instead of the isolated pulse determination unit 20 shown in FIG. The isolated pulse determination unit 20D includes three isolated pulse generation units 201D, 202D, and 203D and a pulse selection unit 80D. The other configuration of the data determination circuit DDC is the same as that in FIG. The data determination circuit DDC may include any of the threshold determination units 10A, 10B, and 10C illustrated in FIGS. 19, 20, and 21 instead of the threshold determination unit 10 illustrated in FIG. .

  The isolated pulse generation unit 201D is a circuit similar to the isolated pulse determination unit 20 except that the adder 210 of the isolated pulse determination unit 20 illustrated in FIG. 5 is supplied with a fixed value “+ VTH” instead of the threshold value VTH. . That is, the isolated pulse generation unit 201D adds the fixed value “+ VTH” to the digital code CDi to generate the corrected digital code CDi. The fixed value “+ VTH” is the same value as “+ VTH” in FIG. Isolated pulse detection signals FPLS1, MPLS1, BPLS1 and pulse median values FPCV1, MPVV1, BPCV1 correspond to isolated pulse detection signals FPLS, MPLS, BPLS and pulse median values FPCV, MPCV, BPCV output from isolated pulse determination unit 20, respectively. Signal.

  The isolated pulse generation unit 202D is a circuit similar to the isolated pulse determination unit 20 except that the adder 210 of the isolated pulse determination unit 20 shown in FIG. 5 supplies a fixed value “0” instead of the threshold value VTH. . That is, the isolated pulse generator 202D adds the fixed value “0” to the digital code CDi to generate the corrected digital code CDi. The isolated pulse detection signals FPLS2, MPLS2, BPLS2 and the pulse median values FPCV2, MPVV2, BPCV2 correspond to the isolated pulse detection signals FPLS, MPLS, BPLS and the pulse median values FPCV, MPCV, BPCV output from the isolated pulse determination unit 20, respectively. Signal.

  The isolated pulse generation unit 203D is a circuit similar to the isolated pulse determination unit 20 except that the adder 210 of the isolated pulse determination unit 20 shown in FIG. 5 supplies a fixed value “−VTH” instead of the threshold value VTH. is there. That is, the isolated pulse generation unit 203D generates a corrected digital code CDi by adding a fixed value “−VTH” to the digital code CDi. The fixed value “−VTH” is the same value as “−VTH” in FIG. 4. The isolated pulse detection signals FPLS3, MPLS3, and BPLS3 and the pulse median values FPCV3, MPVV3, and BPCV3 correspond to the isolated pulse detection signals FPLS, MPLS, BPLS, and the pulse median values FPCV, MPCV, and BPCV output from the isolated pulse determination unit 20, respectively. Signal. The isolated pulse generators 201D, 202D, and 203D can start operating before the threshold value determination unit 10 generates the threshold signal VTH.

  Each isolated pulse generation unit 201D, 202D, 203D has the pulse detectors 220, 230, 240 shown in FIG. Each of the pulse detectors 220, 230, and 240, when the code of the central correction digital code CDi out of the three correction digital codes CDi is different from the codes of the other two correction digital codes CDi, The code CDi is detected as an isolated pulse.

  The decoder 70D outputs a pulse selection signal PSEL according to the threshold value VTH. Specifically, when the threshold value VTH is “+ VTH” shown in FIG. 4, a pulse selection signal PSEL indicating an “increase value” for selecting the output of the isolated pulse generation unit 201D is output. When the threshold value VTH is “0” shown in FIG. 4, a pulse selection signal PSEL indicating “zero” for selecting the output of the isolated pulse generation unit 202D is output. When the threshold value VTH is “−VTH” shown in FIG. 4, a pulse selection signal PSEL indicating a “decrease value” for selecting the output of the isolated pulse generator 203D is output.

  The pulse selection unit 80D selects one of the outputs of the isolated pulse generation units 201D, 202D, and 203D according to the pulse selection signal PSEL, and outputs the isolated pulse detection signals FPLS, MPLS, BPLS, and pulse median values FPCV, MPCV, BPCV Output as.

  In this embodiment, the operation of the isolated pulse generators 201D, 202D, and 203D can be started before the threshold signal VTH is generated. Therefore, the isolated pulse can be detected earlier than the data determination circuit DDC shown in FIG. As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained.

  FIG. 23 shows an example of a data determination circuit DDC in another embodiment. The same elements as those described in the embodiment described above are denoted by the same reference numerals, and detailed description thereof will be omitted. The data determination circuit DDC of this embodiment has a validity determination unit 90E and an isolated pulse determination unit 20E instead of the isolated pulse determination unit 20 shown in FIG. The other configuration of the data determination circuit DDC is the same as that in FIG. The data determination circuit DDC may include any of the threshold determination units 10A, 10B, and 10C illustrated in FIGS. 19, 20, and 21 instead of the threshold determination unit 10 illustrated in FIG. .

  The validity determination unit 90E includes a code determination unit SIGN, a holding unit FF, an exclusive OR circuit 910, and an inverter 920. For example, the holding unit FF is formed by a flip-flop circuit. The code determination unit SIGN determines the code of the digital code Di and outputs it as a code bit value MSB. Since the sign of the digital code Di is represented by the most significant bit, for example, the sign determination unit SIGN may output the most significant bit MSB of the digital code Di. The holding unit FF outputs the sign bit value MSB0 of the previous digital code Di. The exclusive OR circuit 910 outputs logic 0 when the sign bit values MSB and MSB0 are the same, that is, when the signs of two consecutive digital codes Di are the same. The exclusive OR circuit 910 outputs logic 1 when the sign bit values MSB and MSB0 are different, that is, when the signs of two consecutive digital codes Di are different.

  The inverter 920 inverts the output of the exclusive OR circuit 910 and outputs it as the enable signal EN. Therefore, the validity determination unit 90E activates the enable signal EN to logic 1 when the signs of two consecutive digital codes Di are the same, and sends the enable signal EN when the signs of the two consecutive digital codes Di are different. Activate to logic zero.

  The isolated pulse determination unit 20E has a function of detecting an isolated pulse when the enable signal EN is activated and the sign bit values of three consecutive digital codes Di are “110” and “001”. is doing. The function of detecting an isolated pulse when the most significant bit MSB of three consecutive digital codes Di is “010” and “101” is the same as that of the isolated pulse determination unit 20 shown in FIG. An example of the isolated pulse determination unit 20E is shown in FIGS.

  FIG. 24 illustrates an example of the isolated pulse determination unit 20E illustrated in FIG. The isolated pulse determination unit 20E includes pulse detectors 220E, 230E, and 240E instead of the pulse detectors 220, 230, and 240 of the isolated pulse determination unit 20 illustrated in FIG. The other configuration of the isolated pulse determination unit 20E is the same as that of the isolated pulse determination unit 20 shown in FIG. The pulse detectors 220E, 230E, and 240E operate in response to the enable signal EN.

  FIG. 25 shows an example of the pulse detector 220E shown in FIG. Detailed descriptions of the same elements as those in FIG. 6 are omitted. The pulse detector 220E includes AND circuits 221, 222, 224, and 225 and an OR circuit 226. Note that the pulse detector 230E shown in FIG. 24 is the same circuit as the pulse detector 220E, receives the sign bit values SB2, SB3, and SB4 instead of the sign bit values SB1, SB2, and SB3, and receives the isolated pulse detection signal FPLS. Instead, the isolated pulse detection signal MPLS is output. The pulse detector 240E shown in FIG. 24 is the same circuit as the pulse detector 220E, receives the sign bit values SB3, SB4, and SB5 instead of the sign bit values SB1, SB2, and SB3, and replaces the isolated pulse detection signal FPLS. The isolated pulse detection signal BPLS is output.

  The AND circuits 221 and 222 are the same as those in FIG. When the enable signal EN is activated to logic 1, the AND circuit 224 receives the sign bit values SB1 and SB2 and the inverted logic of the sign bit value SB3, and detects logic “110”. The AND circuit 225 receives the inverted logic of the sign bit values SB1 and SB2 and the sign bit value SB3 when the enable signal EN is activated to the logic 1, and detects the logic “001”. The OR circuit 224 activates the isolated pulse detection signal FPLS to logic 1 when any of the AND circuits 221, 222, 224, 225 outputs logic 1.

  FIG. 26 shows an example of the operation of the data determination circuit DDC shown in FIG. Detailed descriptions of the same operations as those in FIGS. 7 and 8 are omitted. FIG. 26 shows the operation when the threshold value VTH is “−3” or “+3”. As in FIG. 8, a thick solid line indicates an analog data signal, and a white circle indicates a digital code Di. A black circle indicates a corrected digital code CDi obtained by adding a threshold value VTH to the digital code Di, and a thick broken line indicates an apparent analog data signal corresponding to the corrected digital code CDi.

  In FIG. 26A, the digital codes Di1-Di5 are continuously negative. Therefore, the validity determination unit 90E shown in FIG. 23 activates the enable signal EN to logic 1 while receiving the digital codes Di1-Di5. Since the sign bit values SB2, SB3, and SB4 of the correction digital codes CDi2, CDi3, and CDi4 are “110”, the pulse detector 230E illustrated in FIG. 24 performs logic 1 from the AND circuit corresponding to the AND circuit 224 in FIG. Is output. As a result, the isolated pulse detection signal MPLS is activated to logic 1. That is, an isolated pulse is detected when the codes of the two correction digital codes CDi2 and CDi3 on the center side are different from the codes of the other correction digital codes CDi1, CDi4, and CDi5.

  26B, 26D, and 26E, since the codes of the digital codes Di1-Di5 are the same, the enable signal EN is activated to logic 1. In FIG. 26D, since the sign bit values SB2, SB3, and SB4 of the correction digital codes CDi2, CDi3, and CDi4 are “001”, the pulse detector 230E activates the isolated pulse detection signal MPLS to logic one. . In FIG. 26B, since the sign bit values SB3, SB4, SB5 of the correction digital codes CDi3, CDi4, CDi5 are “110”, the pulse detector 240E shown in FIG. 1 is activated. That is, an isolated pulse is detected when the codes of the two correction digital codes CDi3 and CDi4 on the center side are different from the codes of the other correction digital codes CDi1, CDi2, and CDi5. In FIG. 26E, since the sign bit values SB3, SB4, SB5 of the correction digital codes CDi3, CDi4, CDi5 are “001”, the pulse detector 240E shown in FIG. 1 is activated.

  Thus, by providing the validity determination unit 90E, it is possible to detect an isolated pulse even when the codes of two adjacent correction digital codes CDi are different from the codes of other correction digital codes CDi. In FIG. 26B having an isolated pulse, the codes of the correction digital codes CDi2, CDi3, CDi4 are “011”. Similarly, in FIG. 26E having an isolated pulse, the codes of the correction digital codes CDi2, CDi3, CDi4 are “100”. Therefore, the pulse detectors 220E, 230E, and 240E shown in FIG. 24 can detect isolated pulses having the codes “011” and “100”. In other words, the pulse detectors 220E, 230E, and 240E do not have to have an AND circuit for detecting isolated pulses of “011” and “100”.

  On the other hand, FIGS. 26C and 26D do not include an isolated pulse, as is apparent from the waveform. Also at this time, the sign bit values SB2, SB3, and SB4 of the correction digital codes CDi2, CDi3, and CDi4 are “110” or “001”. However, since the codes of the original digital codes Di2 and Di3 are different, the validity determination unit 90E deactivates the enable signal EN to logic 0. Accordingly, the AND circuit (corresponding to the AND circuit 224 in FIG. 25) of the pulse detection circuit 230E shown in FIG. 24 sets the isolated pulse detection signal FPLS to logic 0 regardless of the sign of the digital codes Di2, Di3, and Di4. Activate. Therefore, no isolated pulse is detected.

  As described above, also in this embodiment, the same effect as that of the above-described embodiment can be obtained. Furthermore, an isolated pulse can be detected not only by the patterns “010” and “101” but also by the patterns “110”, “001”, “100”, and “011”. At this time, the isolated pulse is detected only when the two adjacent digital codes Di have the same code. The comparison of the codes can be performed with a simple circuit. As a result, an isolated pulse can be detected more reliably.

  In the above-described embodiment, the example in which the correction digital code CDi is generated by adding the threshold value VTH to the digital code Di and the isolated pulse is detected according to the code pattern of the correction digital code CDi has been described. However, as shown in FIG. 27, the determination reference value (thick broken line) of the digital code Di may be shifted from the zero point (0) to the plus side or the minus side in accordance with the threshold signal VTH. However, at this time, when the negative digital code Di continues, the threshold VTH is set to a negative value (for example, -3), and when the positive digital code Di continues, the threshold VTH has a positive value (for example, +3). For this reason, it is necessary to output the selection signal SEL1 from the NOR circuit shown in FIG. 4 and to output the selection signal SEL0 from the AND circuit shown in FIG.

  In addition, serial digital codes Di output from the analog-digital converter ADC are converted in parallel, and the logic of analog data signals of a plurality of UIs (unit intervals) are simultaneously determined using a plurality of data determination circuits DDC. Also good. At this time, the operating frequency of the data determination circuit DDC can be lowered. Further, since the parallel digital code Di is supplied to the data determination circuit DDC, for example, the holding unit FF in FIGS. 4, 9, and 14 can be omitted.

  FIG. 28 illustrates an example of a receiver RCV in which the above-described data determination circuit DDC is mounted. Although not particularly limited, the receiver RCV is formed as a semiconductor integrated circuit. A system SYS is formed by the transmitter TRS and the receiver RCV. The transmitter TRS and the receiver RCV operate asynchronously, and the data determination circuit DDC determines the logic of the data string using a blind CDR technique.

  The receiver RCV receives the binary data signal DT output from the transmitter TRS as an analog data signal via a transmission line TP such as a signal cable or a wiring formed on a printed board. The receiver RCV includes an analog-digital converter ADC, the above-described data determination circuit DDC, and a data processing circuit DPC.

  The analog-to-digital converter ADC samples the voltage level of an NRZ (Non-Return to Zero) analog data signal transmitted through the transmission line TP at a predetermined sampling rate, and outputs an m-bit (for example, 5 bits) digital code Di. Is generated. The data processing circuit DPC operates in response to the output data DOUT output from the data determination circuit DDC, and performs signal processing of the binary data signal DT output from the transmitter TRS.

The invention described in the above embodiments is organized and disclosed as an appendix.
(Appendix 1)
A threshold value indicating an increase value when a digital code generated by over-sampling an analog data signal representing a data string of binary data is sequentially received and negative digital codes corresponding to logic 0 of the binary data are consecutive. A threshold value signal indicating a decrease value when a positive digital code corresponding to logic 1 of the binary data continues, and zero when a negative digital code and a positive digital code appear randomly A threshold determination unit that outputs a threshold signal indicating
A correction digital code is generated by adding a value indicated by the threshold signal to the digital code, and among a plurality of consecutive correction digital codes, when the sign of the central correction digital code is different from the sign of another correction digital code, An isolated pulse determination unit that detects the center correction digital code as an isolated pulse;
A binary determination unit for obtaining the logic of the binary data based on the transition of the sign of the continuous digital code;
When the isolated pulse is detected, the logic of the isolated pulse supplied from the isolated pulse determination unit is output as the logic of the binary data. When the isolated pulse is not detected, the logic is obtained by the binary determination unit. And a data selection unit for outputting the logic of the binary data.
(Appendix 2)
A validity determination unit that outputs an enable signal when two adjacent digital codes have the same sign;
The isolated pulse determination unit, when receiving the enable signal, among the plurality of consecutive correction digital codes, when the sign of the two correction digital codes on the center side is different from the sign of the other correction digital code, 2. The data determination circuit according to appendix 1, wherein the two correction digital codes on the center side are detected as isolated pulses.
(Appendix 3)
The isolated pulse determination unit
A first correction digital code is generated by adding the increase value to the digital code, and a code of a central first correction digital code is a code of another first correction digital code among a plurality of consecutive first correction digital codes. A first isolated pulse generator that detects a first first correction digital code as a first isolated pulse when different from
The second correction digital code is generated by adding the decrease value to the digital code, and the sign of the second correction digital code in the center is the sign of the other second correction digital code among a plurality of consecutive second correction digital codes. A second isolated pulse generator that detects the second correction digital code at the center as a second isolated pulse when
A third isolated pulse generator that detects the central digital code as a third isolated pulse when the code of the central digital code is different from the codes of the other digital codes among the plurality of digital codes;
The first isolated pulse is selected when the threshold signal indicates the increased value, the second isolated pulse is selected when the threshold signal indicates the decreased value, and the second isolated pulse is selected when the threshold signal indicates zero. The data decision circuit according to claim 1, further comprising: a pulse selection unit that selects a third isolated pulse and supplies the selected isolated pulse to the data selection unit.
(Appendix 4)
The threshold determination unit
A plurality of holding units connected in series for sequentially holding the codes of the digital code;
When the signs output from the holding unit are all negative, the threshold signal indicating the increase value is output.When the signs output from the holding unit are all positive, the threshold value signal indicating the decrease value is output. Any one of appendix 1 to appendix 3, further comprising: a threshold control unit that outputs a threshold signal indicating zero when the sign output from the holding unit includes both negative and positive. The data determination circuit described.
(Appendix 5)
The threshold determination unit
A plurality of holding units connected in series to hold the digital code in order;
Any one of appendix 1 to appendix 3, further comprising: an averaging unit that obtains an average value of the digital code output from the holding unit and generates the threshold signal by multiplying the average value by a coefficient. A data determination circuit according to the item.
(Appendix 6)
The threshold determination unit
A plurality of holding units connected in series to hold the digital code in order;
A plurality of multipliers each multiplying the digital code output from the holding unit with a coefficient;
An adder for adding the outputs of the multipliers to generate the threshold signal;
Supplementary notes 1 to 3, wherein a coefficient multiplied by the multiplier corresponding to the new digital code is larger in order to make the weight of the relatively new digital code larger than the weight of the relatively old digital code. The data determination circuit according to any one of the above.
(Appendix 7)
The threshold determination unit
An integrator for sequentially integrating the digital code;
The data determination circuit according to any one of appendix 1 to appendix 3, further comprising: a multiplier that multiplies the output of the integrator by a coefficient to generate the threshold signal.
(Appendix 8)
The data determination circuit according to any one of appendix 1 to appendix 7,
An analog-to-digital converter that sequentially generates the digital code by over-sampling the analog data signal;
And a data processing circuit that operates in response to the logic of the binary data determined by the data determination circuit.
(Appendix 9)
Sequentially receiving a digital code generated by over-sampling an analog data signal representing a data string of binary data;
When a negative digital code corresponding to logic 0 of the binary data continues, an increased value is added to the digital code to generate a corrected digital code;
When a positive digital code corresponding to logic 1 of the binary data is continuous, a reduced value is added to the digital code to generate a corrected digital code;
When a negative digital code and a positive digital code appear randomly, the digital code is used as a correction digital code,
Among the plurality of consecutive correction digital codes, when the sign of the center correction digital code is different from the sign of the other correction digital code, the center correction digital code is detected as an isolated pulse,
When the isolated pulse is detected, the logic of the detected isolated pulse is determined as the logic of the binary data,
A data determination method, wherein when the isolated pulse is not detected, the logic of the binary data is determined based on a transition of a sign of the continuous digital code.

  From the above detailed description, features and advantages of the embodiments will become apparent. This is intended to cover the features and advantages of the embodiments described above without departing from the spirit and scope of the claims. Further, any person having ordinary knowledge in the technical field should be able to easily come up with any improvements and modifications, and there is no intention to limit the scope of the embodiments having the invention to those described above. It is also possible to rely on suitable improvements and equivalents within the scope disclosed in.

  DESCRIPTION OF SYMBOLS 1 ... Threshold judgment part; 2 ... Isolated pulse judgment part; 2a ... Adder; 2b ... Pulse detector; 3 ... Binary judgment part; 4 ... Data selection part; 10, 10A, 10B, 10C ... Threshold judgment part; 20D, 20E, isolated pulse determination unit, 30 phase detection unit, 40 binary determination unit, 50 determination timing generation unit, 60 data selection unit, 70D decoder, 80D pulse selection unit, 90E, validity determination unit, 110A, averaging unit; 110C, integrator; 120B, adder; 130C, 131B, 132B, 133B, 134B, multiplier; 201D, 202D, 203D, isolated pulse generation unit, 210, adder; 220, 220E, 230 , 230E, 240, 240E, pulse detectors, 310, 320, sub-phase detectors, 330, adders, 340, selectors, 510, phase detectors 511, 512 ... amplifier; 514, 516 ... integrator; 520 ... adder; ADC ... analog-to-digital converter; BPCV ... pulse median; BPLS ... isolated pulse detection signal; CDi ... correction digital code; Circuit: Di, Digital code, DPC, Data processing circuit, FPCV, Pulse median value, FPLS, Isolated pulse detection signal, MPLS, Isolated pulse detection signal, MPV, Pulse median value, PAV, Average cross position signal, PINST, Cross position Signal: PPICK: Estimated position signal; RCV: Receiver; SB1, SB2, SB3, SB4, SB5: Sign bit value; SIGN: Sign determination unit: TP: Transmission path; TRS: Transmitter: VTH: Threshold signal

Claims (5)

A threshold value indicating an increase value when a digital code generated by over-sampling an analog data signal representing a data string of binary data is sequentially received and negative digital codes corresponding to logic 0 of the binary data are consecutive. A threshold value signal indicating a decrease value when a positive digital code corresponding to logic 1 of the binary data continues, and zero when a negative digital code and a positive digital code appear randomly A threshold determination unit that outputs a threshold signal indicating
A correction digital code is generated by adding a value indicated by the threshold signal to the digital code, and among a plurality of consecutive correction digital codes, when the sign of the central correction digital code is different from the sign of another correction digital code, An isolated pulse determination unit that detects the center correction digital code as an isolated pulse;
A binary determination unit for obtaining the logic of the binary data based on the transition of the sign of the continuous digital code;
When the isolated pulse is detected, the logic of the isolated pulse supplied from the isolated pulse determination unit is output as the logic of the binary data. When the isolated pulse is not detected, the logic is obtained by the binary determination unit. And a data selection unit for outputting the logic of the binary data. A validity determination unit that outputs an enable signal when two adjacent digital codes have the same sign;
The isolated pulse determination unit, when receiving the enable signal, among the plurality of consecutive correction digital codes, when the sign of the two correction digital codes on the center side is different from the sign of the other correction digital code, The data determination circuit according to claim 1, wherein two correction digital codes on the center side are detected as isolated pulses. The isolated pulse determination unit
A first correction digital code is generated by adding the increase value to the digital code, and a code of a central first correction digital code is a code of another first correction digital code among a plurality of consecutive first correction digital codes. A first isolated pulse generator that detects a first first correction digital code as a first isolated pulse when different from
The second correction digital code is generated by adding the decrease value to the digital code, and the sign of the second correction digital code in the center is the sign of the other second correction digital code among a plurality of consecutive second correction digital codes. A second isolated pulse generator that detects the second correction digital code at the center as a second isolated pulse when
A third isolated pulse generator that detects the central digital code as a third isolated pulse when the code of the central digital code is different from the codes of the other digital codes among the plurality of digital codes;
The first isolated pulse is selected when the threshold signal indicates the increased value, the second isolated pulse is selected when the threshold signal indicates the decreased value, and the second isolated pulse is selected when the threshold signal indicates zero. The data determination circuit according to claim 1, further comprising: a pulse selection unit that selects a third isolated pulse and supplies the selected isolated pulse to the data selection unit. A data determination circuit according to any one of claims 1 to 3,
An analog-to-digital converter that sequentially generates the digital code by over-sampling the analog data signal;
And a data processing circuit that operates in response to the logic of the binary data determined by the data determination circuit. Sequentially receiving a digital code generated by over-sampling an analog data signal representing a data string of binary data;
When a negative digital code corresponding to logic 0 of the binary data continues, an increased value is added to the digital code to generate a corrected digital code;
When a positive digital code corresponding to logic 1 of the binary data is continuous, a reduced value is added to the digital code to generate a corrected digital code;
When a negative digital code and a positive digital code appear randomly, the digital code is used as a correction digital code,
Among the plurality of consecutive correction digital codes, when the sign of the center correction digital code is different from the sign of the other correction digital code, the center correction digital code is detected as an isolated pulse,
When the isolated pulse is detected, the logic of the detected isolated pulse is determined as the logic of the binary data,
A data determination method, wherein when the isolated pulse is not detected, the logic of the binary data is determined based on a transition of a sign of the continuous digital code.

Images