JP2012216983A - Data recovery circuit and data recovery method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide data recovery circuit and method that can surely detect an isolation pulse and execute data determination.SOLUTION: A data recovery circuit comprises: a phase detector for calculating a first data unavailable point position through interpolation by using two sequent digital data of a digital data string, and calculating a second data unavailable point position through extrapolation; a data determining unit for extracting a data determination value array from the digital data array on the basis of the average position and instantaneous positions of the first data unavailable points; and a data selection unit for replacing a data determination value corresponding to a section on a time axis sandwiched between two sequent digital data in the data determination value array by a data value assumed based on extrapolation when two second data unavailable points determined from an extrapolation line of two just-before sequent digital data and an extrapolation line of two just-after sequent digital data are located within the section and the signs of the gradients of the two extrapolation lines are different from each other.

Description

  The present disclosure relates generally to electronic circuits, and more particularly to a data restoration circuit and data restoration method for restoring data.

  In a high-speed interface that enables high-speed signal transmission over a long distance, the transmitter and the receiver generally operate asynchronously. Even if the operating frequencies of the transmitter and the receiver are the same according to the standard, since they are asynchronous with each other, a shift in frequency and phase is inevitable. Therefore, a technique is used in which the receiver extracts (restores) the clock from the received data and correctly performs 0/1 determination of the data using the restored clock. This technique is called CDR (Clock and Data Recovery). In the tracking CDR, the phase of a sampling clock for sampling the received data is controlled based on the received data, thereby determining the data by sampling the center of the input data. On the other hand, in blind CDR, data is determined from a sample sequence sampled in an asynchronous state without controlling the phase of the sampling clock. Specifically, the received signal is first sampled by an ADC (analog / digital converter) at a fixed clock signal timing that does not depend on the timing of the received signal. Then, for example, by interpolating the sampled digital data sequence to obtain the zero cross point, the data transition point is obtained, the sampled data is selected based on the data transition point, and the data judgment value is obtained. Ask.

  In the case of the blind CDR, there is a possibility that the data judgment on the receiver side is erroneous for the isolated pulse appearing in the transmission data, as will be described below. Here, the isolated pulse refers to a data string of “010” or “101”. In the case of blind CDR, sampling is performed at a fixed timing that does not depend on the timing of the received signal. Therefore, it is rare that the center data of an isolated pulse can be sampled at the center position of its UI (Unit Interval), and in many cases the front and back points are sampled. Will do.

  FIG. 1 is a diagram illustrating an example of received data of isolated pulses. In FIG. 1, data points obtained by sampling the reception signal RS are indicated by circles. The horizontal direction indicates time, and the vertical direction indicates data values (digital code values at sampled points). Here, ZC is the position of a predetermined code value (that is, the center of the amplitude of the signal) at the approximate center of the range where the digital code of the received data can take a value, and the data value is considered to be in the range of 0 to 1 Corresponds to a value of 0.5.

  In the example shown in FIG. 1, the data points Da and Db are points obtained by sampling the vicinity of the data “1” at the center of the isolated pulse of “010”. Since the waveform of the received signal RS is dull due to the transmission path characteristics, a sufficient signal amplitude corresponding to the data value “1” is not obtained, and the fixed sampling timing is shifted from the center of the data “1”. Therefore, the data values of the data points Da and Db are close to ZC. In the following description, the zero cross point is a cross point where a line segment obtained by interpolating between two adjacent data points intersects the position ZC.

  In the case of the blind CDR, the received data is obtained by using the estimated position Ppick of the data center obtained from the average position of a plurality of zero cross points in the received data over a long period of time and the instantaneous zero cross point position in 1 UI to be determined. The data judgment is performed. In the case of the example of FIG. 1, the estimated position Ppick of the data center is on the right side of the instantaneous zero cross position, and therefore, as the data determination value assigned to the corresponding 1 UI, the binary determination value “1” of the data point Db on the right side of the zero cross point "Is selected. However, there may be a case where the data value of the data point Da is slightly shifted and sampled as the data point Da 'due to further distortion or noise of the received waveform. In this case, since the estimated position Ppick of the data center is on the left side of the instantaneous zero cross position, the binary determination value “0” of the data point Da ′ on the left side of the zero cross point is selected as the data determination value to be assigned to the corresponding 1 UI. Is done. As a result, the isolated pulse disappears from the received data.

  If the data values at the data points Da and Db are not close to ZC (0.5) but close to “0” and “1”, respectively, the instantaneous zero-crossing The position does not change greatly, and the possibility of erroneous data determination is low. If the data values of the data points Da and Db are in the vicinity of ZC, the position of the instantaneous zero-cross point may change greatly even if the data value is slightly shifted due to noise or the like, which may result in erroneous data determination. high. The reason why the data values of the data points Da and Db are in the vicinity of ZC is due to both the fact that the pulse waveform of the isolated pulse tends to become dull and that the sampling timing is fixed in the blind CDR. For example, in the case of the tracking CDR, the phase of the sampling clock is adjusted so that the data center is always sampled. Therefore, for example, in the example of FIG. Therefore, the above problem does not occur.

  In Patent Document 1, at the position where the signal sequence of “010” or “101” is detected from the series of received sampling points, it is not the data determination value selected based on the zero cross point position and the estimated data center position, The center value of the detected isolated pulse is selected. This eliminates the problem of erroneous determination due to isolated pulses in data determination.

  FIG. 2 is a diagram illustrating another example of isolated pulse reception data. In this example, the waveform rounding of the received signal RS is large, and the data values of the data points Da and Db sampled before and after the center data of the isolated pulse do not exceed ZC (0.5). In this case, since the binary determination values of the data points Da and Db are both “0”, the signal sequence of the “010” or “101” isolated pulse cannot be detected. Therefore, the process of detecting and correcting the signal sequence of “010” or “101” from the sequence of received sampling points as in the above-mentioned Patent Document 1 cannot be executed.

  If equalization processing is performed when the received data is sampled by the ADC, the waveform rounding of the received signal can be eliminated to some extent. However, considering the effects of clock synchronization errors and sampling clock jitter, the equalization process close to returning the received signal to the original transmission signal is necessary to reliably avoid the situation shown in FIG. Required. In order to realize such equalization processing, complicated hardware is required, and the cost increases remarkably.

JP 2010-23931 A JP 2010-130366 A

  In view of the above, a data restoration circuit and a data restoration method that can reliably detect an isolated pulse and perform appropriate data determination are desired.

  The data restoration circuit receives a sequence of digital data obtained by sampling the received signal, and uses two consecutive digital data of the sequence of digital data to interpolate the first data switching point on the time axis And calculating the position of the second data switching point on the time axis by extrapolation, and the digital data based on the average position and the instantaneous position of the first data switching point A data determination unit that extracts a sequence of data determination values from a sequence of data, and an extrapolated line of two consecutive digital data immediately before the interval within a segment on the time axis sandwiched between two consecutive digital data And the two second data switching points obtained from the extrapolated straight lines of two consecutive digital data immediately after the section are located and the two outer data A data selection unit that replaces a data determination value corresponding to the section of the data determination value column extracted by the data determination unit with a data value estimated by extrapolation when signs of straight line slopes are different from each other It is characterized by that.

  In the data restoration method, the position of the first data switching point on the time axis is calculated by interpolation using two consecutive digital data of the digital data sequence obtained by sampling the received signal, and the external data Calculating a position on the time axis of the second data switching point by insertion, and extracting a sequence of data determination values from the sequence of digital data based on the average position and the instantaneous position of the first data switching point; Within an interval on the time axis sandwiched between two consecutive digital data, an extrapolation line of two consecutive digital data immediately before the interval and an extrapolation line of two consecutive digital data immediately after the interval When the two second data switching points respectively obtained from are located and the signs of the slopes of the two extrapolated lines are different from each other, The data decision value corresponding to between, characterized in that it comprises the stages of replacing the data value estimated by extrapolation.

  According to at least one embodiment of the present disclosure, a data restoration circuit and a data restoration method capable of reliably detecting an isolated pulse and executing appropriate data determination are realized.

It is a figure which shows an example of the reception data of an isolated pulse. It is a figure which shows another example of the reception data of an isolated pulse. It is a figure which shows an example of a structure of a data restoration circuit. It is a figure for demonstrating operation | movement of an interpolation phase detector. It is a figure which shows an example of a structure of the series determination part shown in FIG. It is a figure for demonstrating operation | movement of the transition monitor shown in FIG. It is a figure for demonstrating the meaning of the signal y and the signal z. It is a figure which shows an example of a structure of an extrapolation phase detector. It is a figure which shows an example of a structure of the isolated pulse determination part shown in FIG. It is a truth table which shows the pulse detection conditions of an extrapolation pulse detection part. It is a figure which shows an example of a waveform in case the output of an extrapolation pulse detection part is set to 1. It is a figure which shows an example of a structure of the series calculating part shown in FIG. It is a figure which shows an example of a structure of the data determination circuit and selection part which are shown in FIG. It is a figure which shows the 1st modification of a structure of a data restoration circuit. It is a figure which shows an example of a structure of a series determination part. It is a truth table which shows the relationship of the input / output signal of the interpolation pulse detector shown in FIG. It is a figure which shows typically the isolated pulse which the interpolation pulse detector shown in FIG. 15 detects. It is a figure which shows the 2nd modification of a structure of a data restoration circuit. It is a figure which shows an example of a structure of the series calculating part of FIG. It is a figure which shows an example of a structure of the phase detector shown in FIG. It is a figure which shows an example of a structure of an isolated pulse determination part.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 3 is a diagram illustrating an example of the configuration of the data restoration circuit. The data restoration circuit includes an interpolation phase detector 10, a phase filter 11, an adder 12, a serial / parallel converter 13, an extrapolation phase detector 14, a transition monitor 15, an isolated pulse determination unit 16, a sequence determination unit 17, and a sequence calculation. And a data determination circuit and selection unit 19. The data restoration circuit further includes a plurality of flip-flops 20 for adjusting timing and synchronizing in the signal path.

  In FIG. 3 and the subsequent similar drawings, the boundary between each functional block indicated by each box and another functional block basically indicates a functional boundary. It does not always correspond to the separation of the signal and the separation of the control logic. In the case of hardware, each functional block may be one hardware module physically separated from other blocks to some extent, or in a hardware module physically integrated with other blocks. One function may be shown. In the case of software, each functional block may be one software module logically separated from other blocks to some extent, or one function in a software module logically integrated with another block. May be shown.

  The input signal to the data restoration circuit is a digital signal that is an output of an analog-to-digital converter (ADC). This digital signal is, for example, a sequence of digital codes generated by analog-digital conversion of an input analog signal (data) at the rise and fall of the clock signal. For example, the input analog signal is 5 Gbit / sec, and the frequency of the clock signal is 5 GHz. In this case, sampling is performed at two points for each 1 UI (one unit interval) which is the data interval (200 ps) of the input analog signal by the rise and fall of the clock signal. If one UI is considered from end to end, three sample points are obtained for each UI.

  FIG. 4 is a diagram for explaining the operation of the interpolation phase detector 10. In FIG. 2, coordinate points 21 to 23 correspond to three consecutive digital data in a digital data string composed of digital codes. These three digital data correspond to three sample points for each UI. The horizontal position of the coordinate point 21 corresponds to the sample timing of the first digital data, and the vertical position of the coordinate point 21 corresponds to the value of the first digital data. Similarly, the horizontal position of the coordinate point 22 corresponds to the sample timing of the second digital data, and the vertical position of the coordinate point 22 corresponds to the value of the second digital data. Further, the horizontal position of the coordinate point 23 corresponds to the sampling timing of the third digital data, and the vertical position of the coordinate point 23 corresponds to the value of the third digital data.

  The interpolation phase detector 10 shown in FIG. 3 receives a sequence of digital data obtained by sampling a received signal, and uses two consecutive digital data in the sequence of digital data to interpolate data switching points. Calculate the position on the time axis. Specifically, the interpolation phase detector 10 intersects a position ZC of a predetermined code value at the approximate center of a range where digital data can take a value and a line segment obtained by interpolating a digital data column. The position of the cross point (data switching point) is calculated from the digital data sequence. In FIG. 4, a line segment 24 and a line segment 25 obtained by interpolating a sequence of digital data are shown. The line segment 24 is obtained by linear interpolation between the coordinate points 21 and 22. The line segment 25 is obtained by linear interpolation between the coordinate points 22 and 23. The range in which the digital data can take a value is, for example, 0 to 31 when the digital code is 5 bits. In this case, the code value 15.5 at the center of the range 0 to 31 in which the digital data can take a value is the position ZC. The interpolation phase detector 10 obtains the position PINST of the cross point where the horizontal line at the position ZC intersects the line segment obtained by the above interpolation by digital calculation. As the central code value, a value rounded to an integer value (for example, 15 or 16) may be used. The position PINST may represent the distance from the left end of the UI to the cross point with a predetermined number of bits.

  In the following description, for convenience, digital data having a value greater than or equal to the code value at position ZC is positive (+), and digital data having a value less than or equal to the code value at position ZC is negative (−).

  The phase filter 11 shown in FIG. 3 obtains a cross point temporal average position Pav based on the cross point position PINST obtained as described above by executing a filter operation. This average position Pav is an average position of a plurality of zero cross points in the received digital data over a long time. The adder 12 obtains the estimated position Ppick of the data center point by adding 0.5 UI to the temporal average position Pav of the cross points. In FIG. 4 and the following description, the length of 1 UI is 1 for convenience. The estimated data center point position Ppick is used to estimate the data center point in the data determination circuit and selection unit 19 as will be described later.

  The serial-parallel converter 13 outputs 16 pieces of data in parallel by demultiplexing the digital data string on the time axis, for example, 1:16. As a result, the output of the serial-parallel converter 13 is a digital data string in which 16 pieces of digital data are output in parallel. By this demultiplexing process, 1-bit high-speed data is serial-parallel converted and collected every 16 bits to generate low-speed data that is 16-bit parallel data. Thereby, for example, the data rate of 5 Gbit / sec is reduced to the data rate of 625 Mbps, and subsequent digital processing can be easily realized. The 16-bit parallel data corresponds to 8 UI (unit interval) data of the input analog signal, and in the subsequent digital processing, the 8 UI data may be processed in parallel. Further, the serial-parallel converter 13 further demultiplexes the instantaneous cross-point position PINST, which is the output of the interpolation phase detector 10, on the time axis to, for example, 1: 8, so that 8 pieces corresponding to 8 UI are obtained. Output data in parallel.

  The above data rate conversion is not necessarily a necessary process, and it is not necessary to lower the data rate if digital processing can be realized at high speed. Further, the process for each 8 UI is merely an example, and the process may be performed for any number of UIs. For example, the process may be for every 4 UI, or may be performed for each UI. Whether it is 8 UI with 16 digital data, 4 UI with 8 digital data, or 1 UI with 2 digital data, the last one of the previous digital data to be processed is Used as the first piece of digital data to be processed next. Since the same processing is executed for each UI regardless of the number of UIs of parallel data to be processed, a case of processing for each UI will be described below.

  The data determination circuit and the data determination circuit (90-1 to 90-8 in FIG. 13) of the selection unit 19 extract the data determination value sequence from the digital data sequence based on the average position and the instantaneous position of the data switching points. To do. Specifically, this data determination circuit receives the instantaneous cross point position PINST (instant position of the data switching point) for the UI of interest from the interpolation phase detector 10 via the serial / parallel converter 13. The data determination circuit further receives from the adder 12 an estimated data center point position Ppick obtained by adding 0.5 to the average position of the data switching points. The data determination circuit further receives digital data from the serial-parallel converter 13 corresponding to, for example, the three sample points 21 to 23 shown in FIG.

  The data determination circuit first obtains a data determination result of three sample points by performing binary determination of each of the digital data of the three sample points to 0 or 1. Note that the length of 1 UI is 1 for convenience. If the estimated data center point position Ppick is larger than 0 and smaller than 1, the estimated data center point position Ppick is used as it is as the estimated data center point position. When the estimated data center point position Ppick is 1 or more, a value obtained by subtracting -1 from the estimated data center point position Ppick is used as the estimated data center point position. Further, when the estimated data center point position Ppick is 0 or less, a value obtained by adding +1 to the estimated data center point position Ppick is used as the estimated data center point position. By this processing, the estimated data center point position always exists within the range of the focused UI.

  Further, the data determination circuit refers to the estimated data center point position located in the UI and the instantaneous cross point position PINST corresponding to the UI in order to specify one data from three data for one UI. Basically, the position of the instantaneous cross point is considered as the data boundary, and the data of the sample point on the same side as the side where the estimated data center point position is located can be selected between the front side and the rear side of the data boundary. .

  For example, in the example illustrated in FIG. 4, binary data that is a 0/1 determination result of three digital data belonging to the target UI is 0, 1, and 1 for the sample points 21, 22, and 23, respectively. In this example, there is an instantaneous cross point position PINST between the sample points 21 and 22. In this case, if the estimated data center point position belongs to the left side of the instantaneous cross point position PINST, the binary data 0 of the sample point 21 is selected as the restoration data. If the estimated data center point position belongs to the right side of the instantaneous cross point position PINST, the binary data 1 of the sample point 22 or 23 is selected as the restoration data.

  When all three binary data belonging to the target UI are 1, any data may be selected, and the result is the same regardless of which data is selected. The same applies when all three binary data are zero. If the three binary data belonging to the target UI are 0, 1, and 0, respectively, the middle binary data 1 may always be selected. The same applies when the three binary data are 1, 0, and 1, respectively. That is, when the cross point appears twice, the binary data that is the center value may always be selected.

  FIG. 5 is a diagram illustrating an example of the configuration of the sequence determination unit 17 illustrated in FIG. The series determination unit 17 includes an encoding circuit 30, D flip-flops 31 to 33, and an isolated point determination circuit 34. The sign circuit 30 outputs a value of 1 or 0 corresponding to the sign of the digital data according to the value of the most significant bit of the input digital data. For example, if the digital code is 5 bits, the position ZC at the center of the range 0 to 31 in which the digital data can take a value is the code value 15.5, and 1 is output for digital data with a value greater than ZC. , 0 may be output for digital data having a value equal to or greater than ZC. Each of the D flip-flops 31 to 33 stores three consecutive output values of the encoding circuit 30. The isolated point determination circuit 34 asserts an isolated pulse detection signal when the stored value of the D flip-flops 31 to 33 is “010” or “101”. The series determination unit 17 outputs the isolated pulse detection signal and the stored value of the D flip-flop 32 that is the isolated pulse value (center data value) when the isolated pulse detection signal is asserted. . In this way, the series determination unit 17 detects an isolated pulse when the three consecutive digital data are 010 or 101.

  FIG. 6 is a diagram for explaining the operation of the transition monitor 15 shown in FIG. FIG. 6 shows a truth table of input / output signals of the transition monitor 15. The transition monitor 15 receives a digital data string obtained by sampling the received signal and outputs signals x, y, and z. In the truth table of FIG. 6, D (0) and D (1) are two consecutive digital data. The signal x is 1 when both D (0) and D (1) are positive (+), and when both D (0) and D (1) are negative (−). Further, when D (0) and D (1) are different from each other, the signal x is 0. The signal y is a sign of D (1) -D (0), and becomes 1 when D (1)> D (0), and becomes 0 when D (1) <D (0). The signal z is an exclusive OR of the signal y and D (0). In this case, if D (0) is positive, 1 is considered, and if D (0) is negative, 0 is calculated, and an exclusive OR is calculated.

  FIG. 7 is a diagram for explaining the meaning of the signal y and the signal z. In FIG. 7, each of straight lines 41 to 44 is an extrapolated straight line of two continuous digital data D (0) and D (1). Here, the extrapolated straight line is a straight line or line segment that extrapolates two consecutive digital data, passes through two positions corresponding to the two consecutive digital data, and is sandwiched between the two consecutive digital data. It is assumed that the straight line extends to a section outside the section on the time axis. The signal y indicates the sign of the slope of the extrapolation line, and the signal z indicates whether the position of the cross point is on the left side or the right side of two consecutive digital data.

  In the case of the extrapolated straight line 41, since the slope is negative (that is, the signal y = 0) and D (0) is negative (0), the signal z is 0. This signal z = 0 indicates that the cross point is located on the left side of D (0) and D (1). In the case of the extrapolated straight line 42, since the slope is positive (ie, signal y = 1) and D (0) is positive (1), the signal z is 0. This signal z = 0 indicates that the cross point is located on the left side of D (0) and D (1). In the case of the extrapolated straight line 43, since the slope is positive (that is, the signal y = 1) and D (0) is negative (0), the signal z is 1. This signal z = 1 indicates that the cross point is located on the right side of D (0) and D (1). In the case of the extrapolated straight line 44, since the slope is negative (that is, the signal y = 0) and D (0) is positive (1), the signal z is 1. This signal z = 1 indicates that the cross point is located on the right side of D (0) and D (1).

  The extrapolation phase detector 14 shown in FIG. 3 receives a sequence of digital data obtained by sampling a received signal, and uses two consecutive digital data in the sequence of digital data to extrapolate data switching points. Calculate the position on the time axis. Specifically, the extrapolation phase detector 14 depends on the value of the signal z indicating whether the position of the cross point is on the right side or the left side of the digital data D (0) and D (1). Either one of D (0) and D (1) is selected, and an extrapolated straight line extending outward is calculated to calculate an extrapolated cross point.

  FIG. 8 is a diagram illustrating an example of the configuration of the extrapolation phase detector 14. The extrapolation phase detector 14 includes a flip-flop 51, an adjacent point calculation unit 52, selectors 53 and 54, and a phase detector 55. The flip-flop 51 holds data D (0) whose timing is earlier in time among the two consecutive digital data D (0) and D (1). As a result, two consecutive digital data D (0) and D (1) can be simultaneously supplied to the adjacent point calculation unit 52 and the selector 53 in parallel. The adjacent point calculation unit 52 calculates 2D (0) −D (1) to calculate the data value l (−1) on the left side of D (0). The adjacent point calculation unit 52 further calculates 2D (1) −D (0) to calculate the data value l (2) on the right side of D (1). The positions of the data values l (-1) and l (2) are schematically shown in FIG.

  The selector 53 selects D (1) when the signal z is 1 and indicates the right side, and selects D (0) when the signal z is 0 and indicates the left side. The selector 54 selects l (2) when the signal z is 1 and indicates the right side, and selects l (-1) when the signal z is 0 and indicates the left side.

  The phase detector 55 interpolates between two points selected by the selectors 53 and 54, that is, between l (-1) and D (0) or between D (1) and l (2). Thus, an extrapolated cross position of two consecutive digital data D (0) and D (1) is obtained. This extrapolation cross position is a value indicating a position within the range of 0 to 0.5, assuming that half of 1UI is 0.5. If there is no cross point even if interpolated between l (-1) and D (0) or between D (1) and l (2), a value of 0.5 or more is set as the extrapolated cross position. For example, 1.0 may be output.

  FIG. 9 is a diagram illustrating an example of the configuration of the isolated pulse determination unit 16 illustrated in FIG. 3. The isolated pulse determination unit 16 includes an extrapolation validity detection unit 60, AND circuits 61 to 63, an extrapolation pulse detection unit 64, a selector 65, an AND circuit 66, an XOR circuit 67, a comparison circuit 68, a selector 69, and flip-flops 70 to 78. The isolated pulse determination unit 16 receives the extrapolation cross position data (extrapolation 0 cross phase) from the extrapolation phase detector 14 and the signals x, y, and z from the transition monitor 15.

  The extrapolation validity detection unit 60 outputs 1 when the extrapolation cross position data indicates a position within the range of 0 to 0.5, and outputs 0 otherwise. The AND circuit 61 calculates an AND logic of the signal x that becomes 1 when two consecutive digital data have the same sign and the output of the extrapolation validity detection unit 60. The output of the AND circuit 61 is 1 in any of the four cases shown in FIG. 7, and the cross points obtained from the extrapolated straight lines of two consecutive digital data are the two This is a case of being located in a section adjacent to a section on the time axis sandwiched between continuous digital data.

  The AND circuit 62 calculates an AND logic between the output of the AND circuit 61 and the signal z. The output of the AND circuit 62 is 1 when the cross point obtained from the extrapolated line of two consecutive digital data is located in the right adjacent section of the section on the time axis sandwiched between the two consecutive digital data. And 0 otherwise. That is, it is 1 when a cross point obtained from an extrapolated straight line of two consecutive digital data immediately before (on the left side) of the interval is located in an interval on the time axis sandwiched between two consecutive digital data. become.

  The AND circuit 63 calculates an AND logic between the output of the AND circuit 61 and the inverted value of the signal z. The output of the AND circuit 63 is 1 when the cross point obtained from the extrapolated straight line of two consecutive digital data is located in the section on the left side of the section on the time axis sandwiched between the two consecutive digital data. And 0 otherwise. That is, it is 1 when a cross point obtained from an extrapolated straight line of two continuous digital data immediately after (on the right side of) the section on the time axis sandwiched between two continuous digital data is located. become.

  The XOR circuit 67 calculates an exclusive OR of the value y (0) of y at the timing of interest and the value y (2) of y two cycles before. The output of the XOR circuit 67 is an extrapolated line of two consecutive digital data immediately before a section sandwiched between two consecutive digital data and an extrapolated line of two consecutive digital data immediately after the section, It is 1 when the signs of the slopes are different from each other, and 0 otherwise.

  The extrapolation pulse detection unit 64 receives the output of the XOR circuit 67, two consecutive outputs from the AND circuit 62, and the output of the AND circuit 63 as input data. The extrapolation pulse detection unit 64 sets the output to 1 when it is determined that the following two conditions are simultaneously satisfied based on these input data, and sets the output to 0 otherwise. The first condition is that within an interval on the time axis sandwiched between two consecutive digital data, an extrapolated straight line of two consecutive digital data immediately before the interval and two consecutive immediately after the interval The two cross points obtained from the extrapolated straight lines of the digital data are located. The second condition is when the signs of the two extrapolated lines are different.

  FIG. 10 is a truth table showing the pulse detection conditions of the extrapolation pulse detector 64. The condition that XOR (y (2), y (0)) is 1 corresponds to the second condition described above. In addition, the condition that L (2) is 1 is a cross obtained from an extrapolated line of two consecutive digital data immediately before the relevant section in a section on the time axis sandwiched between two consecutive digital data. This is the condition where the point is located. The condition that E (0) is 1 is a cross obtained from an extrapolated line of two consecutive digital data immediately after the section within a section on the time axis sandwiched between two consecutive digital data. This is the condition where the point is located. The condition of L (2) and the condition of E (0) are combined to form the first condition.

  FIG. 11 is a diagram illustrating an example of a waveform when the output of the extrapolation pulse detection unit 64 is 1. FIG. FIG. 11 shows that two cross points obtained from an extrapolation line of two consecutive digital data immediately before a certain section and two extrapolation lines of two consecutive digital data immediately after the section are This is a case where it is located in a section and the signs of the two extrapolated lines are different. In this case, an isolated pulse exists in the section.

  Returning to FIG. 9, the comparison circuit 68 compares the extrapolation cross position data at the timing of interest with the extrapolation cross position data two cycles before, and outputs 0 or 1 depending on the comparison result. Specifically, the output is 1 when the extrapolation cross position data at the target timing is smaller, and the output is 0 when the extrapolation cross position data two cycles before is smaller. In FIG. 11, the extrapolation cross position data at the timing of interest is pExt_b, and the extrapolation cross position data two cycles before is pExt_a. In the example of FIG. 11, since pExt_b is smaller, the output of the comparison circuit 68 is 1. The position to which the isolated pulse detected by the extrapolation pulse detector 64 is assigned is determined based on the output value of the comparison circuit 68. Specifically, an isolated pulse is assigned to a data point on the smaller side of extrapolation cross position data. In the example of FIG. 11, since pExt_b is smaller, an isolated pulse is assigned to the data point D (2). If pExt_a is smaller, an isolated pulse is assigned to the data point D (1).

  The selector 65 shown in FIG. 9 adjusts the timing for outputting the isolated pulse detected by the extrapolation pulse detection unit 64 according to the output value of the comparison circuit 68. When the output of the comparison circuit 68 is 0 (when the previous timing is selected), a data value indicating isolated pulse detection is immediately output from the selector 65 without going through the flip-flop 72. When the output of the comparison circuit 68 is 1 (when the later timing is selected), the data value indicating isolated pulse detection is delayed from the flip-flop 72 by one cycle and then output from the selector 65. The selector 69 adjusts the timing of outputting y (2) as the pulse median value according to the output value of the comparison circuit 68. Here, y (2) is the sign of the slope of the extrapolation line and has a value equal to the value (0 or 1) of the isolated pulse. When the output of the comparison circuit 68 is 0, the value of the isolated pulse is immediately output from the selector 69 without going through the flip-flop 78. When the output of the comparison circuit 68 is 1, the value of the isolated pulse is delayed from the flip-flop 78 by one cycle and then output from the selector 69. Note that the output of the comparison circuit 68 may be designed to hold the next cycle when the output of the extrapolation pulse detection unit 64 becomes 1 in one cycle and an isolated pulse is detected.

  The AND circuit 66 calculates an AND logic between the output of the selector 65 at a certain timing and the inverted value of the output of the selector 65 one cycle before. This calculation prevents the isolated pulse detection from occurring for two consecutive cycles.

  FIG. 12 is a diagram illustrating an example of the configuration of the series calculation unit 18 illustrated in FIG. 3. The series calculation unit 18 includes a selector 80, an OR circuit 81, a serial / parallel conversion unit 82, and a serial / parallel conversion unit 83. The selector 80 receives the isolated pulse detection signal −E by extrapolation from the isolated pulse determination unit 16 and the isolated pulse detection signal −I by sequence determination from the sequence determination unit 17 as selection signals. Based on this selection signal, the selector 80 selects either the pulse median value −E of the isolated pulse by extrapolation from the isolated pulse determination unit 16 or the pulse median value −I of the isolated pulse by sequence determination from the sequence determination unit 17. Select. If the isolated pulse detection signal -E is 1, the pulse median value -E is selected. If the isolated pulse detection signal -I is 1, the pulse median value -I is selected. If both the isolated pulse detection signal-E and the isolated pulse detection signal-I are 0 or both are 1, 0 is selected. The output of the selector 80 is converted into parallel data by the serial / parallel converter 82 as in the case of the serial / parallel converter 13 shown in FIG. This parallel data is, for example, 17-bit isolated pulse median value data Pval [16: 0] corresponding to 8 UI. The OR circuit 81 calculates the OR logic of the isolated pulse detection signal -E and the isolated pulse detection signal -I. The output of the OR circuit 81 is converted into parallel data by the serial / parallel converter 83, as in the serial / parallel converter 13 shown in FIG. This parallel data is, for example, 17-bit isolated pulse detection value data Pdet [16: 0] corresponding to 8 UI.

  FIG. 13 is a diagram illustrating an example of the configuration of the data determination circuit and the selection unit 19 illustrated in FIG. The data determination circuit and selection unit 19 includes data determination circuits 90-1 to 90-8, selectors 91-1 to 91-8, selectors 92-1 to 92-8, a folding circuit 93, a flip-flop 94, a comparison circuit 95, And a comparison circuit 96.

  The data determination circuits 90-1 to 90-8 extract a sequence of data determination values from the sequence of digital codes based on the cross point positions PINST_0 to PINST_7 and the estimated position Ppick of the data center point. More specifically, a column of data determination values is extracted by selecting binary data from a column of binary data DT_0 to DT_16 obtained by performing binary determination on a column of digital codes.

  The folding circuit 93 outputs the Ppick as it is when the estimated data center point position Ppick is less than 1, and outputs the Ppic-1 as a new Ppick when the estimated data center point position Ppick is 1 or more. If the estimated data center point position Ppick may be 0 or less, the folding circuit 93 may output Ppic + 1 as a new Ppick. By the processing of the folding circuit 93, the estimated data center point position always exists within the range of the focused UI.

  The data determination circuits 90-1 to 90-8 are provided corresponding to the eight UIs, respectively. Each of the data determination circuits 90-1 to 90-8 selects one binary data from the three binary data (0/1 determination result) corresponding to 1 UI, and outputs it as a data determination value. When one binary data is selected for one UI, the estimated data center point position Ppick located in the UI and the instantaneous cross point position PINST corresponding to the UI are referred to. As mentioned above, basically, the position of the instantaneous cross point is considered as the data boundary, and the data of the sample point that is on the same side as the side where the estimated data center point position is located on the front side and the back side of the data boundary Should be selected. When all three binary data belonging to the target UI are 1, any data may be selected, and the result is the same regardless of which data is selected. The same applies when all three binary data are zero. If the three binary data belonging to the target UI are 0, 1, and 0, respectively, the middle binary data 1 may always be selected. The same applies when the three binary data are 1, 0, and 1, respectively.

  The selectors 91-1 to 91-8 are based on the signal PHDT, the isolated pulse median data Pval [16: 0], and the isolated pulse detection value data Pdet [16: 0], so that the isolated pulse or data determination circuit 90-1 is used. Any one of outputs from 90-8 is selected. When attention is paid to the selector 91-1 of the first UI as an example for explanation, a combination of signals (PHDT, Pdet [2], Pdet [0]) is supplied as a selection signal. Here, the signal PHDT is a signal generated by the comparison circuit 96, and becomes 1 when the Ppick after folding is larger than 0.5, and becomes 0 when it is 0.5 or less.

  When the selection signal (PHDT, Pdet [2], Pdet [0]) is (1, 1, *), the isolated pulse value Pval [2] is selected ("*" is don't care). That is, when the data center estimated position is in the second half of 1 UI and Pdet [2] at the right end of 1 UI is 1, indicating isolated pulse detection, this isolated pulse value Pval [2] is selected and output. When the selection signals (PHDT, Pdet [2], Pdet [0]) are (1, 0, *), the output of the data determination circuit 90-1 is selected. That is, when the data center estimated position is in the second half of 1 UI and Pdet [2] at the right end of 1 UI is 0, indicating the absence of an isolated pulse, the output of data determination circuit 90-1 is selected and output.

  When the selection signals (PHDT, Pdet [2], Pdet [0]) are (0, *, 1), the isolated pulse value Pval [0] is selected. That is, when the data center estimated position is in the first half of 1 UI and Pdet [0] at the left end of 1 UI is 1, indicating isolated pulse detection, this isolated pulse value Pval [0] is selected and output. When the selection signals (PHDT, Pdet [2], Pdet [0]) are (0, *, 0), the output of the data determination circuit 90-1 is selected. That is, when the data center estimated position is in the first half of 1 UI and Pdet [0] at the left end of 1 UI is 0, indicating the absence of an isolated pulse, the output of the data determination circuit 90-1 is selected and output.

  The selectors 92-1 to 92-8 select and output either the isolated pulse or the outputs of the selectors 91-1 to 91-8 based on the isolated pulse detection result at the center of each UI. Outputs from the selectors 92-1 to 92-8 are data determination values DEC_DT [1] to DEC_DT [8]. Focusing on the selector 92-1 of the first UI as an example for explanation, when Pdet [1] is 1 at the center of 1UI to indicate isolated pulse detection, this isolated pulse value Pval [1] is selected and output. . When Pdet [1] becomes 0 to indicate the absence of an isolated pulse, the output of the selector 91-1 is selected and output.

  In this way, the selectors 91-1 to 91-8 and the selectors 92-1 to 92-8 function as a data selection unit, and an isolated pulse is used in place of the data determination values by the data determination circuits 90-1 to 90-8. The value Pval is selected and output. That is, the data determination values by the data determination circuits 90-1 to 90-8 are replaced with the isolated pulse value Pval. Here, the isolated pulse value Pval is a data value estimated by data extrapolation in the isolated pulse determination unit 16 or a data value estimated by sequence determination in the sequence determination unit 17. Thereby, it is possible to appropriately detect the isolated pulse point and reflect it in the data restoration result.

  The binary data DT_0 at one end of the 8 UI section is additionally output as it is as the data determination value DEC_DT [0]. The data rate between transmission and reception is adjusted by appropriately deleting and adding data to these data determination values DEC_DT [0] to DEC_DT [8]. In order to adjust the total number of received data, a flip-flop 94 and a comparison circuit 95 are provided. The flip-flop 94 stores the Ppick of the previous operation cycle. The comparison circuit 95 compares the Ppick of the current cycle and the output of the flip-flop 94 (Ppick of the previous cycle) with a fixed value of 0.5. If Ppick of the current cycle is smaller than 0.5 and Ppick of the previous cycle is larger than 0.5, the comparison circuit 95 generates the instruction signal DEC_DT_NUM in the first state. Further, when Ppick of the current cycle is larger than 0.5 and Ppick of the previous cycle is smaller than 0.5, the comparison circuit 95 generates the instruction signal DEC_DT_NUM in the second state. The instruction signal DEC_DT_NUM may be, for example, 2-bit binary data, and the 2 bits specify the first state, the second state, and the third state that is neither the first state nor the second state. be able to. When the estimated position Ppick of the data center point shifts in a delayed direction, the instruction signal DEC_DT_NUM in the first state is generated. When the estimated position Ppick of the data center point changes in a direction that advances, the instruction signal DEC_DT_NUM in the second state is generated. The instruction signal in the third state corresponds to the case where no data is skipped or added.

  FIG. 14 is a diagram illustrating a first modification of the configuration of the data restoration circuit. In FIG. 14, the same or corresponding elements as those of FIG. 3 are referred to by the same or corresponding numerals, and a description thereof will be omitted as appropriate. In FIG. 14, a sequence determination unit 17A is provided instead of the sequence determination unit 17 of FIG. The series determination unit 17A detects an isolated pulse based on the output signals x and y of the transition monitor 15.

  FIG. 15 is a diagram illustrating an example of the configuration of the sequence determination unit 17A. Sequence determination unit 17A includes a plurality of flip-flops 100 and an interpolated pulse detector 101. A plurality of flip-flops 100 are provided for timing adjustment and data retention. The interpolation pulse detector 101 detects an isolated pulse based on the value x (2) at a certain timing of the signal x and the value x (3) in the immediately preceding cycle, and the value y (3) of the signal y. Is output as an isolated pulse value.

  FIG. 16 is a truth table showing the relationship between input and output signals of the interpolation pulse detector shown in FIG. As shown in this truth table, the interpolated pulse detector 101 is configured such that when both x (3) and x (2) are 0, that is, when cross points are detected continuously for two sections, Detect isolated pulses. In other cases, no isolated pulse is detected. The value (sign) of the isolated pulse is y (3), and the pulse position is D (1), that is, the center of two adjacent sections.

  FIG. 17 is a diagram schematically showing an isolated pulse detected by the interpolation pulse detector shown in FIG. As shown in FIG. 17, when there are two consecutive cross points (that is, x (3) = x (2) = 0), an isolated pulse is detected at the data point at the boundary between the two sections. The

  FIG. 18 is a diagram illustrating a second modification of the configuration of the data restoration circuit. In FIG. 18, the same or corresponding elements as those of FIG. 3 are referred to by the same or corresponding numerals, and a description thereof will be omitted as appropriate. 18, the interpolated phase detector 10 and the extrapolated phase detector 14 of FIG. 3 are combined into a phase detector 110, and the isolated pulse determining unit 16 and the sequence determining unit 17 of FIG. 3 are combined. An isolated pulse determination unit 112 is provided. Accordingly, a selector 111 is newly provided, and a series calculation unit 18A is provided instead of the series calculation unit 18 of FIG.

  FIG. 19 is a diagram illustrating an example of the configuration of the series calculation unit 18A of FIG. Series operation unit 18A includes serial-parallel converters 121 and 122. The serial / parallel converters 121 and 122 convert the pulse median value and the isolated pulse detection signal from the isolated pulse determination unit 112 into parallel data corresponding to, for example, 8 UI.

  20 is a diagram showing an example of the configuration of the phase detector 110 shown in FIG. In FIG. 20, the same or corresponding elements as those of FIG. 8 are referred to by the same or corresponding numerals, and a description thereof will be omitted as appropriate. In the phase detector 110 of FIG. 20, a selector 56 is added to the extrapolated phase detector 14 of FIG. The selector 56 outputs the outputs of the selectors 53 and 54 when the value of the signal x is 1 for two consecutive digital data, indicating that there is no cross point in the section between the two consecutive digital data. To cause the phase detector 55 to perform extrapolation. Further, when the value of the signal x is 0 with respect to two consecutive digital data and the selector 56 indicates that a cross point exists between the two consecutive digital data, the selector 56 indicates that the two consecutive digital data. Digital data is selected and the phase detector 55 is made to perform interpolation.

  The selector 111 shown in FIG. 18 selects an invalid value when the value of the signal x is 1 for two consecutive digital data and there is no cross point in the section between the two consecutive digital data. Output. In the case where the selector 111 further indicates that the value of the signal x is 0 for two pieces of continuous digital data and a cross point exists in a section between the two pieces of continuous digital data, the selector 111 Select an output to output. Thereby, only the cross point detected by the interpolation can be supplied to the phase filter 11.

  FIG. 21 is a diagram illustrating an example of the configuration of the isolated pulse determination unit 112. In FIG. 21, the same or corresponding elements as those of FIG. 9 are referred to by the same or corresponding numerals, and a description thereof will be omitted as appropriate. The isolated pulse determination unit 112 shown in FIG. 21 includes a selector 131, an interpolation pulse detection unit 132, an OR circuit 133, and flip-flops 134 and 135 in addition to the elements of the isolated pulse determination unit 16 shown in FIG.

  The interpolated pulse detector 132 has the same configuration as that shown in FIG. 15, and when x at a certain timing and x in the immediately preceding cycle are both 0, that is, a cross point is detected continuously for two sections. In this case, 1 indicating isolated pulse detection is output. In other cases, no isolated pulse is detected. When an isolated pulse is detected in this way, the selector 131 selects a signal y at an appropriate timing, which is the value (sign) of the detected isolated pulse, with 1 being the output of the interpolation pulse detector 132 as a selection signal. And output. When the interpolation pulse detector 132 does not detect an isolated pulse by interpolation, the selector 131 outputs the result of the extrapolation pulse. The OR circuit 133 takes an OR logic between the isolated pulse detection result by extrapolation and the isolated pulse detection result by interpolation, and outputs the result.

  As described above, in the configuration shown in FIG. 18, the interpolated phase detector 10 and the extrapolated phase detector 14 are collectively used as the phase detector 110, and the isolated pulse determining unit 16 and the sequence determining unit 17 are collectively isolated. By using the pulse determination unit 112, the circuit scale can be further reduced.

  As mentioned above, although this invention was demonstrated based on the Example, this invention is not limited to the said Example, A various deformation | transformation is possible within the range as described in a claim.

DESCRIPTION OF SYMBOLS 10 Interpolation phase detector 11 Phase filter 12 Adder 13 Serial parallel converter 14 Extrapolation phase detector 15 Transition monitor 16 Isolated pulse determination part 17 Sequence determination part 18 Sequence calculation part 19 Data determination circuit and selection part

Claims (5)

A sequence of digital data obtained by sampling a received signal is received, and the position of the first data switching point on the time axis is calculated by interpolation using two consecutive digital data in the sequence of digital data. And a phase detector for calculating a position on the time axis of the second data switching point by extrapolation;
A data determination unit that extracts a column of data determination values from the column of digital data based on an average position and an instantaneous position of the first data switching point;
Within an interval on the time axis sandwiched between two consecutive digital data, an extrapolation line of two consecutive digital data immediately before the interval and an extrapolation line of two consecutive digital data immediately after the interval When the two second data switching points respectively obtained from are located and the signs of the slopes of the two extrapolated lines are different from each other, the data judgment value column extracted by the data judgment unit is included in the section of the data judgment value sequence. A data restoration circuit including a data selection unit that replaces a corresponding data determination value with a data value estimated by extrapolation.   A sequence determination unit that detects an isolated pulse when three consecutive digital data is 010 or 101, and the data selection unit is extracted by the data determination unit when the sequence determination unit detects an isolated pulse; The data restoration circuit according to claim 1, wherein the data judgment value is replaced with a data value of an isolated pulse detected by the series judgment unit.   Within an interval on the time axis sandwiched between two consecutive digital data, an extrapolation line of two consecutive digital data immediately before the interval and an extrapolation line of two consecutive digital data immediately after the interval When the two second data switching points respectively obtained from are located and the signs of the slopes of the two extrapolated lines are different from each other, the data selection unit further includes an isolated pulse determination unit that detects an isolated pulse, When the isolated pulse determination unit detects an isolated pulse, the data determination value corresponding to the section of the sequence of the data determination values extracted by the data determination unit is the data determination value detected by the isolated pulse determination unit. 3. The data restoration circuit according to claim 1, wherein the data restoration circuit is replaced with a data value. The position of the first data switching point on the time axis is calculated by interpolation using two consecutive digital data in the digital data sequence obtained by sampling the received signal, and the second data is obtained by extrapolation. Calculate the position on the time axis of the data switching point,
Extracting a sequence of data determination values from the sequence of digital data based on an average position and an instantaneous position of the first data switching point;
Within an interval on the time axis sandwiched between two consecutive digital data, an extrapolation line of two consecutive digital data immediately before the interval and an extrapolation line of two consecutive digital data immediately after the interval When the two second data switching points obtained from the above are located and the signs of the slopes of the two extrapolated lines are different from each other, the data judgment value corresponding to the section of the data judgment value column is A data restoration method comprising: replacing each stage with a data value estimated by insertion. Detect an isolated pulse when three consecutive digital data is 010 or 101,
5. The data restoration method according to claim 4, wherein a data judgment value in the data judgment value column is replaced with a data value of the detected isolated pulse.

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