JPH05166393A - Signal generating circuit - Google Patents

Abstract

PURPOSE:To provide a structure in which the output line of a signal generating circuit is easily shielded on an layout pattern without an increase in a cost. CONSTITUTION:In the signal generating circuit which outputs plural signals from plural output terminals OUT 2 and 3 at a different timing, the output lines OUT 2 and 3 are batch reset and a signal line TR, which determines the batch reset timing, shields the terminals OUT 2 and 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal generating circuit having a function of resetting its output.

[0002]

2. Description of the Related Art Conventionally, a circuit as shown in FIG. 2 has been proposed as a shift register for sequentially outputting pulses.

FIG. 3 is a diagram showing an example of the pattern layout of the circuit shown in FIG.

2 and 3, M6 to M17 are MOSs.
Transistors, C2 and C3 are bootstrap capacitors, TR is a trigger pulse line, φ1 and φ2 are clock pulse lines, IN is a shift register input, and OUT1
~ OUT4 indicates shift register output.

In FIG. 3, LOCOS is LOCOS.
S non-oxidized area, POL is polysilicon wiring, AL is aluminum wiring, CNT is aluminum wiring and LOCOS unoxidized portion, aluminum wiring and polysilicon wiring are connected, DCT is polysilicon wiring and LOC
A connection with a portion which is not OS-oxidized is shown.

FIG. 4 is a timing diagram of pulses for driving such a shift register. As shown in FIG. 4, first, TR causes the shift register of FIG. 2 to be in the initial state, and the operation is started by inputting IN in synchronization with φ2. After that, the outputs OUT1 to OUT4 are sequentially output in synchronization with the two-phase clock pulses φ1 and φ2.

At this time, the output lines OUT1 to OUT4 are in a floating state for a long period of time, and unless they are shielded by a constant potential, malfunctions may occur due to noise from the outside. So, conventionally,
Shielding is performed with the GND line.

[0008]

However, because of the layout, the GND needs to surround the entire shift register in common with the well potential, and is therefore arranged in the peripheral portion of the layout pattern. Therefore, there is a problem to be solved in that it is positionally difficult to shield the shift register output, which makes a complicated connection at the center of the circuit pattern, with GND.

That is, in the above conventional example, the output line OUT
In order to prevent the floating state of 1 to OUT4, G
Even if you try to shield with a constant potential such as ND,
In the case of a layout pattern that cannot be shielded with the pattern of, another layer for shielding is required,
There is a cost problem.

In addition, if an attempt is made without providing a shield layer, a layout in which it is difficult to shield directly with the GND line as in the above-described conventional example must be avoided in the pattern design, and the degree of freedom in design is high. There was a problem that became smaller.

[0011]

As a means for solving the above problems, the present invention provides a function for collectively resetting the output lines in a signal generation circuit for outputting a plurality of signals from a plurality of output terminals at different timings. And a signal line that determines the timing of the batch reset,
It has a signal generation circuit characterized in that the plurality of output terminals are shielded.

[0012]

According to the present invention, the trigger pulse pattern that needs to reset all bootstrap capacitors of the shift register all the time passes near the output of the shift register in the pattern layout. You can easily shield the output.

That is, according to the present invention, the floating output line is shielded by using a trigger pulse line for collectively resetting another portion in the shift register without using a constant potential line. It does not require a separate shield layer and can be shielded without layout constraints.

[0014]

1 is an example of a pattern layout diagram of a shift register as a signal output circuit which best represents the features of the present invention. This embodiment is the same as the conventional example described above with reference to FIG. 3, except for the pattern of the trigger pulse line TR.

In FIG. 1, GND is ground, TR
Is a trigger pulse line, φ1 and φ2 are clock pulse lines, and OUT2 and OUT3 are shift register output lines (output terminals).

In FIG. 1, LOCOS is LOCOS.
S non-oxidized area, POL is polysilicon wiring, AL is aluminum wiring, CNT is aluminum wiring and LOCOS unoxidized portion, aluminum wiring and polysilicon wiring are connected, DCT is polysilicon wiring and LOC
A connection with a portion which is not OS-oxidized is shown.

In the present embodiment shown in FIG. 1, the output lines of the signal output circuit are collectively reset, and the pattern of the trigger pulse line TR that determines the timing of collective reset is made as thick as possible to shift register outputs OUT2, OUT.
It is shielded on top of 3.

In terms of layout, the well potential that surrounds the entire shift register and is isolated from the outside is often common to the GND line, whereas the trigger pulse line that collectively resets all the bootstrap capacitors of the shift register has a pattern. On the layout, it always passes near the output of the shift register, so as shown in this embodiment,
Positionally easy to shield.

Further, since the trigger pulse is not required to have a high speed, the layout can be made thicker.

However, the output impedance of the trigger pulse line is
It is necessary to keep it particularly low. Therefore, in this embodiment, as shown in FIG. 1, the impedance is made low by thickening the wiring.

[0021]

As described above, according to the present invention,
By using the trigger pulse line to reset a part of the signal circuit such as the shift register all at once, by shielding the output line of the signal circuit, the trigger pulse that always passes near the output of the shift register in the pattern layout. The pattern can be used to easily shield the position.

Therefore, even in the case of a layout which is conventionally difficult to shield with the GND line, the shield can be shielded without forming a shield layer, and the increase in cost due to the shield can be suppressed.

Further, since it is not necessary to consider a layout capable of shielding with a GND line as in the conventional case, there is an effect that the degree of freedom in design is increased.

That is, according to the present invention, it is possible to easily prevent the malfunction of the output line without increasing the cost.

[Brief description of drawings]

FIG. 1 is a diagram showing a pattern layout of a shift register embodying the present invention.

FIG. 2 is an equivalent circuit diagram of a shift register having a function of collectively resetting outputs.

FIG. 3 is a pattern layout diagram of a conventional shift register.

FIG. 4 is a timing chart illustrating the operation of a shift register.

[Explanation of sign]

M6 to M17 MOS transistors C2 and C3 bootstrap capacitance, TR trigger pulse line, φ1 and φ2 clock pulse line, IN shift register (signal output circuit) input, OUT1 to OUT4 shift register output, LOCOS LOCOS non-oxidized region, POL Polysilicon wiring, AL aluminum wiring, CNT Aluminum wiring and LOCOS non-oxidized portion, aluminum wiring and polysilicon wiring connection, DCT Polysilicon wiring and LOCOS non-oxidized portion are shown.

Claims (3)

[Claims] 1. A signal generation circuit for outputting a plurality of signals from a plurality of output terminals at different timings, the signal line having a function of collectively resetting the output lines and determining the timing of the collective reset A signal generation circuit characterized by shielding the terminals. 2. The output terminal is an output line.
The signal generating circuit according to. 3. The signal line having a function of collectively resetting the output lines and determining the timing of the collective reset is a trigger pulse line for transmitting a reset pulse. The signal generating circuit described.