JPH0265238A - Semiconductor integrated device - Google Patents

Abstract

PURPOSE:To inhibit the switching noise of a digital signal from spreading to an analog circuit sensitive to noise by a method wherein two shielding signals parallel to a certain signal are arranged on both sides of the signal at specified distances from the certain signal wiring and moreover, another signal to be shielded is arranged on the outside of one shielding signal of the two shielding signals at a specified distance from the shielding signal and a constant potential is applied to the two shielding signals. CONSTITUTION:Shielding signals 2 and 3 are arranged on both sides of a digital signal 1 at the intervals L1 between wirings and a signal 4 to be shielded to need to avoid the switching noise of the signal 1 is arranged at the interval L2 between wirings from the signal 2. An stable constant potential (a shielding potential) is applied to the signals 2 and 3 and the L1 is L1<=L2 to the L2. Thereby, as an electric line of force, which is generated from the signal 1, is bent and the bonding force of the signal 1 with the signal 4 is reduced, the noise resistance of a device is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a layout method for an analog/digital mixed type semiconductor integrated device.

[Conventional technology]

Conventionally, when analog circuits sensitive to noise are present on a semiconductor integrated circuit, a method has been adopted in which digital signals (particularly high frequencies) are placed away from blocks of analog circuits.

[Problem to be solved by the invention] However, as the degree of integration of circuits increases year by year, it has become more efficient to place circuit blocks with one function together (
In particular, it is undesirable to make analog circuit signals unnecessarily long.Also, when there are many elements occupying a relatively large area, such as resistive elements and capacitive elements, it is a method to increase the distance from high-speed digital signals. has a limit.

Therefore, an object of the present invention is to suppress the influence of switching noise of high-speed digital signals on circuits sensitive to noise such as analog circuits.

[Means for Solving the Problems] In order to solve the above problems, the semiconductor integrated device of the present invention has the following features:
In the same wiring layer, two parallel signals (shield signals) are placed on both sides at a distance LI from a certain signal wiring, and another signal is placed outside one of the shield signals at a distance L2 from the shield signal. A signal wiring (shielded signal) is arranged, a constant potential (shield potential) is applied to the two shield signals, and L1 and L2 are set such that L1≦
It is characterized by having the relationship L2.

[Example] Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a diagram showing the features of the configuration of the present invention.

Shield signal 2 with wiring spacing L1 on both sides of digital signal 1
．． 3 is placed. A signal 4, which needs to avoid the switching noise of the signal 1, is placed at a wiring interval L2 from the shield signal 2. Here shield signal 2
．． By applying a stable constant potential (shield potential) to signal 3, the lines of electric force generated from signal 1 are bent, and the coupling force with signal 4 is reduced, thereby improving noise resistance.

For the shield power supply 5, a power supply voltage (VDD) or ground voltage (VSS) is selected to have a simple configuration, but if the voltage is stable with little fluctuation, the D/A conversion circuit, A/ This is a sample and hold circuit that is often used in analog circuits such as D conversion circuits. The circuit operation will be explained below. 21 is the input voltage VIN and the sampling pulse 23
Pass the transmission game 1-22 every time it comes,
The input voltage 2] is stored in the signal 25 by the capacitor 24 and the operational amplifier 26. This signal 25 is the operational amplifier 26
becomes a voltage follower input and is output to the output voltage 27, and the output voltage 2 remains until the next sampling pulse 23 arrives.
7 is held.

If a high-speed digital signal 29 is placed in close proximity to this sample-and-hold circuit, there is a risk that the accurate input voltage will not be bolded.

FIG. 3 is a timing diagram of the sample and hold circuit when the digital signal 29 is simply arranged.

When the digital signal 29 operates at a timing different from the sampling pulse 23, noise is added to the signal 25 due to the switching noise. Although this noise disappears in a very short time, there is a possibility that the hold voltage of the signal 25 happens to hold a value that deviates from the correct hold voltage. Then, the value of the output voltage 27 also deviates from the correct value.

Therefore, as in the present invention, two signal lines (shield signals) are arranged in parallel on both sides of the digital signal 29, and the SS potential is applied to these two signals as a shield voltage. The potential at this time may be VDD, VSS, or an intermediate potential, but a power supply voltage with little fluctuation is preferable. Furthermore, the shielding effect will be enhanced if the shield voltage is an output voltage of a piezoelectric circuit that is less susceptible to fluctuations in the power supply voltage.

The digital signal 29 and two adjacent silt signals are arranged at a minimum interval L1 according to design rules.

Furthermore, the wider the wiring width of the shield signal, the higher the shielding effect.

Also, the same effect can be obtained whether the wiring material is aluminum, polysilicon, or diffusion.

FIG. 4 is a timing diagram of the sample and hold circuit in the case of the above configuration according to the present invention. During switching of the digital signal 29, the signal 25 is less susceptible to switching noise. Therefore, a correct value appears at the output voltage 27.

Although this embodiment has described reducing the influence from the digital system to the analog system, the configuration of the present invention can also be applied to countermeasures against switching noise between analog systems and switching noise between digital systems. is clear.

It is also effective in the case of a multi-power supply circuit in which low-voltage and high-voltage signals coexist.

Further, this configuration can be easily applied to wiring technology with three or more layers.

The positional relationship between the digital signal wiring, the shielded signal wiring, and the shielded signal wiring in the present invention is such that the distance L between the digital signal wiring and the shielded signal wiring is at least longer than the distance between the digital signal wiring and the shielded signal wiring. For example, the effects of the present invention can be achieved.

[Effects of the Invention] According to the present invention, it is possible to suppress the switching noise of digital signals generated in the same semiconductor integrated circuit from reaching analog circuits that are sensitive to noise by using an extremely simple additional pattern.

Therefore, the present invention provides a means for realizing a highly accurate analog-digital mixed semiconductor integrated device without increasing the chip area.

[Brief explanation of the drawing]

FIG. 1 is a signal arrangement diagram according to the present invention, FIG. 2 is a sample-and-hold circuit diagram, FIG. 3 is a sample-and-hold timing diagram according to the prior art, and FIG. 4 is a sample-and-hold timing diagram according to the configuration of the present invention. That's all

Claims (1)

[Claims] In the same wiring layer, two parallel signals (hereinafter referred to as shield signals) are arranged on both sides at a distance L_1 from a certain signal wiring, and further, a distance L_2 from the shield signal is placed outside one of the shield signals. Another signal wiring (hereinafter referred to as a shielded signal) is arranged, and a constant potential (hereinafter referred to as a shield potential) is applied to the two shield signals, and the L_1 and L_2 have a relationship of L_1≦L_2. A semiconductor integrated device characterized by: