JPH03224232A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To stabilize the potential level of an analog signal without increasing the areas of wirings and without making small the degree of freedom of the layout of a pattern by the shielding effect of a third wiring, which is formed between parallel wirings and is fixed at a constant potential. CONSTITUTION:Parallel wirings are formed of a first wiring 11 for digital signal use consisting of Al and a second wiring 12 for analog signal use consisting of Al. A third wiring 13, which is fixed at a constant potential and consists of Al, is arranged between these parallel wirings via an insulating film 14. An inter-wiring capacity can be minimized by the shielding effect of the wiring 13. That is, as the capacity between the parallel wirings consisting of the wirings 11 and 12 can be minimized by the shielding effect of the wiring 13, the potential level of an analog signal is stabilized and at the same time, in case the shielding effect is applied to an A/D converter, the accuracy of an A/D conversion can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor integrated circuit device, and more specifically, to a semiconductor integrated circuit device in which the potential level of an analog signal is stabilized by an electrical shield. .

(b) Prior Art In recent years, semiconductor integrated circuits have become larger and more highly integrated, increasing the number of wires and shortening the distance between wires.

For this reason, the distributed capacitance that exists between adjacent parallel wirings increases, and the influence of potential changes in the adjacent wirings tends to increase.

In this case, in the digital signal wiring, since the noise resistance of normal digital circuits is relatively high, malfunctions due to the influence of such potential changes are rare.

However, in parallel wiring where digital signal wiring and analog signal wiring are adjacent, there is a problem that such potential changes directly deteriorate the conversion accuracy of, for example, an A/D converter or a D/A converter. In order to avoid this, it was necessary to increase the distance between the wires to an extent that does not deteriorate conversion accuracy, or to devise a pattern layout to avoid parallel wires.

FIG. 5 is a circuit diagram of a conventional A/D converter, and FIG. 4 is a cross-sectional view including the first wiring (1) and second wiring (2) in the circuit of FIG. be.

In the figure, parallel wiring is formed consisting of a first wiring (1) for digital signals and a second wiring (2) for analog signals, and the second wiring (2) is connected to the gate for sample and hold. P-channel transistor T to which signal φ is input
is connected to one input terminal of the comparator via a reference voltage V ref is input to the other input terminal of the comparator.

Capacitance C1 and capacitance C3 are capacitances between the first wiring (1) and the second wiring (2>) and the semiconductor substrate.

There is a capacitance C between the first wiring (1) and the second wiring (2).
3 is formed.

FIG. 6 is a timing chart showing an example of the operation of the circuit shown in FIG. When the sample and hold signal φ is at a low level, the P-channel transistor T is turned on, and as a result, an analog signal is transmitted to one input terminal of the comparator through the second wiring (2), and reaches an analog voltage V.

Next, when the signal ≠ is at a high level, the P-channel transistor T is turned off, and as a result, the analog voltage V is held.

At this time, when the first wiring (1) changes from low level to high level, the second wiring (1) changes due to the influence of inter-wiring capacitance C1.
2) The chisel position is ΔV l= C1/ (CI+ Ct+
c s ) increases by x vo.

Here, ■ is the potential change of the first wiring (1).

If this capacitance CI is large, the value of ΔV becomes large, and an error of Δ■1 occurs in comparison with the reference voltage V ref, resulting in a large error in A/D conversion.

(c) Problems to be Solved by the Invention In conventional semiconductor integrated circuit devices, analog signals change due to the capacitance between parallel wirings where digital signal wiring and analog signal wiring are adjacent. This results in deterioration of conversion accuracy.

Therefore, in order to avoid deterioration in conversion accuracy, it is necessary to increase the distance between the wiring lines, which has the drawback of increasing the wiring area.

Furthermore, avoiding parallel wiring on a pattern layout has the disadvantage that it reduces the degree of freedom in pattern layout and becomes a constraint on automatic placement and wiring.

The present invention was created in view of the above-mentioned problems,
It is an object of the present invention to provide a semiconductor integrated circuit device in which the potential level of an analog signal is stabilized without increasing the wiring area or reducing the degree of freedom in pattern layout.

(d) Means for Solving the Problems The semiconductor integrated circuit device of the present invention provides a first
parallel wiring consisting of the wiring and a second wiring for analog signals, and a third wiring for electrical shielding formed between the parallel wiring with an insulating film interposed therebetween and fixed at a constant potential. It is characterized by comprising:

(*> Effect) As described above, the present invention utilizes the shielding effect of the third wiring formed between parallel wirings via an insulating film and fixed at a constant potential, so that when there is no third wiring, In comparison, the inter-wiring capacitance can be made very small, so the influence of changes in the potential of digital signals can be reduced and the potential level of analog signals can be stabilized.

(F) Example Hereinafter, an example according to the present invention will be described with reference to FIGS. 1 to 3.

FIG. 1 is a cross-sectional view of one embodiment of the present invention, in which a first wiring (11) for digital signals made of aluminum,
The second wiring for analog signals (1
2) form parallel wiring.

A third wiring (13) made of aluminum and fixed at a constant potential is arranged between the parallel wirings with an insulating film (14) interposed therebetween.

FIG. 2 is a circuit diagram of the A/D converter circuit according to the present invention. In FIG. 0, the third wiring (13) is connected to the ground potential, but it may be connected to the power supply potential.

According to such a configuration, the inter-wiring capacitance can be made extremely small due to the shielding effect of the third wiring (13).

FIG. 3 is a timing chart showing an example of the operation of the circuit shown in FIG.

When the sample and hold signal i is at low level, the P-channel transistor T is turned on, and as a result, the second wiring (
At 12), the analog signal is transmitted to one input terminal of the comparator and reaches the analog voltage 1.

Next, when the signal ≠ is at a high level, the Pf channel transistor T is turned off, and as a result, the analog voltage ■ is held.

At this time, when the first wiring (11) changes from low level to 71 high level, the potential V of the second wiring (12) is affected by the inter-wiring capacitance C4, but C6 is much smaller than the above-mentioned C1. Therefore, the change in potential of the second wiring (12) ΔV is very small compared to Δv1. Therefore,
The stability of the analog voltage level V is improved, and it is possible to improve the A/D conversion accuracy.

(G) Effects of the Invention As explained above, according to the present invention, the capacitance between the parallel wiring consisting of the digital signal wiring and the analog signal wiring can be made much smaller than before, so the potential level of the analog signal can be reduced. A stabilized semiconductor integrated circuit can be manufactured.

[Brief explanation of drawings]

FIG. 1 is a sectional view of one embodiment of the present invention, and FIG. 2 is a sectional view of an embodiment according to the present invention.
A circuit diagram of an A/D converter circuit according to the present invention; FIG. 3 is a timing chart showing an example of the operation of the circuit of FIG. 2; FIG. 4 is a sectional view of a conventional example; FIG. 5 is a conventional example. FIG. 6 is a circuit diagram of an A/D converter circuit according to the invention. FIG. 6 is a timing chart showing an example of the operation of the circuit of FIG.

Claims (3)

[Claims] (1) In a semiconductor integrated circuit device having parallel wiring consisting of a first wiring for digital signals and a second wiring for analog signals, the parallel wiring is formed with an insulating film interposed between the parallel wirings, and A semiconductor integrated circuit device comprising: a third wiring for electrical shielding fixed at a potential. (2) The semiconductor integrated circuit device according to claim 1, wherein the third wiring is applied with a power supply potential or a ground potential and is fixed at a constant potential. (3) The semiconductor integrated circuit according to claim 1 or claim 2, wherein the first, second, and third wirings are formed of an aluminum layer or an aluminum alloy layer of the same layer. circuit device.