JPH05166361A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To control ringing and rounding of waveform of address signals, etc., transmitted via an output buffer by intentionally varying the output impedance of the output buffer for the purpose of matching with board impedance, to attain the high speed not only of a memory board but also of a digital system, etc., by reducing delay time in transmitting address signals, etc., and preventing element destruction due to under-shoot and thereby enhancing the reliability. CONSTITUTION:Between the common combined node of a pair of output MOSFET Q1 and Q2 constituting the output buffer OB1 and the output terminal of a circuit, by changing a part of a photomask for example, the wiring of corresponding connection switching part CS11 to CSp2 and CS21 to CSp2 is selectively formed; and thereby plural damping resisters R1 to RDp which are selectively made effective, are provided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, for example, a technique which is particularly effective when used for a memory driver integrated circuit or the like which includes a plurality of output buffers (output circuits) and is mounted on a memory board of a computer system. It is about.

There is a large-capacity memory board mounted with a plurality of memory integrated circuits and used in a digital system such as a computer. These memory boards require an output buffer for transmitting, for example, an address signal supplied from a processor via a system bus to a plurality of memory integrated circuits. The output buffers are collectively mounted as a memory driver integrated circuit in order to improve the mounting efficiency of the memory board, and as illustrated in the output buffer OB1 of FIG. 8, the board impedance RL of the signal line for transmitting the address signal and the like is provided. It includes a matched damping resistor RD.

[Prior Art]

For a memory driver integrated circuit having a plurality of output buffers, see, for example, October 1988,
It is described in "HD62065 Series Data Sheet" issued by Hitachi, Ltd.

[0004]

In the conventional memory driver integrated circuit as described above, each output buffer includes one damping resistor RD, and the resistance value of the damping resistor RD is an average value. It is fixed.
However, the size of the memory board and the number of memory integrated circuits mounted on the memory board differ depending on the user, and the board impedance RL of the signal line for transmitting the address signal and the like changes accordingly. Therefore, for example, when the output impedance RD of each output buffer is smaller than the board impedance RL, ringing of the output signal occurs due to signal reflection and a substantial transmission delay time of the address signal A1out or the like occurs, as illustrated in FIG. tpd
Is longer and the speed of the memory board is limited. Further, the undershoot exceeding the input standard of the memory driver integrated circuit causes the destruction of the circuit element, and the reliability of the memory board and eventually the computer system is deteriorated. On the other hand, when the output impedance RD of the output buffer is larger than the board impedance RL, the case shown in FIG.
As illustrated in FIG. 5, the output signal waveform is blunted and the transmission delay time tpd of the address signal A1out and the like becomes long, which limits the speeding up of the memory board.

An object of the present invention is to provide an output buffer capable of matching the output impedance with the board impedance. Another object of the present invention is to increase the speed of a memory board having a plurality of output buffers, by extension, a digital system, and to improve its reliability.

[0006]

The outline of a typical invention among the inventions disclosed in the present application will be briefly described as follows. That is, a part of the photomask is changed between the common coupling node of the pair of output MOSFETs forming the output buffer and the output terminal of the circuit to selectively form the corresponding wiring, or A plurality of dampings that are selectively enabled respectively by selectively cutting the corresponding fuse means or by selectively turning on the corresponding switch MOSFETs by performing predetermined bonding. The resistors are provided in parallel. Further, the ON resistance is supplied in series with a pair of output MOSFETs forming the output buffer, or between the common coupling node of these output MOSFETs and the output terminal of the circuit through a predetermined external terminal. M selectively changed according to the control voltage
The OSFET is provided.

[0007]

According to the above means, the output impedance of the output buffer can be intentionally changed to match with the board impedance. Therefore, ringing of an address signal or the like transmitted through the output buffer and rounding of the waveform. Can be suppressed. As a result, the transmission delay time of the address signal and the like can be shortened, and the element destruction due to undershoot can be prevented. Therefore, the speed of the memory board and eventually the digital system can be increased and the reliability thereof can be improved.

[0008]

1 is a block diagram of an embodiment of a memory board MB to which the present invention is applied. Also,
FIG. 2 shows a circuit diagram of a first embodiment of the output buffer OB1 included in the memory driver integrated circuit MD of the memory board MB of FIG. 1, and FIG. 3 shows a signal waveform diagram of that embodiment. It is shown. Based on these figures, the outline and characteristics of the configuration and operation of the memory board, memory driver integrated circuit and output buffer of this embodiment will be described. The memory board MB of this embodiment is included in the computer system and is connected to its system bus. The circuit elements of FIGS. 1 and 2 and the circuit elements constituting each block are formed on one semiconductor substrate such as P-type single crystal silicon. In the following circuit diagrams, MOSFETs (metal oxide semiconductor type field effect transistors; collectively referred to as insulated gate type field effect transistors in this specification) are not particularly limited, but all N-channel It is a MOSFET.

In FIG. 1, the memory board MB of this embodiment is basically composed of m memory integrated circuits M1 to Mm. These memory integrated circuits are substantially coupled in parallel and each have a predetermined storage capacity that is alternatively designated according to n-bit address signals A1 to An.

The memory board MB further controls the operation of the memory integrated circuits M1 to Mm and transmits address signals and the like to the memory integrated circuits M1 to Mm.
And a memory driver integrated circuit MD. this house,
The memory control integrated circuit MC receives various control signals, address signals, input data, and the like supplied from the processor of the computer system via the system bus to identify that the memory board MB has been activated, and The address signal, the input data and the like are transmitted to the memory integrated circuits M1 to Mm via the memory driver integrated circuit MD.

On the other hand, the memory driver integrated circuit MD has n
Output buffers OB1 to OBn and n electrostatic protection circuits ESD1 to ESD1 provided corresponding to these output buffers.
And ESDn. The memory driver integrated circuit MD includes input pads PAI1 to PAI1 from the memory control integrated circuit MC.
N-bit address signals A1 to An via PAIn or the like
Etc., and the n-bit address signals A1 to An etc. output from the output pads PAO1 to PAOn are commonly supplied to the memory integrated circuits M1 to Mm via the corresponding signal lines. Each of these signal lines has a predetermined board impedance RL determined by the line length, line width and the like.

In this embodiment, each of the output buffers OB1 to OBn forming the memory driver integrated circuit MD has a power supply voltage (first power supply voltage) of the circuit as represented by the output buffer OB1 in FIG. ) And a ground potential (second power supply voltage) between a pair of output MOSFETs Q1 (first output MOSFET) and Q2 (second output MOSFET). Of these, a non-inverted internal signal a1 or the like is supplied to the gate of the output MOSFET Q1, and an inverted internal signal a1B (here, a so-called inverted signal which is selectively set to a low level when it is enabled) is supplied to the gate of the output MOSFET Q2. Alternatively, the inverted signal line is supplied with the suffix B of its name like the inverted internal signal a1B. The same applies hereinafter). These non-inverted internal signal a1 and inverted internal signal a1B, etc.
It is formed according to the corresponding address signal A1 or the like, and is selectively set to the high level or the low level. The power supply voltage of the circuit is a positive power supply voltage such as + 5V. The specific configuration and characteristics of the output buffer will be described below by taking the output buffer OB1 as an example. Other output buffer OB2
~ OBn should be inferred from the following description.

The output buffer OB1 further includes an output MO.
P damping resistors RD1 provided in parallel between the common coupling node of the SFETs Q1 and Q2, that is, the internal node n1 and the output terminal of the circuit, that is, the internal node n2.
~ RDp included. One of these damping resistors is commonly coupled to the internal node n1 via the corresponding connection switching units CS11 to CSp1, and the other one is connected to the internal node n2 via the corresponding connection switching units CS12 to CSp2.
Commonly connected to. The internal node n2 is coupled to the output pad PAO1 via the corresponding electrostatic protection circuit ESD1 and further connected to the memory integrated circuit M1 via the corresponding signal line.
~ Mm.

Here, the connection switching units CS11 to CSp
1 and CS12 to CSp2 include a pair of wirings selectively formed by changing a part of a photomask used for manufacturing the memory driver integrated circuit MD.
Therefore, the damping resistors RD1 to RDp are selectively made effective on condition that the wiring shown by the solid line in FIG. 2 is formed, and made invalid when the wiring shown by the dotted line is formed. As a result, the output impedance of the output buffer OB1 is selectively switched, and matching with the board impedance RL of the signal line is achieved. When the output impedance RD of the output buffer OB1 and the board impedance RL of each signal line of the memory board MB substantially match, the output signal, that is, the address signal A
As shown in FIG. 3, 1out has a signal waveform substantially along the input signal, that is, the address signal Ain, and ringing due to signal reflection is also suppressed. As a result, the transmission delay time tpd of the address signal or the like can be shortened, and
Since element destruction due to undershoot can be prevented, the speed of the memory board MB and eventually the computer system can be increased, and its reliability can be improved.

FIG. 4 is a circuit diagram of a second embodiment of the output buffer OB1 of the memory driver integrated circuit MD to which the invention is applied. Since the memory driver integrated circuit MD and the output buffer OB1 of the following embodiments basically follow the embodiment of FIG. 2, description will be added only to the different parts.

In FIG. 4, the output buffer OB1 includes a common coupling node of the output MOSFETs Q1 and Q2, that is, an internal node n1 and an output terminal of the circuit, that is, an internal node n.
2 and p damping resistors RD1 to RDp provided in parallel with each other. One of these damping resistors is commonly coupled to internal node n1 via corresponding fuse means F11 to Fp1, and the other is coupled to internal node n2 via corresponding fuse means F12 to Fp2. As a result, the damping resistors RD1 to RDp are
The corresponding fuse means F11 and F12 or Fp1 and Fp2 are selectively made effective on the condition that they are not in the cut state, whereby the same effect as the embodiment of FIG. 2 can be obtained.

FIG. 5 is a circuit diagram of a third embodiment of the output buffer OB1 of the memory driver integrated circuit MD to which the present invention is applied.

In FIG. 5, the output buffer OB1 includes a common coupling node of the output MOSFETs Q1 and Q2, that is, an internal node n1, and an output terminal of the circuit, that is, an internal node n.
2 and p damping resistors RD1 to RDp provided in parallel with each other. One of these damping resistors is commonly coupled to the internal node n1 via the corresponding switch MOSFETs Q3 to Q5, and the other one is connected to the internal node n via the corresponding switch MOSFETs Q6 to Q8.
Combined with two. The gates of the switch MOSFETs Q3 and Q6 to Q5 and Q8 are commonly connected to the corresponding bonding pads PRD1 to PRDp of the memory driver integrated circuit MD. In this embodiment, the bonding pads PRD1 to PRDp are selectively bonded to the bonding pad PVCC, that is, the power supply voltage of the circuit, as shown by the dotted line in FIG.
Therefore, the switch MOSFETs Q3 and Q6 to Q
5 and Q8 are corresponding bonding pads PRD1 to PRD1.
PRDp is selectively and simultaneously turned on, provided that PRDp is bonded to pad PVCC.
As a result, the damping resistors RD1 to RDp are selectively made effective, whereby the same effect as the embodiment of FIG. 2 is obtained.

FIG. 6 is a circuit diagram of a fourth embodiment of the output buffer OB1 of the memory driver integrated circuit MD to which the present invention is applied.

In FIG. 6, the output buffer OB1 includes a MOSFET Q9 (first MOSFET) provided between the common coupling node of the output MOSFETs Q1 and Q2 and the output terminal of the circuit. A predetermined control voltage VRD is supplied to the gate of the MOSFET Q9 from the external terminal TVRD of the memory board MB via the pad PVRD of the memory driver integrated circuit MD. Where the control voltage VR
D is set to an arbitrary level between the power supply voltage of the circuit and the ground potential. Further, the MOSFET Q9 is an output MOSF.
It is formed to have a smaller size than ETQ1 and ETQ2, and its ON resistance is selectively changed according to the control voltage VRD, thereby acting as a substantial damping resistance. As a result, the output impedance RD of the output buffer OB1 is selectively changed according to the control voltage VRD, whereby the same effect as the embodiment of FIG. 2 can be obtained.

FIG. 7 shows a circuit diagram of a fifth embodiment of the output buffer OB1 of the memory driver integrated circuit MD to which the present invention is applied.

In FIG. 7, the output buffer OB1 includes MOSFETs Q10 (second MOSFET) and Q1 (first output MOSFET) provided in series between the power supply voltage of the circuit and the output terminal of the circuit, and the output buffer OB1 of the circuit. Another pair of MOSFETs Q2 (second output MOSFET) and Q provided in series between the output terminal and the ground potential of the circuit
11 (third MOSFET). Of these, the non-inverted internal signal a1 and the inverted internal signal a1B are supplied to the gates of the output MOSFETs Q1 and Q2, respectively. Further, the MOSFETs Q10 and Q11 are both formed to have a smaller size than the output MOSFETs Q1 and Q2, and the gate thereof has the control voltage VRD from the external terminal TVRD of the memory board MB via the pad PVRD of the memory driver integrated circuit MD. Is supplied. As a result, the MOSFETs Q10 and Q11 have a predetermined ON resistance according to the level of the control voltage VRD, and act as a substantial damping resistance. As a result, the output impedance RD of the output buffer OB1
Is selectively changed according to the control voltage VRD, and thereby the same effect as that of the embodiment of FIG. 2 can be obtained.

As shown in the above embodiments, the present invention is applied to a semiconductor integrated circuit device such as a memory driver integrated circuit which constitutes a memory board of a computer system or the like and has a plurality of output buffers. The following effects can be obtained. That is, (1) a pair of output MOSFETs forming an output buffer
Between the common coupling node of the circuit and the output terminal of the circuit, a plurality of damping resistors that are selectively made effective by parallel formation of corresponding wiring by partially changing the photomask are connected in parallel. By providing the output buffer, the output impedance of the output buffer can be selectively switched. (2) A pair of output MOSFETs forming an output buffer
The output impedance of the output buffer can be selected by providing a plurality of damping resistors in parallel between the common coupling node of the circuit and the output terminal of the circuit, which are selectively enabled by disconnecting the corresponding fuse means. It is possible to obtain the effect that it can be switched to each other. (3) A pair of output MOSFETs forming an output buffer
A plurality of damping resistors are selectively connected in parallel to each other between the common coupling node and the output terminal of the circuit and the corresponding switch MOSFETs are selectively turned on. By providing it, there is an effect that the output impedance of the output buffer can be selectively switched. (4) A pair of output MOSFETs forming an output buffer
A MOSFET whose on-resistance is selectively changed according to a control voltage supplied through an external terminal is provided between the common coupling node of the circuit and the output terminal of the circuit to selectively output the output impedance of the output buffer. The effect that it can be switched is obtained. (5) A pair of output MOSFETs forming an output buffer
The effect that the output impedance of the output buffer can be selectively switched by providing a pair of MOSFETs whose ON resistance is selectively changed according to the control voltage supplied through the external terminal in series with Is obtained.

(6) According to the above items (1) to (5), the output impedance of the output buffer is matched with the board impedance of the memory board or the like, and ringing of the address signal transmitted through the output buffer or the like is performed. The effect that the rounding of the waveform can be suppressed is obtained. (7) According to the above item (6), it is possible to reduce the transmission delay time of the address signal and the like and prevent the element destruction due to the undershoot. (8) According to the above item (7), it is possible to obtain the effect that the speed of the memory board and eventually the digital system can be increased and the reliability thereof can be improved.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in FIG. 1, the memory board MB can mount an integrated circuit other than the memory control integrated circuit MC, the memory driver integrated circuit MD, and the memory integrated circuits M1 to Mm, and the block configuration thereof is according to this embodiment. Not restricted. 2 and 4 to 7,
The output MOSFET Q1 can be replaced with, for example, a P-channel MOSFET that receives the inverted internal signal a1B at its gate. Further, in these embodiments, the output impedance of the output buffer is selectively switched by selectively enabling the p damping resistors RD1 to RDp arranged in parallel. In addition, one or more damping resistors that are selectively made effective may be further added. In each output buffer, a plurality of switch MOSFETs provided corresponding to the damping resistors RD1 to RDp, a plurality of wirings are selectively formed, a plurality of fuse means are selectively cut, or a plurality of bondings are selectively made. A decoder that decodes a control signal of a plurality of bits selectively formed by being performed to selectively turn on the switch MOSFET may be included. In this case, the required number of connection switching units, fuse means, bonding pads, etc. can be reduced, and a plurality of output buffers can be shared. The memory driver integrated circuit MD includes electrostatic protection circuits ESD1 to ECLn.
Need not be included and can be formed integrally with the memory control integrated circuit MC. Various embodiments can be adopted for the specific circuit configuration of the output buffer, the polarity of the power supply voltage, the conductivity type of the MOSFET, and the like.

In the above description, the case where the invention made by the present inventor is mainly applied to the memory driver integrated circuit constituting the memory board of the computer system which is the background field of application has been described, but the invention is not limited thereto. However, the present invention can be applied to, for example, a memory driver integrated circuit forming a memory board of another system, a driver integrated circuit including a plurality of output buffers, a memory integrated circuit, a gate array integrated circuit, and the like. The present invention can be widely applied to semiconductor integrated circuit devices including at least an output buffer.

[0027]

EFFECT OF THE INVENTION A pair of output MOs forming an output buffer.
Between the common connection node of the SFET and the output terminal of the circuit,
Corresponding to the fact that the corresponding wiring is selectively formed by changing a part of the photomask, or the corresponding fuse means is selectively cut, or predetermined bonding is performed. Switch M
When the OSFET is selectively turned on, a plurality of damping resistors that are selectively effective are provided in parallel. Further, the ON resistance is supplied in series with a pair of output MOSFETs forming the output buffer, or between the common coupling node of these output MOSFETs and the output terminal of the circuit through a predetermined external terminal. A MOSFET is provided that is changed according to the control voltage. As a result, the output impedance of the output buffer can be intentionally changed and matching with the board impedance can be achieved, so that ringing of the address signal or the like transmitted through the output buffer and rounding of the waveform can be suppressed. As a result, the transmission delay time of the address signal and the like can be shortened, and the element destruction due to undershoot can be prevented. Therefore, the speed of the memory board and eventually the digital system can be increased and the reliability thereof can be improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of a memory board to which the present invention is applied.

FIG. 2 is a circuit diagram showing a first embodiment of an output buffer included in the memory driver integrated circuit of the memory board of FIG.

FIG. 3 is a signal waveform diagram showing an embodiment of the output buffer of FIG.

FIG. 4 is a circuit diagram showing a second embodiment of the output buffer included in the memory driver integrated circuit to which the present invention is applied.

FIG. 5 is a circuit diagram showing a third embodiment of the output buffer included in the memory driver integrated circuit to which the present invention is applied.

FIG. 6 is a circuit diagram showing a fourth embodiment of the output buffer included in the memory driver integrated circuit to which the present invention is applied.

FIG. 7 is a circuit diagram showing a fifth embodiment of the output buffer included in the memory driver integrated circuit to which the present invention is applied.

FIG. 8 is a circuit diagram showing an example of a conventional output buffer.

9 is a signal waveform diagram showing an example of the output buffer of FIG.

10 is a signal waveform diagram showing another example of the output buffer of FIG.

[Explanation of symbols]

MB ... Memory board, MC ... Memory control integrated circuit, MD ... Memory driver integrated circuit, OB1 to OB
n ... Output buffer, ESD1 to ESDn ... Electrostatic protection circuit, M1 to Mm ... Memory integrated circuit, RD ...
-Output impedance, RL ... Board impedance. RD1 to RDp ... Damping resistance, CS11 to
CSp1, CS12 to CSp2 ... Connection switching unit,
F11 to Fp1, F12 to Fp2 ... Fuse means,
Q1-Q11 ... N-channel MOSFET.

Claims (7)

[Claims] 1. A semiconductor integrated circuit device comprising an output circuit whose output impedance is selectively switched. 2. The output circuit comprises first and second output MOSs provided in series between the first and second power supply voltages.
A plurality of FETs that are provided in parallel between the common coupling node of the first and second output MOSFETs and the output terminal of the circuit and are selectively formed by forming corresponding wirings. 2. The semiconductor integrated circuit device according to claim 1, further comprising: 3. The output circuit comprises first and second output MOSs provided in series between the first and second power supply voltages.
It is selectively made effective by selectively disconnecting the corresponding fuse means provided in parallel between the FET and the common coupling node of the first and second output MOSFETs and the output terminal of the circuit. 2. The semiconductor integrated circuit device according to claim 1, including a plurality of damping resistors. 4. The output circuit comprises first and second output MOSs provided in series between the first and second power supply voltages.
A plurality of FETs are provided in parallel between the FET and the common coupling node of the first and second output MOSFETs and the output terminal of the circuit, and the corresponding bonding is selectively performed to make the plurality of selectively effective. The semiconductor integrated circuit device according to claim 1, further comprising a damping resistor. 5. The output circuit comprises first and second output MOSs provided in series between the first and second power supply voltages.
A first FET is provided between the FET and the commonly connected node of the first and second output MOSFETs and the output terminal of the circuit, and its ON resistance is changed according to a control voltage supplied from a predetermined external terminal. The semiconductor integrated circuit device according to claim 1, further comprising a MOSFET. 6. The first output M, wherein the output circuit is provided in series between a first power supply voltage and an output terminal of the circuit.
A second MO whose OSFET and its ON resistance are changed according to a control voltage supplied via a predetermined external terminal.
It includes an SFET, a second output MOSFET provided in series between the output terminal of the circuit and the second power supply voltage, and a third MOSFET whose ON resistance is changed according to the control voltage. The semiconductor integrated circuit device according to claim 1. 7. The semiconductor integrated circuit device includes a plurality of the output circuits, and is a memory driver integrated circuit constituting a memory board of a digital system. The semiconductor integrated circuit device according to claim 2, claim 3, claim 4, claim 5, or claim 6.