JPH0516215B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a packet buffer device in a packet communication system.

[Conventional technology]

In a packet communication system, by sending and receiving data packets between communication devices via a packet buffer, the communication devices can be operated asynchronously, that is, with independent clocks, and the reliability of the entire system against clock failure can be improved. I can do it.

A ring configuration is often used for this packet buffer, and in a ring configuration buffer, a data write circuit and a data read circuit have independent address pointers for the buffer, and write and read packets independently. perform the following actions. The access address of a buffer in a ring configuration has no logical end, and the physical start address is read after the physical end address. This allows the entire buffer memory to be used effectively.

In a buffer device in which the packet write circuit and read circuit operate independently in this way, a communication mechanism for flow control is provided between the packet write circuit and read circuit in order to avoid overflow and underflow of the buffer memory. It is necessary to provide Conventional buffer devices mainly employ the methods shown in () and () below to realize such a flow control function.
) A method in which the write address of the packet write circuit and the read address of the packet read circuit for the buffer are directly compared. However, since it is difficult to constantly compare two registers that operate asynchronously, the addresses at the time when one packet is processed in both circuits are held in separate registers and their values are compared. When they match, an empty signal indicating that the buffer is empty is transmitted to the packet read circuit, and when the write address is closer than a predetermined distance from the read address, a blockage signal is transmitted to the packet write circuit. method.

) Install a counter that indicates the number of packets in the buffer, add it when writing a packet, subtract it when reading a packet, and send a zero signal indicating that the number of packets in the buffer is 0 to the packet readout circuit. A method in which a blocking signal indicating that the number of packets exceeds a predetermined value is transmitted to the packet writing circuit.

[Problem that the invention seeks to solve]

However, in a buffer device in which the packet write circuit and the read circuit operate independently, the two circuits are not directly coupled, so the data in the buffer, the write or read pointer,
Alternatively, if an accidental error occurs in one of the control counters, it is difficult to detect the error and restore the original state. Therefore, as an indirect means of detecting a failure, there is a method of counting the length of the read packet and determining an abnormal state when the length exceeds the maximum length of a normal packet. If two packets are concatenated and the total length of the concatenated packets does not exceed the maximum normal packet length, no abnormal condition is detected.

Furthermore, in the method using address comparison described above, if the address data held in the packet write address register has an error, the point at which the packet readout circuit is stopped due to address comparison is lost, and there is a possibility of runaway.

Furthermore, in the method using the packet number counter described above, there is a possibility that an error in the counter or an error in the data in the buffer will cause a discrepancy between the counter value and the number of packets accumulated in the buffer. be. If the counter does not reach 0 even though the packet readout circuit has read all the packets in the buffer, the readout circuit does not stop reading packets and sometimes reads old data written in the buffer. However, the above-mentioned indirect fault detection means cannot reliably detect faults. Also, if the counter reaches zero before the read circuit has read all packets in the buffer, the read circuit will stop reading packets, but no fault condition will be detected.

A buffer management means that cannot reliably detect an abnormal state as described above has the problem that a highly reliable buffer device cannot be realized.

SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable packet buffer device that can reliably detect accidental errors and restore a normal state.

[Means for solving problems]

The packet buffer device of the present invention includes a ring-configured buffer memory that temporarily stores packets, writes packets arriving from the outside into the buffer memory, outputs a write end pulse when writing of one packet is completed, and finally outputs a write end pulse. a packet write circuit that holds and outputs the final address when writing of the packet is completed; a packet write circuit that reads the packet from the buffer memory and sends it to the outside; and outputs a read end pulse when reading of one packet is completed; It has a packet read circuit that holds and outputs the final address when packet reading is finally completed, and an up-down counter that is added by the write end pulse and subtracted by the read end pulse, and the contents of this counter are a counter circuit that outputs a zero signal indicating that the packet is 0 to the packet reading circuit; an address comparison circuit that performs subtraction and outputs an address match signal indicating that the operation result is 0, and outputs a blockage signal to the packet write circuit when the operation result is less than a preset threshold; a coincidence signal inspection circuit that inspects the address coincidence signal when the zero signal is output, and sends a reset signal to the packet write circuit, the packet read circuit, and the counter circuit when a mismatch is found in the inspection result; It is composed of:

[Effect]

FIG. 1 is a block diagram showing the configuration of a packet buffer device according to the present invention. In FIG. 1, 11 is a buffer memory in a ring configuration, 12 is a counter circuit, 13 is an address comparison circuit, 14 is a packet write circuit, 15 is a packet read circuit, 16 is a coincidence signal check circuit, and 17 is a circuit for receiving packets from outside. 18 indicates a terminal for sending packets to the outside.

When one packet comes in from the terminal 17, the packet write circuit 14 writes to the buffer memory 11, and when the write is completed, it latches the write address and transmits it to the address comparison circuit 13, and also sends a write end pulse to the counter circuit 12. give. The packet reading circuit 15 monitors the signal input from the counter circuit 12 when the counter value is 0, and starts reading packets from the buffer memory 11 when this signal is off.
The read data is sent to the terminal 18. Furthermore, when the packet readout circuit 15 completes the readout of one packet, it latches the readout address and transmits it to the address comparison circuit 13, and also provides a readout end pulse to the counter circuit 12.

In this configuration, the counter circuit 12 is incremented (+1) at the end of packet writing and subtracted (-1) at the end of packet reading, so that it always indicates the number of packets in the buffer memory 11 during normal operation. When the content of the counter is 0, the counter circuit 12 outputs a zero signal to the packet reading device 15 to stop the packet reading operation.
On the other hand, the address comparison circuit 13 always measures the distance between the final write address input from the packet write circuit 14 and the final read address input from the packet read circuit 15, and measures the distance between the write address and the read address. If the distance is closer than a preset value stored inside the address comparison circuit, a blocking signal is output to the packet write circuit 14 to stop the packet write operation.

As described above, during normal operation, a zero signal is sent to the packet write circuit, and a zero signal is sent to the packet read circuit 15.
By applying a blockage signal to the buffer memory 11, write/read flow control for the buffer memory 11 can be realized. By the way, during normal operation, the number of packets stored in the buffer memory 11 and the contents of the counter circuit 12 match, so
When the content of the counter circuit 12 is 0, that is, a zero signal is given to the coincidence signal check circuit 16, there is no packet in the buffer memory 11, the final write address and the final read address match, and the address The address match signal should have been supplied from the comparison circuit 13 to the match signal test circuit 16. Conversely, if an accidental error occurs in any one of the data in the buffer, the write or read pointer, or the control counter, and a contradiction occurs between the buffer memory 11 and the counter circuit 12, the counter circuit When the content of 12 becomes 0 and a zero signal is applied to the coincidence signal checking circuit 16, the final write address and the final read address do not match, and no address coincidence signal is detected. Therefore, the coincidence signal inspection circuit 16 detects a failure state by inspecting the address coincidence signal when the zero signal is on, and sends a reset signal to the packet write circuit 14, packet read circuit 15,
and can be fed back to the counter circuit 12. By resetting the counter circuit 12 with a reset signal and initializing the write address pointer of the packet write circuit 14 and the read address pointer of the packet read circuit 15, the normal state can be restored.

〔Example〕

Hereinafter, an embodiment of the main circuit of the packet buffer device of the present invention shown in FIG. 1 will be described with reference to the drawings.

FIG. 2 is a block diagram of one embodiment of the address comparison circuit 13. In FIG. 2, 21 is a modulo subtraction circuit, 22 is a subtraction circuit, 23 is a zero judgment circuit, 24 is a fixed register, 25 is a terminal for inputting write address data from the packet write circuit 14, and 26 is a packet read circuit 15. 27 is a terminal for transmitting the output of the zero determination circuit as an address match signal to the match signal checking circuit 16; 28 is a terminal for transmitting the output of the sign bit of the operation result of the subtraction circuit 22 as a block signal to the packet. A terminal for transmitting data to the write circuit 14 is shown.

The modulo subtraction circuit 21 is a subtraction circuit that subtracts the write address data given from the packet write circuit 15 via the terminal 25 from the read address data given from the packet read circuit 14 via the terminal 26. In this case, the physical address space length of the buffer memory 11 is added, the logical distance between the two addresses on the buffer memory 11 is calculated, and the result is output to the subtraction circuit 22 and the zero determination circuit 23. The subtraction circuit 22 performs signed subtraction to subtract the value stored in the fixed register 24 from the output of the modulo subtraction circuit 21, and outputs the sign bit to the terminal 28. The zero judgment circuit 23 is a modulo subtraction circuit 21
When the output is 0, ON is output to the terminal 27, and when it is not 0, OFF is output to the terminal 27.

FIG. 3 is a block diagram of one embodiment of the counter circuit 12. In FIG. 3, 31 is a counter;
32 is a zero determination circuit; 33 is a terminal for inputting a write end pulse from the packet write circuit 14; 34
35 is a terminal for inputting the read end pulse from the packet reading circuit 15, and 35 is a terminal for inputting the output of the zero judgment circuit 32 to the packet reading circuit and the coincidence signal checking circuit 1.
6 is a terminal for outputting to 6, 36 is a coincidence signal inspection circuit 16
This shows the terminal that inputs the reset signal coming from.

The counter 31 is an up-down counter that adds up with pulses input from a terminal 33 and subtracts with pulses input from a terminal 34, and outputs its contents to the zero determination circuit 32. Further, the counter 31 is reset by a reset signal coming from the coincidence signal checking circuit 16 via a terminal 36. The zero determination circuit 32 outputs ON to the terminal 35 when the output of the counter 31 is 0, and outputs OFF when the output is not 0.

FIG. 4 is a block diagram showing one embodiment of the coincidence signal checking circuit 16. In Figure 4, 41 is
AND circuit, 42 is a NOT circuit, 43 is a terminal for inputting the signal coming from the address comparison circuit 13, 4
4 is a terminal for inputting the address match signal coming from the counter circuit 12; 45 is an address comparison circuit 13 using the output of the AND circuit 41 as a reset signal;
Packet writing device 14, packet reading device 1
5 shows the feedback terminal.

〔Effect of the invention〕

According to the present invention, the buffer memory includes a counter that counts the number of packets accumulated in the buffer memory, and a circuit that compares a write address pointer and a read address pointer for the buffer, and a zero signal output from the counter and an address comparison circuit. By comparing the address matching signal outputted from the address matching signal, it is possible to reliably check for errors that occur by chance, and it is possible to provide a highly reliable buffer device.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a packet buffer device according to the present invention, FIG. 2 is a block diagram of an embodiment of the address comparison circuit of FIG. 1, and FIG. 3 is an embodiment of the counter circuit of FIG. 1. block diagram,
FIG. 4 is a block diagram of one embodiment of the coincidence signal checking circuit of FIG. 1. 11...Buffer memory, 12...Counter circuit,
13... Address comparison circuit, 14... Packet write circuit, 15... Packet read circuit, 16... Match signal inspection circuit, 21... Modulo subtraction circuit, 22... Subtraction circuit, 23, 23... Zero judgment circuit, 24... Fixed register , 31...Counter.

Claims (1)

[Claims] 1 A ring-configured buffer memory that temporarily stores packets, writes packets arriving from the outside into the buffer memory, outputs a write end pulse when writing of one packet is completed, and finally writes a write end pulse when writing of one packet is completed. A packet write circuit holds and outputs the final address at the time, reads the packet from the buffer memory and sends it to the outside, outputs a read end pulse when reading of one packet is completed, and finally reads the packet. It has a packet readout circuit that holds and outputs the final address at the time of completion, and an up-down counter that is incremented by the write end pulse and subtracted by the read end pulse, and it is determined that the content of this counter is 0. A counter circuit outputs a zero signal indicating to the packet reading circuit, and subtracts the final address at the time when the packet reading was completed last from the final address at the time when the writing of the packet was completed last, and the calculation result is 0. an address comparison circuit that outputs an address match signal indicating that the packet is a packet, and outputs a blockage signal to the packet write circuit when the calculation result falls below a preset threshold; A packet buffer device characterized in that it has a coincidence signal inspection circuit that inspects the address coincidence signal and sends a reset signal to the packet write circuit, the packet read circuit, and the counter circuit when a mismatch is found in the inspection result. .