JPH0516182B2 - - Google Patents

Info

Publication number
JPH0516182B2
JPH0516182B2 JP57149309A JP14930982A JPH0516182B2 JP H0516182 B2 JPH0516182 B2 JP H0516182B2 JP 57149309 A JP57149309 A JP 57149309A JP 14930982 A JP14930982 A JP 14930982A JP H0516182 B2 JPH0516182 B2 JP H0516182B2
Authority
JP
Japan
Prior art keywords
reflectance
reflected light
amount
laser
detected
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP57149309A
Other languages
Japanese (ja)
Other versions
JPS5940548A (en
Inventor
Mikio Hongo
Takeoki Myauchi
Takao Kawanabe
Morio Inoe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP57149309A priority Critical patent/JPS5940548A/en
Publication of JPS5940548A publication Critical patent/JPS5940548A/en
Publication of JPH0516182B2 publication Critical patent/JPH0516182B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5252Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
    • H01L23/5254Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/525Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections
    • H01L23/5256Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive
    • H01L23/5258Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body with adaptable interconnections comprising fuses, i.e. connections having their state changed from conductive to non-conductive the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Description

【発明の詳細な説明】 本発明は、プログラム配線層上に多層の透明絶
縁膜を被覆した半導体集積回路に対して、レーザ
光を照射してプログラム配線部を接続または切断
のプログラミングを行う半導体集積回路における
プログラミング方法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit in which programming is performed to connect or disconnect a program wiring section by irradiating a laser beam onto a semiconductor integrated circuit whose program wiring layer is coated with a multilayer transparent insulating film. It relates to programming methods in circuits.

集積回路内の配線の一部を切断または接続(短
絡)することにより、製作済みの集積回路チツプ
にプログラム(回路変更)を行うことができる。
従来、このプログラム(回路変更)は、例えば読
み出し専用メモリ(ROM)のプログラム、ある
いは最近ではメモリ素子の欠陥セルの救済に利用
されている。これらの従来法として (1) レーザにより外部から光学的にエネルギを与
えてPoly−SiあるいはAl、ニクロム等の配線
の特定部を切断する。
A fabricated integrated circuit chip can be programmed (circuit modification) by cutting or connecting (shorting) some of the wiring within the integrated circuit.
Conventionally, this programming (circuit modification) has been used, for example, to program a read-only memory (ROM) or, more recently, to repair defective cells in a memory element. These conventional methods include (1) applying optical energy from the outside using a laser to cut a specific portion of wiring made of poly-Si, Al, nichrome, etc.;

(2) レーザにより外部から光学的にエネルギを与
えて、即ちPoly−Si配線(低抵抗部)の一部
に設けられた高抵抗部(不鈍物が何もドープさ
れていなくても良い)とその周辺部にレーザを
照射して高抵抗部を低抵抗化することより接続
する。
(2) A high-resistance part (doped with no dull material) is provided in a part of the Poly-Si wiring (low-resistance part) by applying optical energy from the outside with a laser. The connection is made by irradiating the area around the area with a laser to reduce the resistance of the high-resistance area.

が知られている。It has been known.

いずれの方法でも、ROM等の場合には、あら
かじめ決められた部分、欠陥セルの救済に利用す
る場合にはメモリテスタ等での試験結果から決ま
る部分に、あらかじめ設定された条件、即ち一定
のレーザ・パワーおよび一定のパルス数を照射し
て、切断、接続等の処理を行つている。しかし、
一般的にはレーザが照射される部分であるPoly
−Si、Al、ニクロム等で形成された配線は、
SiO2、PSG(リンガラス)、Si3N4、SiO等の単層
あるいはそれらの複数の層からなるパツシベーシ
ヨン膜で覆われた状態で処理され、必要に応じて
特に切断を行つた場合には最終的なパツシベーシ
ヨン膜を形成する。ここで、配線部の上に形成さ
れたパツシベーシヨン膜を通してレーザを照射す
ると、パツシベーシヨン膜厚の変動により、干渉
効果のため反射率が大きく変動し、結果的に配線
部に入力するレーザパワーが変動してしまう。そ
のため、切断を行う場合には、一定条件でレーザ
を照射しても、配線が切断できなかつたり、基板
にまでダメージが生じたりしてしまう。また接続
を行う場合には一定条件でレーザを照射しても、
接続できなかつたり、配線が切断されてしまつた
りして、歩留りが低いという問題があつた。これ
を防ぐために、パツシベーシヨン膜厚を一定にす
る努力がなされているが、極めて困難であるのが
現状である。
In either method, the laser is applied under preset conditions, i.e., to a predetermined part in the case of ROM, etc., or to a part determined from the test results of a memory tester, etc. when used for repairing defective cells. - Processes such as disconnection and connection are performed by irradiating power and a certain number of pulses. but,
Poly, which is the part that is generally irradiated with the laser.
-Wiring made of Si, Al, Nichrome, etc.
When processed while covered with a passivation film consisting of a single layer or multiple layers of SiO 2 , PSG (phosphorus glass), Si 3 N 4 , SiO, etc., and especially when cutting is performed as necessary, Form the final passivation film. Here, when a laser is irradiated through the passivation film formed on the wiring part, the reflectance changes greatly due to the interference effect due to variations in the passivation film thickness, and as a result, the laser power input to the wiring part changes. I end up. Therefore, when cutting, even if the laser is irradiated under certain conditions, the wiring may not be cut or the substrate may be damaged. Also, when making connections, even if the laser is irradiated under certain conditions,
There was a problem that the yield was low due to failure to connect or disconnection of wiring. In order to prevent this, efforts have been made to keep the passivation film thickness constant, but it is currently extremely difficult.

プログラム配線層上に多層の透明絶縁膜を被覆
した半導体集積回路を製造する際、生じる多層の
透明絶縁膜の膜厚等の特性のバラツキに対して常
に一定のレーザ光エネルギをプログラム配線部に
与えて下層にダメージを与えることなく、高品質
のプログラミングを行つて、高歩留まりの半導体
集積回路が得られるようにした半導体集積回路に
おけるプログラミング方法を提供することにあ
る。即ち、本発明は、上記目的を達成するため
に、プログラム配線層上に多層の透明絶縁膜を被
覆した半導体集積回路に対して、予め、上記プロ
グラム配線部と同一断面構造を有する反射率測定
部に、上記プログラム配線部に照射するレーザ光
と同一波長のレーザ光を上記測定部分が溶融しな
い充分に低いパワーでもつて照射して、上記反射
率測定部に照射するレーザ光の光量を照射光量検
出器で検出すると共に上記反射率測定部から上記
多層の透明絶縁膜の特性の変動に基づいて多重干
渉によつて得られる反射光量を反射光量検出器で
検出し、上記照射光量検出器で検出される照射光
量と上記反射光量検出器で検出される反射光量と
の関係からプログラム配線部の反射率を求め、こ
の求めれたプログラム配線部の反射率からこのプ
ログラム配線部に吸収される実効エネルギが上記
多層の透明絶縁膜の特性の変動にかかわらず常に
一定になるようにレーザ出力を調整してプログラ
ム配線部に照射して接続または切断のプログラミ
ングを行うことを特徴とする半導体集積回路にお
けるプログラミング方法である。なお、上記反射
率測定部が、プログラミングを行なうプログラム
配線部であつてもよいことは明らかである。ま
た、本発明は、プログラム配線層上に多層の透明
絶縁膜を被覆した半導体集積回路に対して、予
め、上記プログラム配線部と同一断面構造を有し
て設けられたターゲツトマーク部に、上記プログ
ラム配線部に照射するレーザ光と同一波長のレー
ザ光を上記ターゲツトマーク部が溶融しない充分
に低いパワーでもつて照射して、上記ターゲツト
マーク部に照射するレーザ光の光量を照射光量検
出器で検出すると共に上記測定部分から上記多層
の透明絶縁膜の特性の変動に基づいて多重干渉に
よつて得られる反射光量を反射光量検出器で検出
し、ターゲツトマークとその周囲の反射率の相異
によつて上記反射光量検出器で検出される照射光
量と上記反射光量検出器で検出されるターゲツト
マークの像からそのターゲツトマークの位置を検
出し、この検出されたターゲツトマークの位置を
基準にしてプログラミングしようとするプログラ
ミング配線部を位置決めし、上記照射光量検出器
で検出される照射光量と上記反射光量検出器で検
出される反射光量との関係からプログラム配線部
の反射率を求め、この求められたプログラム配線
部の反射率からこのプログラム配線部に吸収され
る実効エネルギが上記多層の透明絶縁膜の特性の
変動にかかわらず常に一定になるようにレーザ出
力を調整して上記位置決めされたプログラム配線
部に照射してプログラミングを行なうことを特徴
とする半導体集積回路におけるプログラミング方
法である。
When manufacturing a semiconductor integrated circuit in which a multilayer transparent insulating film is coated on a program wiring layer, constant laser light energy is always applied to the program wiring part to compensate for variations in characteristics such as the thickness of the multilayer transparent insulating film. It is an object of the present invention to provide a programming method for a semiconductor integrated circuit, which enables high-yield semiconductor integrated circuits to be obtained by performing high-quality programming without damaging underlying layers. That is, in order to achieve the above object, the present invention provides a semiconductor integrated circuit in which a multilayer transparent insulating film is coated on a program wiring layer, in which a reflectance measuring section having the same cross-sectional structure as the program wiring section is provided in advance. Then, a laser beam of the same wavelength as the laser beam irradiated to the program wiring section is irradiated at a sufficiently low power that the measurement section is not melted, and the amount of the laser beam irradiated to the reflectance measurement section is detected. At the same time, the amount of reflected light obtained by multiple interference is detected by the reflectance measurement section based on the variation in the characteristics of the multilayer transparent insulating film, and the amount of reflected light obtained by the reflected light amount detector is detected by the irradiated light amount detector. The reflectance of the program wiring section is determined from the relationship between the amount of irradiated light and the amount of reflected light detected by the reflected light amount detector, and from this determined reflectance of the program wiring section, the effective energy absorbed by this program wiring section is calculated as described above. A programming method for semiconductor integrated circuits, characterized in that the laser output is adjusted so that it is always constant regardless of changes in the characteristics of a multilayer transparent insulating film, and the laser output is irradiated onto a program wiring section to perform connection or disconnection programming. be. Note that it is clear that the reflectance measurement section may be a program wiring section that performs programming. Further, the present invention provides a semiconductor integrated circuit in which a multilayer transparent insulating film is coated on a program wiring layer, in which a target mark portion having the same cross-sectional structure as the program wiring portion is provided with the program wiring layer. A laser beam of the same wavelength as the laser beam irradiated to the wiring section is irradiated at a sufficiently low power that the target mark section is not melted, and the amount of the laser beam irradiated to the target mark section is detected by an irradiation light amount detector. At the same time, a reflected light amount detector detects the amount of reflected light obtained from multiple interference based on variations in the characteristics of the multilayer transparent insulating film from the measurement area, and detects the difference in reflectance between the target mark and its surroundings. The position of the target mark is detected from the amount of irradiation light detected by the reflected light amount detector and the image of the target mark detected by the reflected light amount detector, and programming is performed based on the detected position of the target mark. The reflectance of the program wiring section is determined from the relationship between the amount of irradiated light detected by the irradiation light amount detector and the amount of reflected light detected by the reflected light amount detector, and the determined programming wiring section is positioned. The laser output is adjusted so that the effective energy absorbed by the program wiring section based on the reflectance of the area is always constant regardless of variations in the characteristics of the multilayer transparent insulating film, and irradiation is applied to the positioned program wiring section. This is a programming method for a semiconductor integrated circuit, which is characterized in that programming is performed using the following methods.

以下、図に従つて本発明の実施例について説明
する。まず、本発明をレーザによる配線接続に適
用した場合について延べる。第1図は一般的な配
線接続部の構造を示す図であり、Si基板1に被着
したSiO2膜2により基板1と絶縁された2つの
n+形Poly−Si(多結晶シリコン層)3,4が極め
て高抵抗の(例えば109Ω/口以上)Poly−Si層
(不純物がドープされていなくとも良い)からな
るi層5を介在して対向している配線構造を持
ち、それらの上に絶縁膜8、絶縁膜9、絶縁膜1
0が形成されている。ここでn+形層3,4およ
びi層5は厚さが100〜500nmでありn+形層3,
4はリンまたはヒ素が、不純物濃度1018/cm3以上
にドープされている。また絶縁膜8は、厚さが20
〜200nm(200〜2000Å)のSiO2膜、絶縁膜9は
1〜10mol%のリンを含む100〜1000nm(0.1〜
1μm)の厚さのリンガラス膜(PSG膜)、絶縁膜
10は厚さが500〜4000nm(0.5〜4μm)のSiO2
またはSiOまたはSiNの単独あるいはそれらの複
数の膜から成つている最終的な絶縁膜(Final
Passiuasion膜)である。第1図に示した配線接
続部に対して、絶縁膜8,9,10に対して十分
に透明な波長のレーザ光7をn+形Poly−Si層3,
4およびi層に照射すると適正なレーザ条件のも
とでは、i層5にn+形層3,4またはPSG膜9
のどちらか、あるいは両方からリンが拡散しi層
5は低抵抗化する。この時、絶縁膜8,9,10
には、ほとんど損傷を与えない。ここで、適正な
レーザ条件とは、例えばQスイツチYAGレーザ
の第2高調波を用いて、1〜2パルスでPoly−
Si配線部を断線に致らしめるパワー密度の1/2の
パワー密度で数パルス〜数10パルス照射する条件
である。また、ここで、低抵抗化により接続され
た状態とは、高抵抗Poly−Si層(i層)5の抵
抗値が105Ω以下に低下した状態を言う。これは
レーザ照射前の高抵抗Poly−Si層(i層)5の
抵抗値が105Ω以上と比較すると104以上の変化で
あり、完全に短絡状態、即ち接続状態と見なして
差支えない。
Embodiments of the present invention will be described below with reference to the drawings. First, a case where the present invention is applied to wiring connection using a laser will be described. Figure 1 is a diagram showing the structure of a general wiring connection section, in which two wires are insulated from the substrate 1 by a SiO 2 film 2 deposited on the Si substrate 1.
n + type Poly-Si (polycrystalline silicon layers) 3 and 4 are interposed with an i-layer 5 made of an extremely high resistance (for example, 10 9 Ω/or more) Poly-Si layer (doped with no impurity). It has a wiring structure facing each other, and on top of them are an insulating film 8, an insulating film 9, and an insulating film 1.
0 is formed. Here, the n + type layers 3 and 4 and the i layer 5 have a thickness of 100 to 500 nm, and the n + type layers 3 and 4 have a thickness of 100 to 500 nm.
No. 4 is doped with phosphorus or arsenic to an impurity concentration of 10 18 /cm 3 or more. Further, the insulating film 8 has a thickness of 20
~200nm (200~2000Å) SiO2 film, insulating film 9 is 100~1000nm (0.1~2000Å) containing 1~10mol% phosphorus.
The insulating film 10 is a SiO 2 film with a thickness of 500 to 4000 nm (0.5 to 4 μm).
or a final insulating film consisting of SiO or SiN or a combination of these films.
Passiuasion membrane). For the wiring connection part shown in FIG.
4 and the i layer, under appropriate laser conditions, the i layer 5 is exposed to the n + type layers 3, 4 or the PSG film 9.
Phosphorus is diffused from either or both of them, and the resistance of the i-layer 5 is reduced. At this time, insulating films 8, 9, 10
causes almost no damage. Here, appropriate laser conditions include, for example, using the second harmonic of a Q-switched YAG laser to generate poly-
The condition is to irradiate several pulses to several tens of pulses at a power density that is 1/2 of the power density that would cause the Si wiring part to break. Moreover, here, the state of connection due to low resistance refers to the state where the resistance value of the high resistance Poly-Si layer (i layer) 5 has decreased to 10 5 Ω or less. This is a change of 10 4 or more compared to the resistance value of the high-resistance Poly-Si layer (i-layer) 5 of 10 5 Ω or more before laser irradiation, and can be regarded as a completely short-circuited state, that is, a connected state.

しかしながら、半導体チツプを製造する工程に
おいて、絶縁膜8,9,10の膜厚を常に一定に
保つことは極めて困難である。ここで絶縁膜8,
9,10の膜厚が変化した場合について述べる。
絶縁膜10をSiO2の単層膜とすると、絶縁膜8,
9,10ともに波長5324Å(YAGレーザの第2
高調波)に対して屈折率1.45と考えて差支えな
く、吸収も無視できるから、絶縁膜8,9,10
を全体として一層の絶縁膜と考えることができ
る。この時、YAGレーザの第2高調波を上記構
造に垂直に入射した場合の絶縁膜の膜厚と多重干
渉によつて生じる反射率の変化をSiの屈折率を
4.3として第2図に示す。この図からわかる様に
λ/2n=1836Åを周期に反射率は約11%〜39%の範 囲で変化する。(λは入射光の波長,nは絶縁膜
の屈折率)即ち、一定の出力のレーザ7を照射し
た場合、実効的にPoly−Si層3,4,5で吸収
されるレーザ・エネルギは照射エネルギに対して
61%〜89%の範囲で変化することを示している。
However, in the process of manufacturing semiconductor chips, it is extremely difficult to always keep the thickness of the insulating films 8, 9, and 10 constant. Here, the insulating film 8,
The case where the film thicknesses of Nos. 9 and 10 change will be described.
When the insulating film 10 is a single layer film of SiO 2 , the insulating film 8,
Both 9 and 10 have a wavelength of 5324 Å (the second YAG laser
It is safe to assume that the refractive index is 1.45 for harmonics), and the absorption can be ignored, so the insulating films 8, 9, 10
can be considered as a single layer of insulating film as a whole. At this time, when the second harmonic of the YAG laser is incident perpendicularly to the above structure, the change in reflectance caused by the thickness of the insulating film and multiple interference can be expressed as the refractive index of Si.
4.3 is shown in Figure 2. As can be seen from this figure, the reflectance changes in the range of approximately 11% to 39% with a period of λ/2n = 1836 Å. (λ is the wavelength of the incident light, n is the refractive index of the insulating film) In other words, when the laser 7 with a constant output is irradiated, the laser energy that is effectively absorbed by the Poly-Si layers 3, 4, and 5 is for energy
It shows that it varies in the range of 61% to 89%.

次に絶縁膜10として窒化シリコン膜の単層膜
を用いた場合について述べる。窒化シリコンの
5324Åに対する屈折率は約2.0である。前述のご
とく絶縁膜8と絶縁膜9は膜厚がそれぞれ20〜
200nm、100〜1000nmであるが光学的には同質
であり、120〜1200nmの絶縁膜と考えることが
できる。また絶縁膜10は500〜4000nmである。
ここで絶縁膜8,9の合計を640nm 絶縁膜1
0を1400nmとする。第3図に絶縁膜8,9を
640nmに固定して、絶縁膜10が1200〜1600nm
の範囲で変化した場合、第4図に絶縁膜10を
1400nmに固定して、絶縁膜8,9が400〜800n
mの範囲で変化した場合の多重干渉によつて生じ
る反射率の変化を示す。各々、12%〜61%、0.4
%〜61%の範囲で変化している。
Next, a case where a single layer film of silicon nitride film is used as the insulating film 10 will be described. silicon nitride
The refractive index for 5324 Å is approximately 2.0. As mentioned above, the thickness of the insulating film 8 and the insulating film 9 is 20~
Although they are 200 nm and 100 to 1000 nm, they are optically the same and can be considered as an insulating film of 120 to 1200 nm. Further, the thickness of the insulating film 10 is 500 to 4000 nm.
Here, the total thickness of insulating films 8 and 9 is 640 nm Insulating film 1
0 is 1400nm. Insulating films 8 and 9 are shown in Figure 3.
Fixed at 640nm, insulating film 10 is 1200-1600nm
If the change is within the range of
Fixed at 1400nm, insulating films 8 and 9 are 400~800n
3 shows changes in reflectance caused by multiple interference when changing over a range of m. respectively, 12% to 61%, 0.4
It varies from % to 61%.

これらの膜厚と反射率の関係は、例えば、裳華
房 金原、藤原 共著「薄膜(応用物理学選書
3)」P.227から求めた。即ち、絶縁膜8,9,1
0の膜厚により反射率が1%以下から61%まで変
化する。このことは、レーザ出力が一定でも、
Poly−Si層3,4,5への実効的なレーザ光入
力は39%〜99%の間で変化することを意味してお
り、例えばレーザ光出力を1μJ一定で照射しても
Poly−Si層3,4,5で吸収されるエネルギは
0.39μJ〜0.99μJの範囲でばらつく。このことは、
レーザ出力が常に一定でも、吸収エネルギが少な
いため、低抵抗化が起こらない場合や、吸収エネ
ルギが多すぎてPoly−Si層3,4,5が損傷を
受ける場合が生じ、接続の歩留りが低いという問
題が生じる。しかも、第3図および第4図に示し
た変化は一方の膜厚を一定にした場合の特性であ
るが、実際には両方の膜厚が同時に変化するた
め、それぞれが10nm変化するだけで、反射率が
大きく変化する場合もあり、さらにレーザ出力の
バラつきも考慮すると、歩留り低下は著しい。
The relationship between film thickness and reflectance was obtained from, for example, "Thin Films (Applied Physics Selection 3)" co-authored by Shokabo Kanehara and Fujiwara, p. 227. That is, insulating films 8, 9, 1
Depending on the film thickness of 0, the reflectance changes from less than 1% to 61%. This means that even if the laser output is constant,
This means that the effective laser light input to the Poly-Si layers 3, 4, and 5 varies between 39% and 99%. For example, even if the laser light output is constant at 1 μJ,
The energy absorbed by Poly-Si layers 3, 4, and 5 is
It varies in the range of 0.39μJ to 0.99μJ. This means that
Even if the laser output is always constant, the absorption energy is small, so the resistance may not be lowered, or the absorption energy may be too large and the Poly-Si layers 3, 4, and 5 may be damaged, resulting in a low connection yield. A problem arises. Moreover, the changes shown in Figures 3 and 4 are the characteristics when one film thickness is kept constant, but in reality, both film thicknesses change at the same time, so each changes by only 10 nm. In some cases, the reflectance changes greatly, and when the variation in laser output is also taken into account, the yield decreases significantly.

本発明のレーザ処理方法を示す。半導体メモリ
チツプ内に設けられた配線接続部あるいは、配線
接続部と同一構造(レーザ照射の対象となる
Poly−Si層3,4,5の下部構造は任意で良い)
部分に、使用するレーザと同一レーザでかつ出力
が十分に低い状態で照射し、レーザ発振出力から
配線接続部に照射されたレーザエネルギを求め
(途中の光学系の透過率は予めわかつている)、配
線接続部、あるいはそれと同一構造の部分からの
反射光量から、反射率を算出する。この反射率か
ら配線接続部で吸収された実効的なレーザ・エネ
ルギを求め、実効的なレーザエネルギが最適条件
となる様にレーザ発振器出力を調整するか、途中
の光学系で配線接続部に照射される出力を調整し
た後、目的の配線接続部に照射する。照射される
レーザ・スポツト径が配線接続部と同等あるいは
小さい場合には、配線接続部自体で反射率を求
め、スポツト径が大きい場合には、チツプ内の特
定部に設けた反射率測定部で反射率を求める。
1 shows a laser processing method of the present invention. A wiring connection part provided in a semiconductor memory chip or having the same structure as a wiring connection part (subject to laser irradiation)
The lower structure of Poly-Si layers 3, 4, and 5 may be arbitrary)
irradiate the area with the same laser as the one being used with a sufficiently low output, and calculate the laser energy irradiated to the wiring connection part from the laser oscillation output (the transmittance of the optical system in the middle is known in advance) , the reflectance is calculated from the amount of reflected light from the wiring connection portion or a portion having the same structure as the wiring connection portion. From this reflectance, determine the effective laser energy absorbed by the wiring connection, and either adjust the laser oscillator output so that the effective laser energy is optimal, or irradiate the wiring connection with an intermediate optical system. After adjusting the output, irradiate the target wiring connection. If the diameter of the laser spot to be irradiated is the same as or smaller than the wiring connection, the reflectance is measured at the wiring connection itself, and if the spot diameter is large, the reflectance measurement unit installed at a specific part of the chip is used to measure the reflectance. Find the reflectance.

第5図に本発明によれば半導体メモリ・チツプ
を示す。数mm×数mmのSi基板11上に数万から数
10万個のメモリセル12(予備メモリセルも含
む)が形成され、チツプ周辺にはボンデイング用
パツド13が形成されている。また、メモリセル
12内に欠陥が発見された場合に、予備メモリに
切り換えるための選択回路14が設けられてお
り、その一部は第1図に示す構造を持つている。
そして、選択回路に近い部分に反射率測定部15
が形成されている。この反射率測定部15は、第
6図に示す様に第1図に示した配線接続部と同じ
断面構造、即ちSi基1とSiO2膜2上にPoly−Si
層16(この場合は、n+形層でもi層でも良い)
が、照射されるレーザ7のスポツト径と、位置件
め精度を考慮した大きさ、例えば20μm口あるい
は20μmθに形成され、その上には第1図と同様
に、絶縁膜8,9,10が形成されている。
FIG. 5 shows a semiconductor memory chip according to the present invention. Several tens of thousands to several
100,000 memory cells 12 (including spare memory cells) are formed, and bonding pads 13 are formed around the chip. Further, a selection circuit 14 is provided for switching to a spare memory when a defect is found in the memory cell 12, and a part of the selection circuit 14 has the structure shown in FIG.
Then, a reflectance measurement section 15 is provided near the selection circuit.
is formed. As shown in FIG . 6, this reflectance measurement section 15 has the same cross-sectional structure as the wiring connection section shown in FIG.
Layer 16 (in this case, it may be an n + type layer or an i layer)
is formed to a size that takes into consideration the spot diameter of the laser 7 to be irradiated and the positioning accuracy, for example, 20 μm opening or 20 μm θ, and on top of it, insulating films 8, 9, and 10 are formed as shown in FIG. It is formed.

次に第5図に示したチツプにレーザを照射する
場合の手順について述べる。第7図に、本発明を
実施するに最適なレーザ光学系を示す。ここでは
説明に必要な部分のみを示してある。レーザ発振
器17から発振したレーザ光18を対物レンズ1
9に入射するために光路を曲げるミラー20,2
1およびX−Y方向にレーザ光18を走査するた
めの例えばカルバノミラー22(図中では一方向
だけを示す)およびミラー20からの透過光量を
検出するための光検出器23,ミラー24からの
反射光量を検出するための光検出器25,X−Y
ステージ26上に載置されたウエハまたはチツプ
27に照射するレーザ出力を調整するための透過
光量調整器28,および、ウエハまたはチツプ2
7の位置決め、光量検出器23,25の信号から
レーザ光量・反射率等の演算、透過光量調整器2
8の制御、およびレーザのON−OFF等の制御を
行うための制御装置29から成つている。
Next, the procedure for irradiating the chip shown in FIG. 5 with a laser will be described. FIG. 7 shows a laser optical system most suitable for implementing the present invention. Only the parts necessary for explanation are shown here. The laser beam 18 oscillated from the laser oscillator 17 is transmitted through the objective lens 1.
Mirror 20, 2 that bends the optical path to enter 9
For example, a carbano mirror 22 (only one direction is shown in the figure) for scanning the laser beam 18 in the X-Y directions, a photodetector 23 for detecting the amount of transmitted light from the mirror 20, and reflection from the mirror 24. Photodetector 25, X-Y for detecting the amount of light
A transmitted light amount adjuster 28 for adjusting the laser output to irradiate the wafer or chip 27 placed on the stage 26, and the wafer or chip 27
7 positioning, calculation of laser light intensity, reflectance, etc. from the signals of light intensity detectors 23 and 25, transmitted light intensity adjuster 2
8 and a control device 29 for controlling ON/OFF of the laser and the like.

まず、X−Yステージ26上に置かれたウエハ
またはチツプ27に対して、X−Y−θの位置決
め調整を行つた後、第5図に示した反射率測定部
15に対して十分に低い出力でレーザ光18を照
射する。この時ミラー20を透過した光量を光量
検出器23で検出する。ミラー20の透過率が予
めわかつていれば、発振したレーザ光18の出力
を知ることができる。また透過光量調整器28で
十分に低い出力で調整してあるが、透過率がわか
れば、ミラー21,24,22,および対物レン
ズ19の反射率、あるいは透過率を考慮して、ウ
エハまたはチツプ27に照射されたレーザ出力が
算出できる。一方、ウエハまたはチツプ27から
反射したレーザ光は対物レンズ19を透過し、ミ
ラー22,24を反射して光量検出器25に入力
し、反射光量を検出する。この時、対物レンズ1
9の透過率ミラー22,24の反射率がわかれ
ば、ウエハまたはチツプ27からの反射光量を算
出することができる。これら、実際に照射された
レーザ光量と反射光量から、反射率を算出するこ
とは容易である。
First, after performing X-Y-θ positioning adjustment on the wafer or chip 27 placed on the X-Y stage 26, the reflectance measurement unit 15 shown in FIG. Laser light 18 is irradiated with the output. At this time, the amount of light transmitted through the mirror 20 is detected by a light amount detector 23. If the transmittance of the mirror 20 is known in advance, the output of the oscillated laser beam 18 can be known. Although the transmitted light amount adjuster 28 is used to adjust the output to a sufficiently low level, if the transmittance is known, it is possible to remove the wafer or chip by considering the reflectance or transmittance of the mirrors 21, 24, 22 and the objective lens 19. The laser output irradiated to 27 can be calculated. On the other hand, the laser beam reflected from the wafer or chip 27 passes through the objective lens 19, reflects off the mirrors 22 and 24, and enters the light amount detector 25, where the amount of reflected light is detected. At this time, objective lens 1
If the reflectance of the transmittance mirrors 22 and 24 of 9 is known, the amount of reflected light from the wafer or chip 27 can be calculated. It is easy to calculate the reflectance from the amount of laser light actually irradiated and the amount of reflected light.

例えば、ミラー20の反射率r20が98%(透過
率は1−r20)、ミラー21の反射率r21が99%ミラ
ー24の反射率r24が10%、ガルバノミラー22
の反射率r22が99%、対物レンズ19の透過率t19
が80%として、光量検出器23で、0.2μJ検出し
たとすれば、レーザ発振出力Po=0.2/1−r20=10μJ が得られる。透過光量調整器28が透過率t=28
=2%に設定してあれば、実際にウエハまたはチ
ツプ27に照射されたレーザ光量P′はP′=Po・
r20・r21・(1−r24)・r22・t19・t28=0.138μJと求
まる。一方、光量検出器25での光量がP″=
0.00546μJと検出されれば、反射光量はP=
P″/t19・r22・r24=0.0689μJと算出できる。故にウ
エ ハまたはチツプ27での反射率RはP″/P′=0.5即ち 50%と算出できる。ここで第1図に示した配線接
続部に対して、低抵抗に必要かつ十分なレーザエ
ネルギが0.5μJであるならば、レーザ発振器17
の出力を一定のまま、透過光量調整器28の透過
率を t28=0.5/P0・r20・(1−r24)・r22・t13・(1−
R) =0.1446(14.46%)に設定して、予め決定されて
いる、あるいはメモリテスタで検査した結果に基
づいて、第5図に示した選択回路14内の配線接
続部にレーザを照射する。これにより、絶縁膜
8,9,10による反射率の変化の影響を全く受
けずに、常に一定のエネルギがPoly−Si層3,
4,5に入力する様にレーザを照射することがで
きる。1チツプ内の処理が終了したら、他のチツ
プでも同じ手順でくり返す。この場合、1チツプ
内の絶縁膜8,9,10の膜厚のばらつきは、無
視できる程度であり、また、1チツプを処理する
のに要する時間内でのレーザ発振器17の出力の
変化も無視できるものとして、1チツプにつき1
ケ所の測定を行つている。しかし、レーザ発振器
17の発振出力が短時間内に変動する場合には、
レーザを発振するたび毎に光量検出器23での検
出光量から、透過光量調整器28の透過率を調整
することにより、ウエハまたはチツプ27に照射
されるレーザ・エネルギを常に一定にすることは
可能である。(ただし、パルス間のばらつきを補
正することはできない。) 1チツプ内での絶縁膜8,9,10の膜厚のば
らつきが無視できない場合は、第8図に示し様に
選択回路14内の配線接続部周辺あるいは、膜厚
の変化が無視できる程度の位置に反射率測定部1
5′あるいは15を設け、レーザ処理が必要な部
分に一番近い部分で、接続を行うたびに反射率を
測定することにより、より完全に絶縁膜8,9,
10の膜厚のばらつきによる反射率の変化を補正
することができる。
For example, the reflectance r 20 of the mirror 20 is 98% (transmittance is 1 - r 20 ), the reflectance r 21 of the mirror 21 is 99%, the reflectance r 24 of the mirror 24 is 10%, and the galvano mirror 22
The reflectance of r 22 is 99%, and the transmittance of objective lens 19 is t 19
is 80% and the light amount detector 23 detects 0.2 μJ, the laser oscillation output Po=0.2/1−r 20 =10 μJ is obtained. The transmitted light amount adjuster 28 has a transmittance t= 28
= 2%, the amount of laser light P' actually irradiated onto the wafer or chip 27 is P' = Po・
r20r21・(1− r24 )・r22t19t28 =0.138μJ. On the other hand, the light amount at the light amount detector 25 is P″=
If 0.00546μJ is detected, the amount of reflected light is P=
It can be calculated that P″/t 19 ·r 22 ·r 24 =0.0689 μJ. Therefore, the reflectance R at the wafer or chip 27 can be calculated as P″/P′=0.5, that is, 50%. Here, for the wiring connection shown in FIG. 1, if the necessary and sufficient laser energy for low resistance is 0.5 μJ, then the laser oscillator 17
While keeping the output constant, the transmittance of the transmitted light amount adjuster 28 is t 28 = 0.5/P 0・r 20・(1−r 24 )・r 22・t 13・(1−
R) = 0.1446 (14.46%) and irradiates the wiring connection portion in the selection circuit 14 shown in FIG. 5 with a laser, based on a predetermined value or the result of testing with a memory tester. As a result, constant energy is always applied to the Poly-Si layer 3, without being affected by changes in reflectance due to the insulating films 8, 9, and 10.
It is possible to irradiate the laser so as to input it to 4 and 5. When the processing in one chip is completed, repeat the same procedure for other chips. In this case, variations in the film thickness of the insulating films 8, 9, and 10 within one chip are negligible, and changes in the output of the laser oscillator 17 within the time required to process one chip are also ignored. As much as possible, 1 per chip
Measurements are being taken at several locations. However, if the oscillation output of the laser oscillator 17 fluctuates within a short time,
By adjusting the transmittance of the transmitted light amount adjuster 28 based on the amount of light detected by the light amount detector 23 each time the laser is oscillated, it is possible to always keep the laser energy irradiated to the wafer or chip 27 constant. It is. (However, variations between pulses cannot be corrected.) If variations in the thickness of the insulating films 8, 9, and 10 within one chip cannot be ignored, the variation in the selection circuit 14 as shown in FIG. Reflectance measurement unit 1 is installed near the wiring connection or in a position where changes in film thickness can be ignored.
5' or 15 and measure the reflectance each time a connection is made at the part closest to the part that requires laser processing, the insulating films 8, 9,
Changes in reflectance due to variations in film thickness of 10 can be corrected.

この他、各チツプ位置の精位置決め、あるいは
チツプの原点位置検出に用いるターゲツト・マー
クを用いた反射率測定が可能である。即ちチツプ
上の特定位置に、第7図に示したX−Yステージ
26(ステツプ・アンド・リピータも含む)によ
るチツプ・サイズに相当する移動量の精度範囲に
十分入る大きさの短形、あるいはL字型のPoly
−Si層を形成し、Poly−Si層上をX−Y2方向に
レーザを走査(十分に低いエネルギで)して、
Poly−Si層とその周辺の反射率の差から、ター
ゲツト・マーク位置を検出する方法がとられてい
る。例えば第9図に示すターゲツト・マークの断
面に対して、断面に平行な方向にレーザ18を走
査すると、第7図に示した光学系の光量検出器2
5の信号として、第10図に示す信号が得られ
る。ここでターゲツト・マークの断面は第6図に
示した反射率測定部と全く同一でも良い。この得
られた信号からターゲツト・マークの中心、例え
ば、低反射部と高反射部の信号の中間値を示す位
置の中心からを求め(X−Y2方向について)、こ
の中心をチツプの原点として、選択回路内の配線
接続部をチツプの設計寸法から求めることができ
るが、このターゲツト・マーク上で得られた反射
光量から、絶縁膜8,9,10の反射率を求める
ことができることは前記した通りである。また、
Poly−Si層16とその周辺からの反射光量の差
が明確に得られない場合もある(周辺部において
SiO2膜2が加わることによつて反射光量がPoly
−Si層16上と同程度になる場合)が、第11図
に示す様に、Poly−Si層16の周辺に反射率が
異なる層30(例えばAI)をPoly−Si層16と
接して、あるいは絶縁膜8あるいは8,9、ある
いは8,9,,10を介して形成しても、(第11
図はPoly−Si層16と接している場合を示す)
あるいは、第12図に示す様に、十分大きな
Poly−Si層16の中央部上に、Poly−Si層16
と接して、あるいは絶縁膜8あるいは8,9、あ
るいは8,9,,10を介して形成しても(第1
2図は絶縁膜8,9を介して形成された場合を示
す)、十分に目的(位置決めおよび反射率の測定)
を達することができる。
In addition, it is possible to perform reflectance measurement using a target mark used for precise positioning of each chip position or for detecting the origin position of a chip. That is, at a specific position on the chip, there is a rectangular shape that is large enough to fall within the accuracy range of the amount of movement corresponding to the chip size by the X-Y stage 26 (including the step and repeater) shown in FIG. 7, or L-shaped Poly
- form a Si layer, scan a laser (with sufficiently low energy) on the Poly-Si layer in the X-Y2 direction,
A method is used to detect the target mark position from the difference in reflectance between the poly-Si layer and its surroundings. For example, when the cross section of the target mark shown in FIG. 9 is scanned with the laser 18 in a direction parallel to the cross section, the light amount detector 2 of the optical system shown in FIG.
As the signal No. 5, the signal shown in FIG. 10 is obtained. Here, the cross section of the target mark may be exactly the same as the reflectance measuring section shown in FIG. From this obtained signal, find the center of the target mark, for example, from the center of the position indicating the intermediate value of the signals of the low reflection part and the high reflection part (with respect to the X-Y direction), and use this center as the origin of the chip. The wiring connections in the selection circuit can be determined from the design dimensions of the chip, and as mentioned above, the reflectance of the insulating films 8, 9, and 10 can be determined from the amount of reflected light obtained on this target mark. That's right. Also,
In some cases, the difference in the amount of reflected light from the Poly-Si layer 16 and the surrounding area cannot be clearly obtained (in the surrounding area
By adding SiO 2 film 2, the amount of reflected light is
- the same level as on the Si layer 16), as shown in FIG. Alternatively, the (11th
The figure shows the case where it is in contact with the Poly-Si layer 16)
Alternatively, as shown in Figure 12, a sufficiently large
Poly-Si layer 16 is placed on the center of Poly-Si layer 16.
The first
(Figure 2 shows the case where the film is formed through insulating films 8 and 9), and is fully suitable for the purpose (positioning and measurement of reflectance).
can be reached.

また、十分に大きなPoly−Si(不純物をドープ
していない層)に矩形あるいはL字形に不純物を
ドープした領域を形成するか、あるいは十分大き
なPoly−Si(不純物拡散層)に矩形あるいはL字
形のi層(不純物をドープしていない属)を形成
してもi層と不純物拡散層の反射率の差から、同
じ目的を達することができる。
In addition, a rectangular or L-shaped impurity-doped region is formed in a sufficiently large poly-Si (an undoped layer), or a rectangular or L-shaped region is formed in a sufficiently large poly-Si (an impurity diffusion layer). Even if an i-layer (non-doped with impurities) is formed, the same purpose can be achieved due to the difference in reflectance between the i-layer and the impurity diffusion layer.

ただし、第11図の場合、得られる信号は周辺が
高く中央部が低くなり、また第12図の場合中央
部が高く周辺が低くなる。求める反射光量は第1
1図の場合は中央部、第12図の場合は周辺部で
ある。また、第9図〜第12図に示したターゲツ
トマークを利用する実施例は第5図に示した反射
率測定部を設けた場合と同様に1チツプにつき、
1or2ケ所の測定で1チツプ全体の処理を行うもの
である。
However, in the case of FIG. 11, the obtained signal is high at the periphery and low at the center, and in the case of FIG. 12, the signal obtained is high at the center and low at the periphery. The amount of reflected light to seek is the first
In the case of FIG. 1, it is the central part, and in the case of FIG. 12, it is the peripheral part. In addition, in the embodiment using the target mark shown in FIGS. 9 to 12, as in the case of providing the reflectance measurement section shown in FIG.
The entire chip is processed by measuring one or two locations.

以上、本発明をROMへの書き込み、あるいは
半導体メモリの欠陥セル救済を目的とした配線接
続に適用した場合について説明して来た。しか
し、同様の目的のため、配線切断を行うために適
用した場合も全く同じ効果が得られる。即ち反射
率が高すぎると切断部への実効的なレーザ・エネ
ルギが低くなり切断できなかつたり、反射率が低
すぎると、切断部への実効的なレーザ・エネルギ
が高すぎ、基板に損傷を与えたりするが、本発明
を適用すれば、チツプ毎あるいは切断部毎に反射
率を測定して、最適なレーザ・エネルギで、配線
部に入力することができ、その歩留りを向上する
ことが可能であることは明らかである。
So far, the case where the present invention is applied to wiring connection for the purpose of writing to ROM or relieving defective cells in semiconductor memory has been described. However, when applied to cut wiring for the same purpose, exactly the same effect can be obtained. That is, if the reflectance is too high, the effective laser energy to the cut will be too low and the cut will not be possible, and if the reflectance is too low, the effective laser energy to the cut will be too high and damage the substrate. However, by applying the present invention, it is possible to measure the reflectance of each chip or each cut section and input the optimum laser energy to the wiring section, thereby improving the yield. It is clear that

この他、半導体素子の製造工程において、部分
的なあるいは全面のレーザ・アニーリング(イオ
ン注入した部分の結晶欠陥の回復)、部分的な結
晶状態の変化(多結晶あるいはアモルフアスから
単結晶へ、単結晶から多結晶あるいはアモルフア
スへ)等のレーザ処理を行う際にも、光学的に性
質の異なる膜を介してレーザ処理を行う場合に、
干渉による実効的な入力エネルギーの変化を補正
して、高品質なレーザ処理を行うことができるこ
とは明らかである。
In addition, in the manufacturing process of semiconductor devices, partial or full laser annealing (recovery of crystal defects in the ion-implanted area), partial change of crystal state (from polycrystalline or amorphous to single crystal, single crystal (from polycrystalline to amorphous), and when laser processing is performed through films with optically different properties,
It is clear that high quality laser processing can be achieved by correcting for changes in effective input energy due to interference.

また、用いるレーザとして、本実施例ではQス
イツチYAGレーザの第2高調波を用いた場合に
ついて説明して来たが、それに限定されるもので
はなく、パルス発振、CW(連続)発振によらず、
また波長にもよらず、レーザ処理に用いるレーザ
で実際の反射率が測定可能であることは明らかで
ある。
In addition, although the second harmonic of a Q-switched YAG laser has been described in this embodiment as the laser to be used, the present invention is not limited to this, and may be either pulsed oscillation or CW (continuous) oscillation. ,
Furthermore, it is clear that the actual reflectance can be measured with the laser used for laser processing, regardless of the wavelength.

以上述べて来た様に、本発明によればプログラ
ム配線層上に多層の透明絶縁膜を被覆した半導体
集積回路を製造する際、生じる多層の透明絶縁膜
の膜厚等の特性のバラツキに対してレーザ光の干
渉効果による滅衰の変動を補正して常に一定のレ
ーザ光エネルギをプログラム配線部に与えて下層
にダメージを与えることなく、高品質のプログラ
ミングを行つて、高歩留まりの半導体集積回路が
得られる効果を奏する。
As described above, according to the present invention, when manufacturing a semiconductor integrated circuit in which a multilayer transparent insulating film is coated on a program wiring layer, variations in characteristics such as the thickness of the multilayer transparent insulating film can be prevented. By correcting fluctuations in attenuation due to laser beam interference effects and always applying a constant laser beam energy to the programming wiring section, high-quality programming can be performed without damaging the underlying layer, and semiconductor integrated circuits with high yields can be achieved. It produces the effect that can be obtained.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の適用対象である配線接続部の
構成図、第2図〜第4図は膜厚が変化した場合の
反射率の変化を示す図、第5図は本発明の半導体
メモリチツプを示す図、第6図は反射率測定部の
断面図、第7図は本発明方法を実施するための光
学系構成図、第8図は本発明の別な実施例である
半導体メモリチツプを示す図、第9図はターゲツ
トマークの断面図、第10図はターゲツトマーク
から得られる信号の一例を示す図、第11図、及
び第12図は別なターゲツト・マークの断面図。 1……Si基板、2……SiO2膜、3,4……n+
形Poly−si層、5……i層、8,9,10……絶
縁膜、15,15′,15″……反射率測定部、1
7…レーザ発振器、18……レーザ光、19……
対物レーズ、23,25……光量検出器、28…
…透過光量調整器、16……Poly−Si層、30
……反射率の異なる層。
FIG. 1 is a configuration diagram of a wiring connection part to which the present invention is applied, FIGS. 2 to 4 are diagrams showing changes in reflectance when film thickness changes, and FIG. 5 is a diagram of a semiconductor memory chip of the present invention. 6 is a cross-sectional view of the reflectance measuring section, FIG. 7 is a diagram showing the configuration of an optical system for carrying out the method of the present invention, and FIG. 8 is a diagram showing a semiconductor memory chip which is another embodiment of the present invention. 9 is a sectional view of a target mark, FIG. 10 is a diagram showing an example of a signal obtained from the target mark, and FIGS. 11 and 12 are sectional views of other target marks. 1...Si substrate, 2...SiO 2 film, 3, 4...n +
Poly-si layer, 5...I layer, 8, 9, 10...Insulating film, 15, 15', 15''...Reflectance measurement section, 1
7... Laser oscillator, 18... Laser light, 19...
Objective laser, 23, 25... Light amount detector, 28...
...Transmitted light amount adjuster, 16...Poly-Si layer, 30
...layers with different reflectance.

Claims (1)

【特許請求の範囲】 1 プログラム配線層上に多層の透明絶縁膜を被
覆した半導体集積回路に対して、予め、上記プロ
グラム配線部と同一断面構造を有する反射率測定
部に、上記プログラム配線部に照射するレーザ光
と同一波長のレーザ光を上記測定部分が溶融しな
い充分に低いパワーでもつて照射して、上記反射
率測定部に照射するレーザ光の光量を照射光量検
出器で検出すると共に上記反射率測定部から上記
多層の透明絶縁膜の特性の変動に基づいて多重干
渉によつて得られる反射光量を反射光量検出器で
検出し、上記照射光量検出器で検出される照射光
量と上記反射光量検出器で検出される反射光量と
の関係からプログラム配線部の反射率を求め、こ
の求められたプログラム配線部の反射率からこの
プログラム配線部に吸収される実効エネルギが上
記多層の透明絶縁膜の特性の変動にかかわらず常
に一定になるようにレーザ出力を調整してプログ
ラム配線部に照射して接続または切断のプログラ
ミングを行なうことを特徴とする半導体集積回路
におけるプログラミング方法。 2 上記反射率測定部が、プログラミングを行な
うプログラミング配線部であることを特徴とする
特許請求の範囲第1項記載の半導体集積回路にお
けるプログラミング方法。 3 プログラム配線層上に多層の透明絶縁膜を被
覆した半導体集積回路に対して、予め、上記プロ
グラム配線部と同一断面構造を有して設けられた
ターゲツトマーク部に、上記プログラム配線部に
照射するレーザ光と同一波長のレーザ光を上記タ
ーゲツトマーク部が溶融しない充分に低いパワー
でもつて照射して、上記ターゲツトマーク部に照
射するレーザ光の光量を照射光量検出器で検出す
ると共に上記測定部から上記多層の透明絶縁膜の
特性の変動に基づいて多重干渉によつて得られる
反射光量を反射光量検出器で検出し、ターゲツト
マークとその周囲の反射率の相異によつて上記反
射光量検出器で検出される照射光量と上記反射光
量検出器で検出されるターゲツトマークの像から
そのターゲツトマークの位置を検出し、この検出
されたターゲツトマークの位置を基準にしてプロ
グラミングしようとするプログラミング配線部を
位置決めし、上記照射光量検出器で検出される照
射光量と上記反射光量検出器で検出される反射光
量との関係からプログラム配線部の反射率を求
め、この求められたプログラム配線部の反射率か
らこのプログラム配線部に吸収される実効エネル
ギが上記多層の透明絶縁膜の特性の変動にかかわ
らず常に一定になるようにレーザ出力を調整して
上記置決めされたプログラム配線部に照射してプ
ログラミングを行なうことを特徴とする半導体集
積回路におけるプログラミング方法。
[Scope of Claims] 1. For a semiconductor integrated circuit in which a multilayer transparent insulating film is coated on a program wiring layer, a reflectance measuring section having the same cross-sectional structure as the program wiring section is used. A laser beam having the same wavelength as the laser beam to be irradiated is irradiated with a sufficiently low power that the measuring section is not melted, and an irradiation light amount detector detects the amount of laser beam irradiating the reflectance measurement section and detects the reflection. A reflected light amount detector detects the amount of reflected light obtained by multiple interference based on the variation in the characteristics of the multilayer transparent insulating film from the rate measuring section, and the amount of irradiated light detected by the irradiated light amount detector and the amount of reflected light are detected by the reflected light amount detector. The reflectance of the program wiring section is determined from the relationship with the amount of reflected light detected by the detector, and from this determined reflectance of the program wiring section, the effective energy absorbed by the program wiring section is determined by the multilayer transparent insulating film. A programming method for a semiconductor integrated circuit, characterized in that the laser output is adjusted so that it is always constant regardless of variations in characteristics, and the laser output is irradiated onto a program wiring section to perform connection or disconnection programming. 2. The method of programming in a semiconductor integrated circuit according to claim 1, wherein the reflectance measuring section is a programming wiring section that performs programming. 3. For a semiconductor integrated circuit in which a multilayer transparent insulating film is coated on a program wiring layer, a target mark portion provided in advance with the same cross-sectional structure as the program wiring portion is irradiated onto the program wiring portion. A laser beam having the same wavelength as the laser beam is irradiated at a sufficiently low power so as not to melt the target mark portion, and the amount of the laser beam irradiated to the target mark portion is detected by the irradiation light amount detector, and the amount of the laser beam is detected from the measuring section. The reflected light amount detector detects the amount of reflected light obtained by multiple interference based on the variation in the characteristics of the multilayer transparent insulating film, and the reflected light amount detector detects the amount of reflected light obtained by multiple interference based on the variation in the characteristics of the multilayer transparent insulating film. The programming wiring section detects the position of the target mark from the amount of irradiated light detected by the irradiation light amount and the image of the target mark detected by the reflected light amount detector, and performs programming based on the detected position of the target mark. The reflectance of the program wiring section is determined from the relationship between the irradiation light amount detected by the irradiation light amount detector and the reflected light amount detected by the reflected light amount detector, and from this determined reflectance of the program wiring portion. Programming is performed by adjusting the laser output so that the effective energy absorbed by the program wiring section is always constant regardless of variations in the characteristics of the multilayer transparent insulating film, and irradiating the positioned program wiring section. A programming method for a semiconductor integrated circuit, characterized in that:
JP57149309A 1982-08-30 1982-08-30 Semiconductor ic circuit and laser processing thereof Granted JPS5940548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP57149309A JPS5940548A (en) 1982-08-30 1982-08-30 Semiconductor ic circuit and laser processing thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP57149309A JPS5940548A (en) 1982-08-30 1982-08-30 Semiconductor ic circuit and laser processing thereof

Publications (2)

Publication Number Publication Date
JPS5940548A JPS5940548A (en) 1984-03-06
JPH0516182B2 true JPH0516182B2 (en) 1993-03-03

Family

ID=15472307

Family Applications (1)

Application Number Title Priority Date Filing Date
JP57149309A Granted JPS5940548A (en) 1982-08-30 1982-08-30 Semiconductor ic circuit and laser processing thereof

Country Status (1)

Country Link
JP (1) JPS5940548A (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7741131B2 (en) * 2007-05-25 2010-06-22 Electro Scientific Industries, Inc. Laser processing of light reflective multilayer target structure
GB2459669A (en) * 2008-04-30 2009-11-04 Xsil Technology Ltd Dielectric layer pulsed laser scribing and metal layer and semiconductor wafer dicing
EP3544760B1 (en) * 2016-11-23 2020-11-25 Aperam Method for laser stripping a moving metal product and plant for the execution thereof

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5627352A (en) * 1979-08-11 1981-03-17 Ricoh Co Ltd Ink jet head

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5627352A (en) * 1979-08-11 1981-03-17 Ricoh Co Ltd Ink jet head

Also Published As

Publication number Publication date
JPS5940548A (en) 1984-03-06

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