JPH05160708A - Tri-state output circuit - Google Patents

Abstract

PURPOSE:To reduce power consumption by interrupting a current path between power supplies in a high resistance output state. CONSTITUTION:In a tri-state output circuit in which base potentials of transistors(TRs) Q3, Q4 are reduced by inputting a control signal whose positive logic level '0' to a control terminal CNT to cause a high resistance output state, a current path between a high potential side power supply VCC and a low potential power supply VEE caused in the high resistance output state is interrupted by using P-channel MOS TRs M1, M2 switched by the control signal to reduce the power consumption in the high resistance state.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention is used in a three-state output circuit having a high resistance state as an output state.

[0002]

2. Description of the Related Art A three-state output circuit having a high resistance state as an output state has an advantage that it can be used for so-called wiring logic for connecting output terminals to each other, and has been widely used in recent years. On the other hand, the power supply voltage and the input / output potential, that is, the level are different depending on the circuit configuration in the integrated circuit that constitutes the logic, and there are TTL level, ECL level, CMOS level, etc. depending on the used element and the circuit configuration.

In recent years, integrated circuits having different input / output levels may be mixedly used, and in this case, it is necessary to use an integrated circuit capable of level conversion. In particular, the TTL that has been generally used conventionally
In many cases, the level and the ECL level capable of high-speed operation are mixed and used. On the other hand, in a semi-custom integrated circuit such as a gate array, one in which TTL and ECL levels can be mixed in one integrated circuit has been developed.

As described above, in an integrated circuit in which TTL and ECL levels can be mixed, the ECL is used to drop the substrate potential of the chip of the integrated circuit to the lowest potential among the potentials used.
It is set to the lower power supply VEE on the circuit (hereinafter referred to as VEE). As a result, the N-channel transistor is used between the ground potential GND (hereinafter referred to as GND) level and the VEE level, so that the relationship between the power supply and the circuit configuration is as shown in FIG.

FIG. 5 is a block diagram showing a mixed circuit of a TTL level and an ECL level (hereinafter referred to as a mixed TTL / ECL circuit). A TTL input circuit is provided between a high-side power supply VCC (hereinafter referred to as VCC) and GND. 11 and TTL
The output circuit 14 is arranged, and ECL is provided between GND and VEE.
Input circuit 12, internal circuit 13 and ECL output circuit 15
Are placed.

FIG. 3 shows a TT shown in FIG. 5 as a first conventional example.
FIG. 10 is a circuit diagram showing an example of a conventional TTL level three-state output circuit in an L / ECL mixed circuit.

The input terminal IN is connected to the buffer G1, and the output of the buffer G1 is connected to the base of the transistor Q2. The emitter of the transistor Q2 is a resistor R2.
Is connected to VEE via the
1 emitter. The base of the transistor Q1 is connected to GND, and the collector is connected to the base of the transistor Q3 and VCC via the resistor R1. The emitter of the transistor Q3 is connected to GND through the base of the output-stage transistor Q6 and the resistor R4, and the collector is connected to the base of the transistor Q4 and VCC through the resistor R3.

The collector of the transistor Q4 is connected to the collector of the transistor Q5 in the output stage, and the emitter is connected to the base of the transistor Q5 and the emitter of the transistor Q5 via the resistor R6. Output stage transistor Q
The collector of 5 is connected to VCC through the Schottky diode D3 and the resistor R7, and the emitter is the output terminal O.
It is connected to the UT and the collector of the transistor Q6. The emitter of the transistor Q6 is connected to GND.

A control terminal CN to which a control signal is input
T is connected to the input of the inverter G2, and the output of the inverter G2 is connected to the base of the transistor Q8. The emitter of the transistor Q8 is connected to VEE via the resistor R5, and the collector is connected to the emitter of the transistor Q7. The base of the transistor Q7 is connected to GND,
The collectors are connected to the bases of transistors Q3 and Q4 via Schottky diodes D1 and D2, respectively.

Next, the operation of this first conventional example will be described. First, the operation when not in the three-state state will be described.

Here, the transistors Q1, Q2,
Q3, Q4, Q6, Q7 and Q8 are NPN type transistors with Schottky barrier, and transistor Q5 is NP.
It is an N-type transistor. The control signal 2 of positive logic "1" is input to the control terminal CNT. When the input signal 1 of positive logic "1" is input to the input terminal IN, the base potential of the transistor Q2 rises due to the buffer G1 and the transistor Q2 turns "on". Then, the emitter potential of the transistor Q1 decreases, and the transistor Q1 is also turned "on". On the other hand, since the control signal 2 of the positive logic "1" input to the control terminal CNT is inverted by the inverter G2 and the positive logic "0" is at the base, the transistor Q8 is "off". Transistor Q3 is transistor Q1
And Q2 are "on", a voltage drop occurs due to the resistor R1 and the base potential drops, so "off"
Becomes As a result, the base potential of the transistor Q6 also drops and becomes "off". On the other hand, the base potential of the transistor Q4 rises through the resistor R3 to the high-side power source at the TTL level, that is, near VCC, the transistor Q4 turns "on", and the transistor Q5 also turns "on". 1 ”output can be obtained.

When a positive logic "0" input signal 1 is input to the input terminal IN, the transistor Q2 is "off", so that the base potential of the transistor Q3 rises to near VCC through the resistor R1 and the transistor Q3. Will be "on" and the transistor Q6 will also be "on".
On the other hand, the base potential of the transistor Q4 decreases, the transistor Q4 turns "off", the transistor Q5 also turns "off", and the output terminal OUT outputs a positive logic "0".

Next, the three-state state will be described. When positive logic "0" is input to the control terminal CNT, the transistor Q8 is turned "on", so that the emitter potential of the transistor Q7 is lowered and the transistor Q7 is also turned "on". As a result, the base potentials of the transistors Q3 and Q4 are respectively Schottky diode D1.
And it goes "off" because it goes down through D2. Therefore, the transistors Q5 and Q6 are also “off”.
Therefore, the output terminal OUT is in a high resistance state.

FIG. 6 is a block diagram showing a circuit only for the TTL level, in which a TTL input circuit 1 is provided between VCC and GND.
1, the internal circuit 13 and the TTL output circuit 14 are connected.

FIG. 4 is a circuit diagram showing an example of a conventional TTL level three-state output circuit as compared with FIG. 6 as a second conventional example.

The second conventional example is an N with Schottky barrier.
PN type transistors Q11, Q12 and Q13,
NPN type transistor Q15, P channel MOS transistor M11, N channel MOS transistor M
14 and M15 and the Schottky diode D11,
D12 and D13, diode D14, and resistor R1
1 to R15, inverters G13 and G14, an input terminal IN, a control terminal CNT, an output terminal OUT, a high potential side power supply VCC, and a ground potential GND.

As in the first conventional example of FIG. 3, when a control signal of positive logic "0" is input to the control terminal CNT,
The output terminal OUT is in a high resistance state.

[0018]

In the conventional three-state output circuit described above, in the high resistance state, for example, in the first conventional example of FIG. 3, the Schottky diode is used to lower the base potential of the transistors Q3 and Q4. Since it is connected to VEE through D1 or D2, the transistors Q7 and Q8 and the resistor R5, a current path is generated from VCC to VEE through the resistor R1 or R3 and the circuit described above. Similarly, in the second conventional example of FIG. To G
There is a drawback that a current path is generated in ND and power consumption increases.

An object of the present invention is to provide a three-state output circuit in which the current flowing from VCC to VEE or GND is prevented and the power consumption is reduced in the high resistance state by eliminating the above-mentioned drawbacks. ..

[0020]

The present invention includes means for obtaining an output in a high resistance state by controlling at least one input signal by a control signal, and is connected between a high power source and a low power source. The state output circuit includes switch means connected in series to a current path generated between the high-potential side power source and the low-potential side power source in a high resistance state, and controlled to an “off” state by the control current in a high resistance state. It is characterized by

Further, the present invention is a three-state output circuit connected between a high potential side power source and a ground potential, which includes means for obtaining an output in a high resistance state by controlling at least one input signal by a control signal. It is characterized in that it includes switch means connected in series to a current path generated between the high-potential side power source and the ground potential in the high resistance state, and controlled to the “OFF” state by the control signal in the high resistance state.

[0022]

According to the present invention, VCC and V generated in the high resistance state
The current path generated between EE or GND is turned off by the control means for obtaining the high resistance state of the switch means connected in series to this current path, and the current path is disconnected.

Therefore, no current flows between VCC and VEE or GND, so that power consumption can be reduced.

[0024]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

In the first embodiment, N with a Schottky barrier is used.
PN type transistors Q1, Q2, Q3, Q4, Q6,
Q7 and Q8, NPN type transistor Q5, Schottky barrier diodes D1, D2 and D3,
Resistors R1 to R7 and P-channel MOS transistor M1
And M2, a buffer G1, an inverter G2, an input terminal IN, an output terminal OUT, a control terminal CNT,
It includes VCC, VEE, and GND.

The input terminal IN is connected to the input of the buffer G1, and the output of the buffer G1 is the transistor Q2.
Connected to the base of. The emitter of the transistor Q2 is connected to VEE via the resistor R2, and the collector is connected to the emitter of the transistor Q1. Transistor Q1
Has a base connected to GND and a collector connected to the base of the transistor Q3 and one end of the resistor R1. Resistance R1
The other end of V is connected to V via the P-channel MOS transistor M1.
Connected to CC. P-channel MOS transistor M1
Is connected to the output of the inverter G2. The emitter of the transistor Q3 is connected to the base of the transistor Q6 in the output stage and the GND via the resistor R4, and the collector is connected to the base of the transistor Q4 and one end of the resistor R3. The other end of the resistor R3 has a P-channel MOS transistor M
2 to VCC. The gate of P-channel MOS transistor M2 is connected to the output of inverter G2. The collector of the transistor Q4 is connected to the collector of the transistor Q5 in the output stage, and the emitter is connected to the base of the transistor Q5 and the emitter of the transistor Q5 via the resistor R6. The collector of the transistor Q5 in the output stage is connected to VCC via the Schottky barrier diode D3 and the resistor R7, and the emitter is the output terminal O
It is connected to the UT and the collector of the transistor Q6. The emitter of the transistor Q6 is connected to GND.

The control terminal CNT is connected to the input of the inverter G2, and the output of the inverter G2 is connected to the base of the transistor Q8. The emitter of the transistor Q8 is connected to VEE through the resistor R5, and the collector is connected to the emitter of the transistor Q7. The base of transistor Q7 is connected to GND, and the collector is connected to the bases of transistors Q3 and Q4 via Schottky barrier diodes D1 and D2, respectively.

A feature of the present invention is that in FIG. 1, P-channel MOS transistors M1 and M are used as switch means.
2 is provided.

Next, the operation of the first embodiment will be described.

First, the case where the high resistance state is not set will be described. In this case, the control signal 2 of positive logic "1" is input to the control terminal CNT. Therefore, the output of the inverter G2 is positive logic "0", and the transistor Q8 is "off". At this time, since the positive logic "0" is input to the gates of the P-channel MOS transistors M1 and M2, both transistors are turned "on", and the circuit configuration is the same as that of FIG. 3 and the buffer operates as a normal buffer.

Next, the high resistance state will be described. When the control signal 2 of positive logic "0" is input to the control terminal CNT, the transistor Q8 is turned "on".
The emitter potential of the transistor Q7 decreases and the transistor Q7 also turns on. As a result, the base potentials of the transistors Q2 and Q4 drop through the Schottky barrier diodes D1 and D2, respectively, so that the transistors Q3 and Q4 are turned "off". Therefore, the transistors Q5 and Q6 are also "off" and the output terminal OUT is in a high resistance state.

At this time, since the output of the inverter G2 is a positive logic "1", the P-channel MOS transistors M1 and M2 are also "off", so that the resistors R1 and R3 are separated from VCC, respectively, and the conventional circuit is provided. VCC
Since there is no current path that escapes from VEE to VEE, power consumption can be suppressed.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention. The second embodiment is an application of the present invention to the case where only the TTL circuit shown in FIG. 6 is connected.

The second embodiment is N with a Schottky barrier.
PN type transistors Q11, Q12 and Q13,
NPN type transistor Q15, P channel MOS transistors M11, M12 and M13, N channel MOS transistors M14 and M15, Schottky barrier diodes D11, D12 and D13, diode D14, resistors R11 to R15, and inverter G11. And G12, input terminal IN, and output terminal OU
It includes a T, a control terminal CNT, a VCC, and a GND.

The input terminal IN is a P channel MOS
Transistor M11, N-channel MOS transistor M
14 and the gate of M15. P channel M
The source of the OS transistor M11 is connected to VCC,
The drain is connected to the source of the P-channel MOS transistor M12. N-channel MOS transistor M14
Source is connected to GND and drain is diode D
One end of the resistor R11 is connected via 14 to the base of the transistor Q11. The other end of the resistor R11 is a P channel M
It is connected to the drain of the OS transistor M12.

The emitter of the transistor Q11 is connected to the base of the transistor Q13 and GND via the resistor R13, and the collector is connected to one end of the resistor R12 and the transistor Q1.
2 connected to the base. The collector of the transistor Q12 is connected to the collector of the output stage transistor Q5,
The emitter is connected to the emitter of the transistor Q15 via the base of the transistor Q15 and the resistor R14. The collector of the transistor Q15 in the output stage is connected to VCC via the Schottky diode D13 and the resistor R15, and the emitter is the output terminal OUT and the transistor Q13.
Connected to the collector. The emitter of the transistor Q13 is connected to GND. The source of the N-channel MOS transistor M15 is connected to GND, and the drain is connected to the base of the transistor Q13.

The control terminal CNT is an inverter G11.
, The output of the inverter G11 is connected to the input of the inverter G12, and the output of the inverter G12 is connected to the bases of the transistors Q11 and Q12 via the Schottky barrier diodes D11 and D12, respectively. The source of the P-channel MOS transistor M12 is connected to the drain of the P-channel MOS transistor M11, the drain is connected to the other end of the resistor R11, and the gate is connected to the output of the inverter G11. P
The source of the channel MOS transistor M13 is connected to VCC, and the drain is connected to the other end of the resistor R12.

A feature of the present invention is that P-channel OS transistors M12 and M13 are provided as switch means in FIG.

Next, the operation of the second embodiment will be described.

First, the case where the high resistance state is not set will be described. In this case, the control signal 2 of positive logic "1" is input to the control terminal CNT. Therefore, the inverter G11
Output becomes positive logic "0", and since positive logic "0" is input to the gates of the P-channel MOS transistors M12 and M13, both transistors become "on", which is equivalent to the conventional circuit diagram 4 for FIG. Operates as a normal buffer.

Next, the case of the high resistance state will be described. In this case, since the control signal 2 of positive logic "0" is input to the control terminal CNT, the output of the inverter G12 becomes positive logic "0", and the base potentials of the transistors Q11 and Q12 are the Schottky barrier. Transistors Q11 and Q12 are "off" because they fall through diodes D11 and D12. Therefore, the transistor Q15 and the transistor Q
13 is also turned off, and the output terminal OUT is in a high resistance state.

At this time, since the gates of the P-channel MOS transistors M12 and M13 are positive logic "1" and "OFF", the resistors R11 and R12 are respectively set to V.
Separated from CC, VCC to G that existed in the conventional circuit
There is no current path leading to ND, and power consumption can be suppressed.

[0044]

As described above, according to the present invention, the "on" of the MOS transistor connected as the switch means is turned on.
・ By controlling "off" with a control signal, the current path between the high-side power supply and the low-side power supply or the ground potential that occurs when the three-state output circuit is in the high resistance state is cut off, and the power consumption of the circuit is reduced. There is.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is a circuit diagram showing a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing a first conventional example.

FIG. 4 is a circuit diagram showing a second conventional example.

FIG. 5 is a block diagram showing a mixed TTL / ECL circuit.

FIG. 6 is a block configuration diagram showing a TTL circuit.

[Explanation of symbols]

1 Input signal 2 Control signal CNT Control input terminal D1 to D3, D11 to D13 Schottky barrier diode D4, D14 Diode G1 Buffer G2, G11, G12 Inverter GND Ground potential IN input terminal M11 to M13 P channel MOS transistor M14, M15 N Channel MOS transistor OUT output terminal Q1 to Q4, Q6, Q7, Q8, Q11 to Q13 (NPN type with Schottky barrier) transistors Q5 and Q15 (NPN type) transistors R1 to R7, R11 to R15 Resistance VCC High-side power supply VEE Lower power supply

Claims (2)

[Claims] 1. A three-state output circuit connected between a high-potential side power source and a low-potential side power source, including a means for obtaining an output in a high resistance state by controlling at least one input signal by a control signal, A three-state output comprising switch means which is connected in series to a current path generated between the high-potential side power source and the low-potential side power source at a time and which is controlled to be in an “off” state by the control current in a high resistance state. circuit. 2. A three-state output circuit connected between a high-potential side power supply and a ground potential, which includes means for obtaining an output in a high resistance state by controlling at least one input signal by a control signal. A three-state output circuit, which is connected in series to a current path generated between the high-potential side power supply and the ground potential, and includes switch means controlled to be in an "off" state by the control signal in a high resistance state.