JPH05160695A - Timing generation circuit - Google Patents

Abstract

PURPOSE:To compress a circuit scale and circuit configuration by simplifying a circuit by reducing relative deviation in plural timing pulses setting a first timing pulse as reference. CONSTITUTION:The timing pulse RTG is generated at a pulse generation circuit 1 based on a reference clock signal CLK and data signals Dn-D0. A signal A is outputted from a shift register 2 being delayed by two cycles of the clock CLK corresponding to the pulse RTG and the reference clock CLK. AND of the timing pulse RTG and the signal A is taken at an AND circuit 3, then, the timing pulse STG is outputted. Also, the exclusive OR of the timing pulse RTG that is the same signal as the reference of the pulse STG and the signal A is taken at an EXOR circuit 4, then, the timing pulse FTG is outputted. The relative deviation of timing of the pulses FTG and STG for the pulse RTG can be outputted with the minimum error of the shift register 5 and a circuit 5.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing for generating a plurality of different timings such as a read timing for reading data from a memory and a display timing for displaying on a screen in a picture-in-picture system of a television system. Regarding the generation circuit,
In particular, the present invention relates to a timing generation circuit in which each timing has a relatively small deviation.

[0002]

2. Description of the Related Art A conventional timing generating circuit will be described with reference to FIG. FIG. 4 is a circuit diagram of a picture-in-picture timing generation circuit of a television system showing an example of a conventional timing generation circuit. Figure 5
, 5a, 5b are counter circuits, 6a, 6b, 6
c decoder circuit, D _n to D ₀ is the data signal, D _n '~D _0' data signal for setting the initial value of the counter circuit 5b for setting an initial value of the counter circuit 5a, CLK is a reference clock, RTG is The timing pulse output from the decoder 6a, STG is the timing pulse output from the decoder 6b, and FGT is the timing pulse output from the decoder 6c. Here, the timing pulse RT
G, STG, and FTG are, for example, a memory read signal, a display timing signal, and a frame signal from a sub-screen in a picture-in-picture system of a television system.

[0003] The counter circuit 5a the data signal D _n to D
₀ and the reference clock CLK are input, the counter circuit 5a outputs the count value of the reference clock CLK, and the output is input to the decoder 6a. The decoder 6a outputs "L" according to a specific count value of the counter circuit 5a.
Or by changing to "H", timing pulse R
Generate TG. Data signals D _n ′ to D ₀ ′ and a reference clock CLK are input to the counter circuit 5b,
The counter circuit 5b outputs the count value of the reference clock CLK, and the output is input to the decoders 6b and 6c. The decoders 6a, 6b generate timing pulses STG, FTG by changing the output to "L" or "H" according to a certain specific count value of the counter circuit 5b.

[0004]

The conventional timing generating circuit is configured as described above, and the different decoder 6 is used.
Since the timing pulses are individually generated in a to 6c, there is a problem that a relative deviation occurs in the signal output timing among the mutual timing pulses RTG, STG, and FTG.

The present invention has been made to solve the above problems, and in a timing generation circuit for generating a plurality of timing pulses, it is possible to reduce a relative deviation in signal output timing between each pulse. The purpose is to obtain a timing generation circuit capable of performing

[0006]

A timing generating circuit according to a first aspect of the present invention includes a pulse generating circuit which receives a reference clock and generates a first pulse, and which receives the reference clock and the first pulse as input. A shift register that delays the first pulse according to the reference clock and outputs a second pulse; an AND circuit that outputs the third pulse by using the first and second pulses as inputs; And the third
And an exclusive OR circuit that outputs the fourth pulse as the input.

The timing generation circuit according to the second invention is
A pulse generation circuit that receives a reference clock and generates a first pulse, and outputs the second pulse by receiving the reference clock and the first pulse as input and delaying the first pulse according to the reference clock. A first shift register, a third clock which receives the reference clock and the second pulse and delays the second pulse according to the reference clock;
A second shift register for outputting a pulse of
And an AND circuit that outputs the fourth pulse with the third pulse as an input, and an exclusive OR circuit that outputs the fifth pulse with the second and third pulses as an input. There is.

[0008]

According to the first aspect of the present invention, there is provided a timing generating circuit, which comprises a shift register for receiving a reference clock and a first pulse, delaying the first pulse according to the reference clock, and outputting a second pulse, It is configured to include a logical product circuit that inputs the first and second pulses and outputs the third pulse, and an exclusive OR circuit that inputs the first and second pulses and outputs the fourth pulse. , The relative deviation of the timing between the first pulse and the third and fourth pulses is an operation error of the shift register, and the relative deviation between the first pulse and the third and fourth pulses. The gap can be reduced. Further, the relative deviation of the timing between the third pulse and the fourth pulse is the difference in operation speed between the AND circuit and the exclusive OR circuit, and the difference in operation speed is very small. It is possible to reduce the relative deviation between the timings of the third pulse and the fourth pulse. Moreover, since the circuit configuration can be simplified, the number of gates can be reduced.

The timing generation circuit in the second invention receives the reference clock and the first pulse as input, delays the first pulse in accordance with the reference clock, and outputs the second pulse. A shift register; a second shift register which receives the reference clock and the second pulse and delays the second pulse according to the reference clock to output a third pulse; and the second and third shift registers. An AND circuit that outputs the fourth pulse by inputting the pulse of
Since the exclusive logic circuit which outputs the fifth pulse with the second and third pulses as an input is provided, the timing between the first pulse and the fourth and fifth pulses is changed. The relative shift is an operation error of the first or second shift register, and the relative shift of the timing between the first pulse and the fourth and fifth pulses can be reduced. Further, the relative deviation of the timing between the fourth pulse and the fifth pulse is the difference in operation speed between the AND circuit and the exclusive OR circuit, and the difference in operation speed is very small. , The relative deviation of the timing between the fourth pulse and the fifth pulse can be reduced.
Further, by changing the shift amounts of the first and second shift registers, the phases between the first pulse and the fourth and fifth pulses can be arbitrarily shifted and output. Moreover, since the circuit configuration can be simplified, the number of gates can be reduced.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to FIGS. 1 is a block diagram showing the structure of a timing generation circuit according to an embodiment of the present invention. In FIG. 1, 1 is a pulse generating circuit, 2 is a shift register, 3 is an AND circuit, and 4 is an exclusive OR circuit. The pulse generation circuit 1 can be configured by combining a counter circuit and a decoder as in the conventional case, for example.
D _{n to} D ₀ are data signals and set initial values of the pulse generation circuit 1. CLK is a reference clock, RTG, ST
G and FTG are timing pulses, A is shift register 2
Is an output signal of.

Data signals D _{n to} D ₀ , which are initial value data, and a reference clock CLK are input to the pulse generation circuit 1.
The timing pulse RTG which is the first pulse is output. The timing pulse RTG that is the first pulse and the reference clock CLK are input to the shift register 2, and the signal A that is the second pulse is output from the shift register 2.
The signal A that is the second pulse and the timing pulse RTG that is the first pulse are input to the AND circuit 3, and the timing pulse STG is output from the AND circuit 3. Similarly, the signal A which is the second pulse and the timing pulse RTG which is the first pulse are input to the exclusive OR circuit 4,
A timing pulse FTG is output from the exclusive OR circuit 4.

Next, the relationship between the input reference clock CLK, the timing pulses RTG, STG, FTG and the signal A will be described with reference to the timing waveform diagram of FIG.
A timing pulse RTG is generated by the pulse generation circuit 1 based on the reference clock CLK and the data signals D _{n to} D ₀ . According to the timing pulse RTG and the reference clock CLK, the signal A is output from the shift register 2 with a delay of two cycles of the reference clock CLK. Then, the logical product of the timing pulse RTG and the signal A is performed by the logical product circuit 3, and the timing pulse STG is output. Further, the exclusive OR of the timing pulse RTG, which is the same signal as the reference of the timing pulse STG, and the signal A is performed by the exclusive OR circuit 4, and the timing pulse FTG is output. For example, in the case of a signal for sub-screen display of a picture-in-picture system in a television system, when the timing pulse STG is "H", the timing pulse RTG is "H", and the timing pulse STG changes from "H" to "H". It suffices that the timing pulse FTG be "H" after changing to "L" and before the timing pulse STG changes from "L" to "H", and this circuit can output the same signal as the conventional one.

As described above, the timing pulse FTG,
The relative deviation of the timing of the STG with respect to the timing pulse RTG is caused by the operation delay and the operation error of the shift register 2, the AND circuit 3, and the exclusive OR circuit 4. That is, after the timing pulse RTG is input to the exclusive OR circuit 4, the timing pulse FTG is called an operation delay of the exclusive OR circuit 4 which is a very small error or an operation delay of the shift register 2 and the exclusive OR circuit 4. After being output with a small error, the timing pulse RTG is input to the logical product circuit 5, and then the timing pulse STG is generated with a small error such as an operation delay between the logical product circuit 5 and the shift register 2 or a very small error of the logical product circuit 5. Therefore, the relative timing deviation between the timing pulse RTG and the timing pulses STG and FTG is small.

The relative timing deviation between the timing pulse STG and the timing pulse FTG is the timing pulse RTG input to the AND circuit 3 and the exclusive OR circuit 4, or the change in the output signal A of the shift register 2. Then, the AND circuit 3 and the exclusive OR circuit 4
Occurs due to the difference in time until the output signal is output from, i.e., the difference in operating speed of the logic circuits 3 and 4. Therefore, the difference is very small, and the relative timing deviation between the timing pulses STG and FTG is small.

Next, another embodiment of the present invention will be described with reference to FIG.
And FIG. 4 will be described. FIG. 3 is a block diagram showing the structure of a timing generation circuit according to another embodiment of the present invention. In FIG. 3, reference numeral 1 is a pulse generator circuit, and 2a and 2b.
Is a shift register, 3 is an AND circuit, and 4 is an exclusive OR circuit. D _{n to} D ₀ are data signals and set initial values of the pulse generation circuit 1. B is the shift register 2a
, C is the output signal of the shift register 2b, and the same reference numerals as those in FIG. 1 indicate the same contents as those in FIG.

The data signals D _{n to} D ₀ which are initial value data and the reference clock CLK are input to the pulse generator 1.
The timing pulse RTG which is the first pulse is generated. Next, the timing pulse RTG which is the first pulse
And the reference clock CLK are input to the shift register 2a,
Output signal B which is the second pulse from the shift register 2a
Will output. The output signal B that is the second pulse and the reference clock CLK are input to the shift register 2b, and the output signal C that is the third pulse is output from the shift register 2b. Then, the output signal B which is the second pulse and the output signal C which is the third pulse are input to the AND circuit 3, and the timing pulse ST which is the fourth pulse is input from the AND circuit 3.
G outputs. Similarly, in the exclusive OR circuit 4,
The output signal B which is the second pulse and the output signal C which is the third pulse are input, and the exclusive OR circuit 4 outputs the timing pulse FTG which is the fifth pulse.

Next, the relationship between the input reference clock CLK and the timing pulses RTG, STG, FT and the signals B, C will be described with reference to the timing waveform diagram of FIG. As shown in FIG. 4, the timing pulse RTG is generated by the pulse generation circuit 1 based on the reference clock CLK and the data signals D _{n to} D ₀ . Timing pulse RTG
And 1 of the reference clock CLK according to the reference clock CLK
The signal B is output from the shift register 2a with a delay of a period.

Further, according to the reference clock CLK and the signal B, the signal C is output from the shift register 2b with a delay of the signal B by one cycle of the reference clock CLK. Then, the signals B and C output from the shift registers 2a and 2b
And the timing pulse ST
Output G. Similarly, the exclusive OR circuit 4 performs the exclusive OR of the signals B and C output from the shift registers 2a and 2b, and outputs the timing pulse FTG.

As described above, the timing pulse RTG,
The relative timing shift between the STG and FTG signal outputs is caused by the operation delay and operation error of the shift registers 2a and 2b, the AND circuit 3, and the exclusive OR circuit 4. That is, the timing pulse RTG and the timing pulse S
The relative deviation between the timings of TG and FTG is a small error that is an operation delay between the shift registers 2a and 2b and the AND circuits 3 and 4. Further, the relative deviation between the timings of the timing pulse STG and the timing pulse FTG is exclusive OR with the logic circuit 3 after the change of the signal B or the signal C input to the AND circuit 3 and the exclusive OR circuit 4 is input. It is caused by a time difference until the circuit 4 outputs a signal, that is, a difference in operation speed of the AND circuits 3 and 4. Therefore, the time difference is very small, and the relative timing deviation between the signal outputs is small.

For example, in the case of a signal for displaying a sub screen of a picture-in-picture system in a television system, when the timing pulse STG is "H", the timing pulse RTG is "H" and the timing pulse STG is "H". It is sufficient if the timing pulse FTG is “H” after the change from “H” to “L” and before the timing pulse STG changes from “L” to “H”.
Although it is not like that in the timing waveform diagram of No. 2, the above signals can be produced by changing the amount of shifting the phase of the signals in the shift registers 2a and 2b, and the phase of the timing pulses STG and FTG. Can be arbitrarily shifted with respect to the timing pulse RTG according to the reference clock, and the range of applications that can be applied is expanded as compared with the above-described embodiment.

In each of the above embodiments, the pulse generation circuit 1
Although it was necessary to set the initial value of the data signal D _{n to} D ₀ , the pulse generating circuit may be one that does not require the input of the data signal, and the same effect as that of each of the above embodiments can be obtained. Play.

[0022]

As described above, according to the timing generating circuit of the present invention, the reference clock and the first pulse are input and the first pulse is delayed according to the reference clock. A shift register that outputs two pulses; an AND circuit that inputs the first and second pulses and outputs a third pulse; and a fourth pulse that inputs the first and third pulses It is characterized in that it is provided with an exclusive OR circuit for outputting and outputs the first, third and fourth pulses as timing pulses.
There is an effect that the delay time of the output of each of the first to fourth pulses can be reduced to reduce the relative deviation of the timing of outputting each timing pulse.
Further, there is an effect that the circuit can be simplified and the circuit configuration and the circuit scale can be reduced.

According to another aspect of the timing generating circuit of the present invention, the reference clock and the first pulse are input, and the first pulse is delayed according to the reference clock to generate the second pulse. A first shift register for outputting, a second shift register for inputting the first and second pulses, delaying the second pulse according to the reference clock, and outputting a third pulse, A logical product circuit that outputs a fourth pulse by inputting the second and third pulses and an exclusive OR circuit that outputs a fifth pulse by inputting the second and third pulses; Since the first, fourth, and fifth pulses are output as timing pulses, the delay time of the output of each of the first to fifth pulses is reduced, and the timing of outputting each timing pulse There is an effect that it is possible to reduce the relative displacement. Further, there is an effect that the circuit can be simplified and the circuit configuration and the circuit scale can be reduced.

Further, there is an effect that the phases of the fourth pulse and the fifth pulse can be arbitrarily shifted and output according to the reference clock with respect to the first pulse.

[Brief description of drawings]

FIG. 1 is a block diagram of a timing generation circuit according to an embodiment of the present invention.

FIG. 2 is a timing waveform chart of signals at various parts of the timing generation circuit shown in FIG.

FIG. 3 is a block diagram of a timing generation circuit according to another embodiment of the present invention.

FIG. 4 is a timing waveform chart of signals at various parts of the timing generation circuit shown in FIG.

FIG. 5 is a block diagram of a conventional timing generation circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 pulse generation circuit 2 shift registers 2a, 2b shift register 3 AND circuit 4 exclusive OR circuit 5 counter circuit 6 decoder

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[Procedure amendment]

[Submission date] April 24, 1992

[Procedure Amendment 1]

[Document name to be amended] Statement

[Name of item to be corrected] Claim 2

[Correction method] Change

[Correction content]

Claims (2)

[Claims] 1. A pulse generation circuit for generating a first pulse with a reference clock as an input, and a second pulse for delaying the first pulse according to the reference clock with the reference clock and the first pulse as inputs. Shift register for outputting the pulse, a logical product circuit for outputting the third pulse by inputting the first and second pulses, and a fourth pulse by inputting the first and third pulses A timing generation circuit comprising an exclusive OR circuit and outputting the first, third and fourth pulses as timing pulses. 2. A pulse generation circuit which receives a reference clock and generates a first pulse; and a first pulse which receives the reference clock and the first pulse and delays the first pulse according to the reference clock. A first shift register which outputs two pulses; and a second shift which inputs the reference clock and the second pulse, delays the second pulse according to the reference clock, and outputs a third pulse A register, an AND circuit that outputs the fourth pulse by inputting the second and third pulses, and an exclusive OR circuit that outputs the fifth pulse by inputting the second and third pulses And outputting the first, fourth and fifth pulses as timing pulses.