JPH05160428A - Semiconductor light receiving device - Google Patents

Semiconductor light receiving device

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Publication number
JPH05160428A
JPH05160428A JP3307455A JP30745591A JPH05160428A JP H05160428 A JPH05160428 A JP H05160428A JP 3307455 A JP3307455 A JP 3307455A JP 30745591 A JP30745591 A JP 30745591A JP H05160428 A JPH05160428 A JP H05160428A
Authority
JP
Japan
Prior art keywords
layer
light receiving
compound semiconductor
receiving device
semiconductor layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
JP3307455A
Other languages
Japanese (ja)
Inventor
Tatsuaki Shirai
達哲 白井
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP3307455A priority Critical patent/JPH05160428A/en
Publication of JPH05160428A publication Critical patent/JPH05160428A/en
Withdrawn legal-status Critical Current

Links

Abstract

PURPOSE:To prevent crosstalks from being generated in a semiconductor light receiving device, by making the diffusion length of carriers at the hetero- interface short through very simple means and suppressing the diffusion of the carriers generated due to incident light. CONSTITUTION:In a semiconductor light receiving device, an n-InP buffer layer 2, an n-InGaAs light absorbing layer 3, and an n-InP window layer 4 are formed in succession, and these layers constitute a hetero-junction structure. Also, in the device, provided are n<+>-InGaAs carrier diffusing suppressing layers 11, 12 inserted into the respective hetero-interfaces of the hetero-junction structure, and a plurality of p<+>-window regions spaced in parallel and having depths from the surface of the device to the n-InGaAs light absorbing layer 3.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、複数の受光素子が並ん
でいて光信号を並列伝送するのに好適な半導体受光装置
の改良に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an improvement of a semiconductor light receiving device in which a plurality of light receiving elements are arranged and which is suitable for transmitting an optical signal in parallel.

【0002】現在、光ファイバを利用した通信の分野は
拡大され、また、多様化する状況にあり、例えば、コン
ピュータの配線を従来の同軸ケーブルから10芯〜40
芯ものリボン光ファイバに置き換え、コンピュータ・デ
ータを並列的に送る、所謂、並列伝送が行われようとし
ている。
At present, the field of communication using optical fibers is expanding and diversifying. For example, the wiring of a computer is changed from a conventional coaxial cable to 10 cores to 40 cores.
The so-called parallel transmission is about to be performed, in which computer data is sent in parallel by replacing the core with a ribbon optical fiber.

【0003】従って、当然のことながら、そこで用いら
れる発光或いは受光装置は、従来の1チップに単体素子
を作り込んだものではなく、1チップに複数の素子が並
ぶように作り込まれたものでなければならない。然しな
がら、そのような発光装置或いは受光装置は未だ改良す
べき点が多く残されている。
Therefore, as a matter of course, the light-emitting or light-receiving device used therein is not one in which a single element is built in a conventional one chip, but one in which a plurality of elements are arranged in one chip. There must be. However, such a light emitting device or light receiving device still has many points to be improved.

【0004】[0004]

【従来の技術】一般に、半導体受光素子を同一チップ上
に並列配置して作り込んだ場合、素子間のクロス・トー
クが問題となる。特に、InP/InGaAs/InP
のように禁制帯幅が異なる半導体層を積層したヘテロ構
造を用いた半導体受光素子では深刻な問題となる。
2. Description of the Related Art Generally, when semiconductor light receiving elements are arranged in parallel on the same chip and built in, cross talk between the elements becomes a problem. In particular, InP / InGaAs / InP
As described above, a semiconductor photodetector using a heterostructure in which semiconductor layers having different forbidden band widths are stacked poses a serious problem.

【0005】その理由は、各半導体層の間に生成される
ヘテロ界面に於けるキャリヤの拡散長が非常に長い為、
或る素子に入射した光に依って発生するキャリヤが隣接
する素子に入り込むことが多く、所謂、クロス・トーク
のレベルが高いことにある。
The reason is that the diffusion length of carriers at the hetero interface formed between the semiconductor layers is very long.
Carriers generated due to light incident on a certain element often enter an adjacent element, and this is because the so-called cross talk level is high.

【0006】そこで、従来から、このようなクロス・ト
ークを抑える為の種々な試みがなされている。図6はク
ロス・トークを防止する構成を備えた半導体受光装置の
従来例を表す要部切断側面図である。図に於いて、1は
+ −InP基板、2はn−InPバッファ層、3はn
−InGaAs光吸収層、4はn−InPウインドウ
層、5は素子間を分離する為のメサ溝、6はp+ −ウイ
ンドウ領域、7はSiNx からなる無反射コーティング
膜、8はp側電極、9はn側電極をそれぞれ示してい
る。
Therefore, various attempts have conventionally been made to suppress such cross talk. FIG. 6 is a cutaway side view of a main part of a conventional example of a semiconductor light receiving device having a structure for preventing cross talk. In the figure, 1 is an n + -InP substrate, 2 is an n-InP buffer layer, 3 is n
-InGaAs light absorption layer, 4 is an n-InP window layer, 5 is a mesa groove for separating elements, 6 is a p + -window region, 7 is a non-reflective coating film made of SiN x , 8 is a p-side electrode , 9 are n-side electrodes, respectively.

【0007】この半導体受光装置では、素子間を分離す
る為のメサ溝5を設けることで、或る素子に入射した光
に依って発生するキャリヤが隣接する素子に侵入するこ
とがないようにし、クロス・トークの発生を防止してい
る。
In this semiconductor light receiving device, by providing the mesa groove 5 for separating the elements from each other, carriers generated by the light incident on a certain element do not enter the adjacent element, It prevents the occurrence of cross talk.

【0008】[0008]

【発明が解決しようとする課題】図6に見られる半導体
受光装置に於いては、クロス・トークを防止する為、メ
サ溝5を形成してあるが、通常、この種の半導体受光装
置に於いては、その光感度を高くする為、n−InGa
As光吸収層3を例えば2〔μm〕〜3〔μm〕と厚く
してあるので、メサ溝5の深さは約5〔μm〕〜6〔μ
m〕程度にもなってしまう。従って、このメサ溝5の段
差に依って、例えば無反射コーティング膜7の段差切れ
など種々な問題が起こる。
In the semiconductor light receiving device shown in FIG. 6, the mesa groove 5 is formed in order to prevent cross talk. Normally, in this type of semiconductor light receiving device. In order to increase its photosensitivity, n-InGa
Since the As light absorption layer 3 is thickened, for example, 2 [μm] to 3 [μm], the depth of the mesa groove 5 is about 5 [μm] to 6 [μm].
m]. Therefore, due to the step difference of the mesa groove 5, various problems such as the step difference of the antireflection coating film 7 occur.

【0009】本発明は、極めて簡単な手段を採ることで
ヘテロ界面に於けるキャリヤの拡散長が短くなるように
し、入射する光に依って発生するキャリヤの拡散を抑え
てクロス・トークの発生を防止しようとする。
According to the present invention, by adopting an extremely simple means, the diffusion length of carriers at the hetero interface is shortened, the diffusion of carriers generated by incident light is suppressed, and the occurrence of cross talk is suppressed. Try to prevent.

【0010】[0010]

【課題を解決するための手段】図1は本発明の原理を説
明する為の半導体受光装置を表す要部切断側面図であ
り、図6に於いて用いた記号と同記号は同部分を表すか
或いは同じ意味を持つものとする。
FIG. 1 is a cutaway side view of an essential part of a semiconductor light receiving device for explaining the principle of the present invention, and the same symbols as those used in FIG. 6 represent the same parts. Or have the same meaning.

【0011】図1に見られる半導体受光装置が図6に見
られる半導体受光装置と相違するところは、光電変換を
行うべきn−InGaAs光吸収層3が1×1017〔cm
-3〕を越える高い濃度の不純物を含有した約500
〔Å〕〜1000〔Å〕程度の薄いn+ −InGaAs
キャリヤ拡散抑止層11並びに12で挟まれている点に
ある。
The semiconductor light receiving device shown in FIG. 1 differs from the semiconductor light receiving device shown in FIG. 6 in that the n-InGaAs light absorption layer 3 to be subjected to photoelectric conversion is 1 × 10 17 [cm].
-3 ]] About 500 containing high concentration of impurities
Thin n + -InGaAs of about [Å] to 1000 [Å]
It is located between the carrier diffusion suppressing layers 11 and 12.

【0012】このような構成を採ると、n−InGaA
s光吸収層3とn−InPバッファ層2或いはn−In
Pウインドウ層4とのヘテロ界面に於けるキャリヤの拡
散長は短くなる。
With such a structure, n-InGaA
s light absorption layer 3 and n-InP buffer layer 2 or n-In
The carrier diffusion length at the hetero interface with the P window layer 4 becomes short.

【0013】このようなことから、本発明に依る半導体
受光装置に於いては、 (1)禁制帯幅Eg1及びEg2及びEg3が Eg1>Eg2及びEg3>Eg2 なる関係にあって且つ順に積層形成されてヘテロ接合構
造を構成する禁制帯幅がEg1である一導電型の第一の化
合物半導体層(例えばn−InPバッファ層2)及び禁
制帯幅がEg2である一導電型の第二の化合物半導体層
(例えばn−InGaAs光吸収層3)及び禁制帯幅が
g3である一導電型の第三の化合物半導体層(例えばn
−InPウインドウ層4)と、該ヘテロ接合構造に於け
る各ヘテロ界面に介挿され禁制帯幅がEg2であると共に
該第二の化合物半導体層に比較して充分に高濃度の一導
電型不純物を含有した化合物半導体薄膜(例えばn+
InGaAsキャリヤ拡散抑止層11及び12)と、表
面から第二の化合物半導体層に達する深さ及び所定間隔
を維持して並列された複数の反対導電型不純物拡散領域
(例えばp+ −ウインドウ領域6)とを備えてなること
を特徴とするか、或いは、
From the above, in the semiconductor light receiving device according to the present invention, (1) the forbidden band widths E g1 and E g2 and E g3 have a relationship of E g1 > E g2 and E g3 > E g2. The first compound semiconductor layer of one conductivity type (e.g., n-InP buffer layer 2) having a forbidden band width of E g1 and having a forbidden band width of E g2 that are present and are sequentially stacked to form a heterojunction structure. One conductivity type second compound semiconductor layer (for example, n-InGaAs light absorption layer 3) and one conductivity type third compound semiconductor layer (for example, n) having a forbidden band width of E g3.
-InP window layer 4) and a forbidden band width of E g2 inserted at each hetero interface in the heterojunction structure and having a sufficiently high concentration of one conductivity type as compared with the second compound semiconductor layer. Compound semiconductor thin film containing impurities (for example, n +
InGaAs carrier diffusion suppression layers 11 and 12) and a plurality of opposite conductivity type impurity diffusion regions (for example, p + − window region 6) arranged in parallel while maintaining a depth reaching a second compound semiconductor layer from the surface and a predetermined interval. Or comprising, or

【0014】(2)前記(1)に於いて、第一の化合物
半導体層及び第二の化合物半導体層及び第三の化合物半
導体層がInP層及びInGaAs層及びInP層であ
ることを特徴とする。
(2) In the above (1), the first compound semiconductor layer, the second compound semiconductor layer, and the third compound semiconductor layer are InP layers, InGaAs layers, and InP layers. .

【0015】[0015]

【作用】前記した本発明の構成に依ると、InGaAs
層とInP層との間に不純物濃度が高いInGaAs層
が介挿されているので、ヘテロ界面に於けるキャリヤの
拡散長が短くなり、メサ溝を形成しなくても、実効的に
光感度を有する面積が狭くなって、素子間のクロス・ト
ークは低減される。
According to the above-described structure of the present invention, InGaAs
Since the InGaAs layer having a high impurity concentration is interposed between the InP layer and the InP layer, the diffusion length of carriers at the hetero interface is shortened, and effective photosensitivity is achieved without forming a mesa groove. Since the area of the device is reduced, cross talk between the elements is reduced.

【0016】図2は半導体受光装置にスポット状の光を
照射して一次元走査を行った場合の光感度を表す線図で
あり、縦軸に光感度を、また、横軸に位置をそれぞれ採
ってある。図に於いて、PC1及びPC2は受光素子部
分をそれぞれ示し、破線はn+ −InGaAsキャリヤ
拡散抑止層がある場合(本発明)の特性線、実線はn+
−InGaAsキャリヤ拡散抑止層がない場合(実験
例)の特性線をそれぞれ示している。
FIG. 2 is a diagram showing the photosensitivity in the case where the semiconductor light receiving device is irradiated with spot-like light and one-dimensionally scanned, and the photosensitivity is plotted on the vertical axis and the position is plotted on the horizontal axis. It is taken. In the figure, PC1 and PC2 respectively indicate the light receiving element portion, the broken line is the characteristic line in the case where the n + -InGaAs carrier diffusion suppressing layer is present (the present invention), and the solid line is the n +
The characteristic lines in the case where there is no -InGaAs carrier diffusion suppression layer (experimental example) are shown.

【0017】図から明らかなように、受光素子部分PC
1及びPC2に於ける光感度は本発明のものも実験例に
依るものも変わりないが、受光素子部分PC1とPC2
との間では、本発明のものでは、その中央で零になって
いるが、実験例のものでは、かなりの光感度をもってし
まうことが看取され、本発明の効果が明らかである。
As is apparent from the figure, the light receiving element portion PC
The photosensitivities of the light receiving element portions PC1 and PC2 are the same as those of the present invention and those of the experimental example.
In the meantime, in the case of the present invention, the value is zero in the center of the present invention, but it is observed that the experimental example has a considerable photosensitivity, and the effect of the present invention is clear.

【0018】[0018]

【実施例】図3乃至図5は本発明一実施例を製造する工
程を解説する為の工程要所に於ける半導体受光装置の要
部切断側面図を表し、以下、これ等の図を参照しつつ詳
細に説明する。尚、図1及び図6に於いて用いた記号と
同記号は同部分を表すか或いは同じ意味を持つものとす
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIGS. 3 to 5 are side sectional views of essential parts of a semiconductor light receiving device at a process step for explaining a process for manufacturing an embodiment of the present invention. The details will be described. The same symbols as those used in FIGS. 1 and 6 represent the same parts or have the same meanings.

【0019】図3参照 3−(1) 気相エピタキシャル成長(vapor phase e
pitaxy:VPE)法を適用することに依り、n+
−InP基板1上にn−InPバッファ層2、n+ −I
nGaAsキャリヤ拡散抑止層11、n−InGaAs
光吸収層3、n+ −InGaAsキャリヤ拡散抑止層1
2、n−InPウインドウ層4を成長させる。
See FIG. 3 3- (1) Vapor phase epitaxial growth
pitaxy: VPE) method depends on applying the, n +
N-InP buffer layer 2, n + -I on -InP substrate 1
nGaAs carrier diffusion suppression layer 11, n-InGaAs
Light absorption layer 3, n + -InGaAs carrier diffusion suppression layer 1
2. Grow the n-InP window layer 4.

【0020】ここで成長させた各半導体層に関する主要
なデータを例示すると次の通りである。 バッファ層2について 厚さ:1〔μm〕 不純物濃度:1〜2×1016〔cm-3〕 キャリヤ拡散抑止層11について 厚さ:500〔Å〕乃至1000〔Å〕 不純物濃度:1〜5×1017〔cm-3
The main data regarding each semiconductor layer grown here is illustrated as follows. About the buffer layer 2 Thickness: 1 [μm] Impurity concentration: 1 to 2 × 10 16 [cm −3 ] About carrier diffusion suppression layer 11 Thickness: 500 [Å] to 1000 [Å] Impurity concentration: 1 to 5 × 10 17 [cm -3 ]

【0021】 光吸収層3について 厚さ:2〔μm〕乃至2.5〔μm〕 不純物濃度:1〜5×1015〔cm-3〕 キャリヤ拡散抑止層12について 厚さ:500〔Å〕乃至1000〔Å〕 不純物濃度:1〜5×1017〔cm-3〕 ウインドウ層4について 厚さ:0.5〔μm〕乃至1〔μm〕 不純物濃度:5〜10×1015〔cm-3Regarding the light absorption layer 3 Thickness: 2 [μm] to 2.5 [μm] Impurity concentration: 1 to 5 × 10 15 [cm −3 ] Carrier diffusion suppressing layer 12 Thickness: 500 [Å] to 1000 [Å] Impurity concentration: 1 to 5 × 10 17 [cm −3 ] Regarding the window layer 4 Thickness: 0.5 [μm] to 1 [μm] Impurity concentration: 5 to 10 × 10 15 [cm −3 ]

【0022】図4参照 4−(1) プラズマCVD(plasma chemical v
apour deposition)法を適用すること
に依り、厚さ例えば2000〔Å〕のSiNx 膜13を
形成する。 4−(2) リソグラフィ技術に於けるレジスト・プロセス及びエッ
チャントをフッ化水素酸とフッ化アンモニウムとの混合
液とするウエット・エッチング法を適用することに依
り、SiNx 膜13を選択的にエッチングしてウインド
ウ領域形成用開口13Aを形成する。
See FIG. 4 4- (1) Plasma CVD (plasma chemical v)
The SiN x film 13 having a thickness of, for example, 2000 [Å] is formed by applying the apour deposition method. 4- (2) The SiN x film 13 is selectively etched by applying a resist process in the lithography technique and a wet etching method using an etchant as a mixed liquid of hydrofluoric acid and ammonium fluoride. Then, the window region forming opening 13A is formed.

【0023】4−(3) 熱拡散法を適用することに依り、温度を500〔℃〕、
そして、時間を15〔分〕とし、燐化亜鉛の拡散源から
ウインドウ領域形成用開口13Aを介してn−InPウ
インドウ層4の表面からn+ −InGaAsキャリヤ拡
散抑止層12を貫通してn−InGaAs光吸収層3に
達するZnの拡散を行って不純物濃度が1×1018〔cm
-3〕程度であるp+ −ウインドウ領域6を形成する。
4- (3) By applying the thermal diffusion method, the temperature is 500 [° C.],
Then, the time is set to 15 minutes, the zinc phosphide diffusion source penetrates the n + -InGaAs carrier diffusion suppression layer 12 from the surface of the n-InP window layer 4 through the window region forming opening 13A, and n- Zn is diffused to reach the InGaAs light absorption layer 3 so that the impurity concentration is 1 × 10 18 [cm
The p + -window region 6 having a size of about −3 ] is formed.

【0024】図5参照 5−(1) プラズマCVD法を適用することに依り、厚さ例えば2
000〔Å〕のSiNx からなる無反射コーティング膜
7を形成する。
See FIG. 5 5- (1) By applying the plasma CVD method, the thickness is, for example, 2
The anti-reflection coating film 7 made of SiN x of 000 [Å] is formed.

【0025】5−(2) リソグラフィ技術に於けるレジスト・プロセス及びエッ
チャントをフッ化水素酸とフッ化アンモニウムとの混合
液とするウエット・エッチング法を適用することに依
り、無反射コーティング膜7を選択的にエッチングして
p側電極コンタクト窓を形成する。 5−(3) この後、通常の技法、例えば真空蒸着法及びリフト・オ
フ法などを適用し、AuZnからなるp側電極8やAu
Geからなるn側電極9を形成して完成する。
5- (2) By applying a resist process in the lithography technique and a wet etching method using an etchant as a mixed solution of hydrofluoric acid and ammonium fluoride, the antireflection coating film 7 is formed. Selective etching is performed to form a p-side electrode contact window. 5- (3) Thereafter, a normal technique such as a vacuum vapor deposition method and a lift-off method is applied to apply the p-side electrode 8 made of AuZn or Au.
The n-side electrode 9 made of Ge is formed and completed.

【0026】このようにして得られた半導体受光装置
は、図1について説明した原理に依って、メサ溝を形成
しなくてもクロス・トークは発生せず、勿論、表面は平
坦である。
According to the principle described with reference to FIG. 1, the semiconductor light-receiving device thus obtained does not cause cross talk even if the mesa groove is not formed, and of course the surface is flat.

【0027】[0027]

【発明の効果】本発明に依る半導体受光装置に於いて
は、禁制帯幅Eg1及びEg2及びEg3が Eg1>Eg2及びEg3>Eg2 なる関係にあって且つ順に積層形成されてヘテロ接合構
造を構成する禁制帯幅がEg1である一導電型の第一の化
合物半導体層及び禁制帯幅がEg2である一導電型の第二
の化合物半導体層及び禁制帯幅がEg3である一導電型の
第三の化合物半導体層と、ヘテロ接合構造に於ける各ヘ
テロ界面に介挿され禁制帯幅がEg2であると共に該第二
の化合物半導体層に比較して充分に高濃度の一導電型不
純物を含有した化合物半導体薄膜と、表面から第二の化
合物半導体層に達する深さ及び所定間隔を維持して並列
された複数の反対導電型不純物拡散領域とを備える。
In the semiconductor light receiving device according to the present invention, the forbidden band widths E g1 and E g2 and E g3 have a relationship of E g1 > E g2 and E g3 > E g2 and are formed in order. Forming a heterojunction structure, the first conductivity type first compound semiconductor layer having a forbidden band width of E g1 and the second conductivity type second compound semiconductor layer having a forbidden band width of E g2 and the forbidden band width E A third conductivity type third compound semiconductor layer of g3 and a forbidden band width of E g2 which is inserted at each hetero interface in the heterojunction structure and is sufficiently compared with the second compound semiconductor layer. A compound semiconductor thin film containing a high concentration of one conductivity type impurity, and a plurality of opposite conductivity type impurity diffusion regions arranged in parallel while maintaining a depth reaching a second compound semiconductor layer from the surface and a predetermined interval.

【0028】前記本発明の構成に依れば、例えばバッフ
ァ層である第一の化合物半導体層と光吸収層である第二
の化合物半導体層との間及びその第二の化合物半導体層
とウインドウ層である第三の化合物半導体層との間には
第二の化合物半導体層と同じ材料からなり、しかも、高
不純物濃度のキャリヤ拡散抑止層である化合物半導体薄
膜が存在しているので、ヘテロ界面に於けるキャリヤの
拡散長を短くすることができ、従来のようなメサ溝を形
成しなくても、実効的に光感度を有する面積は狭くなっ
て、素子間のクロス・トークは低減される。また、メサ
溝を形成していないから、大きな段差は存在せず、従っ
て、無反射コーティング膜の段差切れなど段差に起因す
る種々な問題を解消することができる。
According to the structure of the present invention, for example, between the first compound semiconductor layer which is a buffer layer and the second compound semiconductor layer which is a light absorption layer, and between the second compound semiconductor layer and the window layer. Since a compound semiconductor thin film which is the same material as the second compound semiconductor layer and which is a carrier diffusion suppressing layer having a high impurity concentration is present between the third compound semiconductor layer which is The diffusion length of carriers in the carrier can be shortened, and the area having an effective photosensitivity becomes narrower without forming a mesa groove as in the conventional case, and cross talk between elements can be reduced. Further, since the mesa groove is not formed, there is no large step, and therefore various problems caused by the step, such as step breakage of the antireflection coating film, can be solved.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の原理を説明する為の半導体受光装置を
表す要部切断側面図である。
FIG. 1 is a side sectional view showing a main part of a semiconductor light receiving device for explaining the principle of the present invention.

【図2】半導体受光装置にスポット状の光を照射して一
次元走査を行った場合の光感度を表す線図である。
FIG. 2 is a diagram showing photosensitivity when a semiconductor light receiving device is irradiated with spot-like light and one-dimensional scanning is performed.

【図3】本発明一実施例を製造する工程を解説する為の
工程要所に於ける半導体受光装置の要部切断側面図であ
る。
FIG. 3 is a side sectional view of a main part of a semiconductor light receiving device at a process key point for explaining a process for manufacturing an embodiment of the present invention.

【図4】本発明一実施例を製造する工程を解説する為の
工程要所に於ける半導体受光装置の要部切断側面図であ
る。
FIG. 4 is a side sectional view of a main part of a semiconductor light receiving device at a process key point for explaining a process for manufacturing an embodiment of the present invention.

【図5】本発明一実施例を製造する工程を解説する為の
工程要所に於ける半導体受光装置の要部切断側面図であ
る。
FIG. 5 is a cutaway side view of a main part of the semiconductor light receiving device at a process key point for explaining a process for manufacturing the embodiment of the present invention.

【図6】クロス・トークを防止する構成を備えた半導体
受光装置の従来例を表す要部切断側面図である。
FIG. 6 is a cutaway side view of a main part showing a conventional example of a semiconductor light receiving device having a structure for preventing cross talk.

【符号の説明】[Explanation of symbols]

1 n+ −InP基板 2 n−InPバッファ層 3 n−InGaAs光吸収層 4 n−InPウインドウ層 5 素子間を分離する為のメサ溝 6 p+ −ウインドウ領域 7 SiNx からなる無反射コーティング膜 8 p側電極 9 n側電極 11 n+ −InGaAsキャリヤ拡散抑止層 12 n+ −InGaAsキャリヤ拡散抑止層 13 SiNx 膜 13A 開口 PC1 受光素子部分 PC2 受光素子部分Anti-reflective coating film composed of a window region 7 SiN x - 1 n + -InP mesa groove 6 for separating between the substrate 2 n-InP buffer layer 3 n-InGaAs light absorbing layer 4 n-InP window layer 5 element p + 8 p-side electrode 9 n-side electrode 11 n + -InGaAs carrier diffusion suppression layer 12 n + -InGaAs carrier diffusion suppression layer 13 SiN x film 13A opening PC1 light receiving element portion PC2 light receiving element portion

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】禁制帯幅Eg1及びEg2及びEg3が Eg1>Eg2及びEg3>Eg2 なる関係にあって且つ順に積層形成されてヘテロ接合構
造を構成する禁制帯幅がEg1である一導電型の第一の化
合物半導体層及び禁制帯幅がEg2である一導電型の第二
の化合物半導体層及び禁制帯幅がEg3である一導電型の
第三の化合物半導体層と、 該ヘテロ接合構造に於ける各ヘテロ界面に介挿され禁制
帯幅がEg2であると共に該第二の化合物半導体層に比較
して充分に高濃度の一導電型不純物を含有した化合物半
導体薄膜と、 表面から第二の化合物半導体層に達する深さ及び所定間
隔を維持して並列された複数の反対導電型不純物拡散領
域とを備えてなることを特徴とする半導体受光装置。
1. The forbidden band widths E g1 and E g2 and E g3 are in a relation of E g1 > E g2 and E g3 > E g2 and are formed in order to form a heterojunction structure. One conductivity type first compound semiconductor layer having g1 and one conductivity type second compound semiconductor layer having a forbidden band width E g2 and one conductivity type third compound semiconductor having a forbidden band width E g3 And a compound having a forbidden band width of E g2 interposed at each hetero interface in the heterojunction structure and containing a sufficiently high concentration of one conductivity type impurity as compared with the second compound semiconductor layer. A semiconductor light receiving device comprising: a semiconductor thin film; and a plurality of opposite-conductivity-type impurity diffusion regions arranged in parallel while maintaining a depth reaching a second compound semiconductor layer from the surface and a predetermined interval.
【請求項2】第一の化合物半導体層及び第二の化合物半
導体層及び第三の化合物半導体層がInP層及びInG
aAs層及びInP層であることを特徴とする請求項1
記載の半導体受光装置
2. The first compound semiconductor layer, the second compound semiconductor layer and the third compound semiconductor layer are InP layers and InG.
2. An aAs layer and an InP layer.
Described semiconductor light receiving device
JP3307455A 1991-11-22 1991-11-22 Semiconductor light receiving device Withdrawn JPH05160428A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3307455A JPH05160428A (en) 1991-11-22 1991-11-22 Semiconductor light receiving device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3307455A JPH05160428A (en) 1991-11-22 1991-11-22 Semiconductor light receiving device

Publications (1)

Publication Number Publication Date
JPH05160428A true JPH05160428A (en) 1993-06-25

Family

ID=17969274

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3307455A Withdrawn JPH05160428A (en) 1991-11-22 1991-11-22 Semiconductor light receiving device

Country Status (1)

Country Link
JP (1) JPH05160428A (en)

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