JPH05160130A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To prevent disconnection and short-circuiting failure due to electromigration of a metal wiring in a semiconductor device and at the same time enable resistance against heat treatment in a post process and moisture resistance of the completed semiconductor device to be improved. CONSTITUTION:A barrier metal 3, an Al wiring 1, and a lamination film 4 are formed in sequence on a lower-layer layer insulation film 2 and then a conductive metal layer 11 (line width: 1mum or less) is formed on it by lithography, which is subjected to anisotropic etching by a reactivity ion etching. Then, the conductive metal layer 11 is deposited on it, which is subjected to etching by the reactive ion etching until a lamination film 4 appears.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a device structure for improving reliability against disconnection and short circuit failure of metal wiring, and a method for manufacturing the same.

[0002]

2. Description of the Related Art FIG.
Proceedings of JSAP Autumn Meeting, P591, 27
10 is a cross-sectional view showing a conventional laminated Al wiring shown in "a-9 Ekuyama et al."

In the figure, 1 is Al (or Al alloy containing several% of Si, Cu, etc.) wiring, 2 is Al wiring 1
And a lower interlayer insulating film 3 for insulating the semiconductor element formed on the semiconductor substrate from the Al wiring layer 1 when the Al wiring 1 forms a contact with the lower semiconductor element. It is a barrier metal that prevents mutual diffusion and chemical reaction.

Reference numeral 4 is a laminated film made of a metal such as Ti or W or an alloy thereof formed to enhance the resistance of the Al wiring 1 to electromigration. Here, electromigration is the movement of electrons from one atom to another due to the collision of electrons flowing through the conductor with the conductor atoms, causing the conductor atoms to move. Then, it is a phenomenon that a projection called hillock is formed by the accumulation of atoms.

Reference numeral 6 denotes an upper interlayer insulating film formed above the Al wiring 1, and 9 denotes an upper interlayer insulating film when the upper interlayer insulating film 6 is formed.
This is a void-like space generated by the step of the Al wiring 1 not being able to completely fill the upper interlayer insulating film 6. The upper interlayer insulating film 6 is A
When the 1-wiring 1 has two or more layers, it serves as an interlayer insulating film with the upper wiring, and when the Al-wiring 1 has a single layer, it serves as a wiring protective film.

When the laminated film 4 is formed on the Al wiring 1, electromigration occurs and voids are formed in the Al wiring 1. Even if the Al wiring 1 is about to be broken, the laminated film 4 does not cause electromigration. The conductivity is maintained and the reliability of the Al wiring 1 is improved.

[0007]

Since the conventional laminated Al wiring is constructed as described above, it is possible to prevent disconnection due to the occurrence of electromigration voids. However, in the wiring technology of 1.0 μm rule or less, Al wiring In No. 1, since the upper part is covered with the laminated film 4, there is a problem that the ratio of side hillocks (hillocks grow in the lateral direction) is increased and a short circuit defect easily occurs.

Further, in the case of wiring having a thickness of 1.0 μm or less, the distance between the wirings is reduced and the Al wiring 1 is formed when the upper interlayer insulating film 6 is formed.
Has a vertical side wall, the upper interlayer insulating film 6 is not filled in the gap between the Al wirings 1 and a void space 9 is generated, and the void space 9 is expanded by a heat treatment in a later process, and the semiconductor device is expanded. It was a cause of defects such as damage to the product and deterioration of the moisture resistance of the completed semiconductor device.

The present invention has been made in order to solve the above problems, and prevents disconnection and short-circuiting defects due to electromigration of metal wiring in a semiconductor device, and also has resistance to heat treatment in a subsequent step and completed. An object is to improve the moisture resistance of a semiconductor device.

[0010]

In a semiconductor device according to the present invention, a side wall of a conductive metal, which is unlikely to cause electromigration, is formed on a side surface of a metal wiring, and a side surface of the metal wiring is inclined.

[0011]

Function: Side hillocks due to electromigration of metal wiring are suppressed, disconnection due to voids is prevented, and generation of voids is suppressed. .

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional view showing a laminated Al wiring according to an embodiment of the present invention. Reference numeral 5 is made of a conductive metal such as Ti, W, V, and Mo or their alloys (Ti-N, W-Si) in which electromigration does not easily occur, and a conductive metal side is formed on both sides of the Al wiring 1 with inclination. It is a wall, and is otherwise the same as FIG. 7.

The manufacturing method will be described below. In FIG. 5, 10 is a resist pattern, and 11 is a conductive metal layer made of a material having a high selection ratio with the laminated film 4 in the reactive ion etching (the conductive metal layer 11 is etched but the laminated film 4 is hardly etched). ).

First, a barrier metal 3, an Al wiring 1, and a laminated film 4 are sequentially formed on the lower interlayer insulating film 2. A resist pattern 10 (line width 1
(μm or less) is formed (FIG. 5A). This is anisotropically etched by reactive ion etching to form a wiring pattern shown in FIG. 5 (b).

Then, a conductive metal layer 11 is deposited thereon (FIG. 5 (c)), and this is etched by reactive ion etching until the laminated film 4 appears, and then FIG. 5 (d).
The state shown in is obtained. Since the laminated film 4 is hardly etched by the reactive ion etching as compared with the conductive metal layer 11, the thickness and the like hardly change.

The conductive metal layer 11 is deposited in a mountain shape as shown in FIG. 5C, and the conductive metal sidewall 5 is formed by anisotropically etching the conductive metal layer 11. Therefore, the shape of the conductive metal layer 11 is changed. The side surfaces of the conductive metal sidewall 5 are inherited by the conductive metal sidewall 5 and are inclined.

In the above embodiment, the conductive metal layer 11 is made of the laminated film 4 and the material having a high selection ratio with respect to the laminated film 4 in the reactive ion etching, but the laminated film 4 and the material having a low etching selection ratio may be used. Good.

FIG. 6 is a cross-sectional view showing a method of manufacturing an Al wiring according to an embodiment of the present invention when a material having a low selection ratio is used as the material for the conductive metal sidewall 5 with the laminated film 4.

Reference numeral 11a is a conductive metal layer made of W having a low selection ratio to the laminated film 4 in the reactive ion etching.
Is a high selectivity mask material having a thickness of about 0.1 μm and made of silicon oxide having a high selectivity with the conductive metal layer 11a in the reactive ion etching.

A barrier metal 3, A is formed on the lower interlayer insulating film 2.
The l wiring 1 and the laminated film 4 are formed, and the high selection ratio mask material 12 is further formed thereon. A resist pattern 10 is formed thereon by photolithography (FIG. 6).
(A)). This is etched by the reactive ions contained in the gas plasma to obtain the state shown in FIG. 6 (b).

A conductive metal layer 11a is deposited on the state (FIG. 6 (c)) and then etched by the reactive ions contained in the gas plasma to obtain the state of FIG. 6 (d).
Here, the laminated film 4 has no difference in etching rate from the conductive metal layer 11a, but the laminated film 4 is not etched because the high selection ratio mask material 12 is present on the laminated film 4.

Finally, when the etching process is performed by gas plasma containing reactive ions capable of etching silicon oxide, the high selectivity mask material 12 is removed, and the lower interlayer insulating film 2 made of silicon oxide is used as the high selectivity mask material. The Al wiring 1 is formed with the conductive metal sidewall 5 in the state of FIG. 6E in which the step 13 is formed by etching by the thickness of 12.

Although the laminated film 4 is formed on the Al wiring 1 in the above embodiment, the Al wiring 1 is formed as shown in FIG.
It can also be applied when the laminated film 4 is not formed thereon. Further, as shown in FIGS. 3 and 4, the upper layer Al wiring 7 is formed on the Al wiring 1.
3 is present, the Al wiring 1 and the upper layer A in the case where the laminated film 4 in FIG. 4 is not present are more than in the case where the laminated film 4 in FIG.
The contact resistance of the contact portion 8 of the l-wiring 7 is low.

In the above embodiment, A is used as the wiring material.
Although 1 is described, it can be applied to the case of other metal wiring (Cu, Au, etc.) where electromigration easily occurs.

[0025]

As described above, according to the present invention, the side wall of the metal wiring is formed with the side wall of the conductive metal which is unlikely to cause electromigration, so that the semiconductor manufacturing apparatus having high reliability without disconnection or short circuit failure. There is an effect that can be easily formed.

Since the metal wiring has a trapezoidal cross section,
Even if the metal wiring becomes finer and the interval becomes narrower, a void-like space is not generated when depositing the interlayer insulating film, the resistance to the heat treatment in the subsequent process is improved, and the moisture resistance of the completed semiconductor device is improved. It has the effect of improving.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a metal wiring portion of a semiconductor device showing an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a case where the laminated film 4 of FIG. 1 is not provided.

FIG. 3 is a sectional view of a contact portion of a two-layer Al wiring showing another embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a case where the laminated film 4 of FIG. 3 is not provided.

5 is a cross-sectional view showing one embodiment of a manufacturing process of the metal wiring part of FIG.

FIG. 6 is a cross-sectional view showing another embodiment of the manufacturing process of the metal wiring part of FIG.

FIG. 7 is a cross-sectional view of a metal wiring portion of a conventional semiconductor device.

[Explanation of symbols]

 1 Al wiring 2 Lower interlayer insulating film 3 Barrier metal 4 Laminated film 5 Conductive metal sidewall 6 Upper interlayer insulating film

Claims (2)

[Claims] 1. A wiring comprising a metal formed on a semiconductor substrate, and a sidewall formed of a metal which is unlikely to cause electromigration unlike the wiring and formed on a side surface of the wiring with an inclination angle. Semiconductor device. 2. A step of depositing a metal on which electromigration is unlikely to occur on a substrate on which metal wiring is formed, and anisotropically etching the metal deposited on the metal wiring until the upper portion of the metal wiring is exposed. A method of manufacturing a semiconductor device, which comprises a step of etching.