JPH05160084A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH05160084A JPH05160084A JP32720691A JP32720691A JPH05160084A JP H05160084 A JPH05160084 A JP H05160084A JP 32720691 A JP32720691 A JP 32720691A JP 32720691 A JP32720691 A JP 32720691A JP H05160084 A JPH05160084 A JP H05160084A
- Authority
- JP
- Japan
- Prior art keywords
- contact
- gas
- etching
- alumina
- post
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
係り, 特にコンタクトホール形成後の後処理に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device, and more particularly to post-treatment after forming a contact hole.
【0002】半導体装置の高集積化, 高速化に伴い, 下
層配線と上層配線を結ぶコンタクト技術はより難しくな
ってきている。特に, コンタクトホール形成のためのエ
ッチング後のコンタクト面は従来より一層清浄化する必
要がある。As the integration and speed of semiconductor devices have increased, contact technology for connecting lower layer wiring and upper layer wiring has become more difficult. In particular, the contact surface after etching for forming the contact hole needs to be cleaned more than before.
【0003】[0003]
【従来の技術】従来のコンタクトホール形成のためのエ
ッチング後の後処理方法として, フッ素系ガスを用いて
コンタクト面を少量エッチングして基板表面に付着した
堆積物あるいは基板表面に形成された損傷層を除去して
いた。2. Description of the Related Art As a conventional post-etching post-treatment method for forming contact holes, a small amount of the contact surface is etched with a fluorine-based gas to deposit on the substrate surface or a damaged layer formed on the substrate surface Had been removed.
【0004】しかし,エッチング後の付着物としてアル
ミナが存在することもあり,このアルミナは従来法では
除去困難であったが, 従来の半導体装置はコンタクト面
が大きかったので, コンタクト面のエッチングによりア
ルミナ付着物をリフトオフにより除去していた。ところ
が,半導体装置の微細化に伴いコンタクト面が小さくな
るにつれてアルミナ付着物を除去しにくくなってきた。However, since alumina may be present as deposits after etching, it is difficult to remove this alumina by the conventional method. However, since the contact surface of the conventional semiconductor device is large, the alumina is removed by etching the contact surface. The deposit was removed by lift-off. However, as the contact surface becomes smaller with the miniaturization of semiconductor devices, it has become difficult to remove alumina deposits.
【0005】[0005]
【発明が解決しようとする課題】従来例の後処理では良
好なコンタクト特性が得られず, 半導体装置の高集積化
と高速化の妨げとなっていた。Good contact characteristics cannot be obtained by the post-treatment of the conventional example, which hinders high integration and high speed of semiconductor devices.
【0006】本発明はコンタクトエッチング後のアルミ
ナ付着物を完全に除去して良好なコンタクト特性を得る
後処理方法の提供を目的とする。An object of the present invention is to provide a post-treatment method for completely removing alumina deposits after contact etching to obtain good contact characteristics.
【0007】[0007]
【課題を解決するための手段】上記課題の解決は,1)
被処理基板上に被着された絶縁膜にコンタクトホールを
形成するエッチング工程と,次いで,四臭化炭素(CBr4)
あるいは三塩化硼素(BCl3)あるいは四塩化炭素(CCl4)あ
るいは三臭化硼素(BBr3)を含むガスのプラズマを用いて
該被処理基板のドライエッチングを行う後処理工程とを
有する半導体装置の製造方法,あるいは2)前記後処理
工程で前記のガスとフッ素系ガスの混合ガスを用いるこ
とを特徴とする前記1)記載の半導体装置の製造方法,
あるいは,3)前記後処理工程で前記のガスを用いてド
ライエッチングを行い,次いでフッ素系ガスを用いてド
ライエッチングを行う前記1)記載の半導体装置の製造
方法により達成される。[Means for Solving the Problems] 1)
Etching process to form contact holes in the insulating film deposited on the substrate to be processed, and then carbon tetrabromide (CBr 4 )
Alternatively, a semiconductor device having a post-treatment step of dry etching the substrate to be treated using plasma of a gas containing boron trichloride (BCl 3 ) or carbon tetrachloride (CCl 4 ) or boron tribromide (BBr 3 ). Or 2) a method of manufacturing a semiconductor device according to 1), wherein a mixed gas of the gas and a fluorine-based gas is used in the post-treatment step.
Alternatively, 3) it is achieved by the method of manufacturing a semiconductor device according to 1), in which dry etching is performed using the gas in the post-treatment step, and then dry etching is performed using a fluorine-based gas.
【0008】[0008]
【作用】本発明では,後処理として四臭化炭素(CBr4)あ
るいは三塩化硼素(BCl3)あるいは四塩化炭素(CCl4)ある
いは三臭化硼素(BBr3)のプラズマを用いることにより,
次の反応式に示されるようにアルミナ(Al2O3) を除去し
ている。In the present invention, by using a plasma of carbon tetrabromide (CBr 4 ) or boron trichloride (BCl 3 ) or carbon tetrachloride (CCl 4 ) or boron tribromide (BBr 3 ) as a post-treatment,
Alumina (Al 2 O 3 ) is removed as shown in the following reaction formula.
【0009】 Al2O3+CBr4→ AlBr3↑+ CBr2O↑ Al2O3+BCl3→ AlCl3↑+BCl2O↑ Al2O3+CCl4→ AlBr3↑+(CCl3)2O↑ Al2O3+BBr3→ AlBr3↑+Br2O↑ 上式のように, CBr4等のプラズマによりアルミナ付着物
を気化して除去し, さらにコンタクト面を清浄にするた
め, 通常のようにフッ素系ガスを用いてコンタクト面を
少量エッチングする。Al 2 O 3 + CBr 4 → AlBr 3 ↑ + CBr 2 O ↑ Al 2 O 3 + BCl 3 → AlCl 3 ↑ + BCl 2 O ↑ Al 2 O 3 + CCl 4 → AlBr 3 ↑ + (CCl 3 ) 2 O ↑ Al 2 O 3 + BBr 3 → AlBr 3 ↑ + Br 2 O ↑ As in the above formula, the alumina deposits are vaporized and removed by the plasma such as CBr 4 , and the contact surface is cleaned. A small amount of the contact surface is etched using a system gas.
【0010】この場合, CBr4等とフッ素系ガスの混合ガ
スを用いてアルミナ除去とコンタクト面エッチングを同
時に行ってもよいし,あるいはCBr4等とフッ素系ガスを
この順に用いて2ステップでエッチングを行ってもよ
い。[0010] etching this case, may be carried out at the same time the alumina removed and the contact surface etched with a mixed gas of CBr 4 or the like and the fluorine-based gas, or CBr 4 or the like and a fluorine-based gas in two steps using in this order You may go.
【0011】ただし,本発明ではCBr4プラズマを用いる
ので,処理室内のプラズマに曝される部分はアルミニウ
ム(Al)またはアルミナ材で構成しないようにする。However, since CBr 4 plasma is used in the present invention, the portion exposed to the plasma in the processing chamber is not made of aluminum (Al) or alumina material.
【0012】[0012]
【実施例】図1は実施例に使用した処理装置の模式断面
図である。図において,1は処理室,2はガス導入口,
3は排気口,4は基板側電極,5は対向電極,6はRF
電源,7は被処理基板である。EXAMPLE FIG. 1 is a schematic sectional view of a processing apparatus used in the example. In the figure, 1 is a processing chamber, 2 is a gas inlet,
3 is an exhaust port, 4 is a substrate side electrode, 5 is a counter electrode, 6 is RF
A power source, 7 is a substrate to be processed.
【0013】実施例(1) :図の装置を用い,被処理基板
上に被着された二酸化シリコン(SiO2)からなる絶縁膜に
コンタクトホール形成のためのコンタクトエッチを, CH
F3/CF4/Ar を用いた反応性イオンエッチング(RIE) によ
り行う。Example (1): Using the apparatus shown in the figure, contact etching for forming a contact hole was performed on an insulating film made of silicon dioxide (SiO 2 ) deposited on a substrate to be processed by CH etching.
It is carried out by reactive ion etching (RIE) using F 3 / CF 4 / Ar.
【0014】このエッチング時, コンタクト面はカーボ
ン系ポリマおよびアルミナ等の膜に覆われている。次い
で, 後処理としてCBr4/NF3/Ar をそれぞれ流量20/20/60
SCCM で流し, RF電力50 W, ガス圧力 0.2 Torr の条
件で,RIE を30秒間行う。During this etching, the contact surface is covered with a film of carbon-based polymer and alumina. Then, CBr 4 / NF 3 / Ar was added as a post-treatment at a flow rate of 20/20/60, respectively.
Flow with SCCM, RIE for 30 seconds under conditions of RF power of 50 W and gas pressure of 0.2 Torr.
【0015】この際, コンタクト面 (シリコン面) の掘
られた深さは約 100Åであった。実施例では, CBr4とフ
ッ素系ガスの混合ガスを用いてアルミナ除去とコンタク
ト面エッチングを同時に行っているが, まず CBr4/Arを
用いてRIE を行い, 次いでNF3/Arを用いてRIE を行って
もよい。At this time, the dug depth of the contact surface (silicon surface) was about 100Å. In the example, alumina removal and contact surface etching were performed simultaneously using a mixed gas of CBr 4 and a fluorine-based gas.First, RIE was performed using CBr 4 / Ar and then RIE was performed using NF 3 / Ar. You may go.
【0016】実施例(2) :図の装置を用い,被処理基板
上に被着されたSiO2からなる絶縁膜にコンタクトホール
形成のためのコンタクトエッチを, CHF3/CF4/Ar を用い
たRIE により行う。Example (2): Using the apparatus shown in the figure, contact etching for forming contact holes was performed on the insulating film made of SiO 2 deposited on the substrate to be processed, and CHF 3 / CF 4 / Ar was used. It will be done by RIE.
【0017】このエッチング時, コンタクト面はカーボ
ン系ポリマおよびアルミナ等の膜に覆われている。次い
で, 後処理としてBCl3/Ar あるいはCCl4/Ar をそれぞれ
流量20/80 SCCMで流し, RF電力50 W, ガス圧力 0.2 T
orrの条件で,RIE を30秒間行う。During this etching, the contact surface is covered with a film of carbon-based polymer and alumina. Then, as a post-treatment, BCl 3 / Ar or CCl 4 / Ar was made to flow at a flow rate of 20/80 SCCM, RF power of 50 W and gas pressure of 0.2 T.
RIE is performed for 30 seconds under the condition of orr.
【0018】この際, コンタクト面の掘られた深さは約
60Åであった。 実施例(3):図の装置を用い,被処理基板上に被着され
たSiO2からなる絶縁膜にコンタクトホール形成のための
コンタクトエッチを,CHF3/CF4/Ar を用いたRIE により
行う。At this time, the dug depth of the contact surface is about
It was 60Å. Example (3): Using the apparatus shown in the figure, contact etching for forming contact holes was performed on the insulating film made of SiO 2 deposited on the substrate to be processed by RIE using CHF 3 / CF 4 / Ar. To do.
【0019】このエッチング時, コンタクト面はカーボ
ン系ポリマおよびアルミナ等の膜に覆われている。次い
で, 後処理としてBBr3/NF3/Ar をそれぞれ流量20/20/60
SCCM で流し, RF電力50 W, ガス圧力 0.2 Torr の条
件で,RIE を30秒間行う。During this etching, the contact surface is covered with a film of carbon-based polymer, alumina or the like. Then, as a post-treatment, BBr 3 / NF 3 / Ar was used at a flow rate of 20/20/60, respectively.
Flow with SCCM, RIE for 30 seconds under conditions of RF power of 50 W and gas pressure of 0.2 Torr.
【0020】この際, コンタクト面の掘られた深さは約
80Åであった。At this time, the dug depth of the contact surface is about
It was 80Å.
【0021】[0021]
【発明の効果】本発明によれば, コンタクトエッチング
後のアルミナ付着物を完全に除去でき良好なコンタクト
特性を得ることができた。この結果, 微細面積のコンタ
クトが可能となり, 半導体装置の高集積化, 高速化に寄
与することができた。According to the present invention, alumina deposits after contact etching can be completely removed, and good contact characteristics can be obtained. As a result, it became possible to make contact in a fine area and contribute to higher integration and higher speed of semiconductor devices.
【図1】 実施例に使用した処理装置の模式断面図FIG. 1 is a schematic sectional view of a processing apparatus used in Examples.
1 処理室 2 ガス導入口 3 排気口 4 基板側電極 5 対向電極 6 RF電源 7 被処理基板 1 processing chamber 2 gas inlet port 3 exhaust port 4 substrate side electrode 5 counter electrode 6 RF power source 7 substrate to be processed
Claims (3)
タクトホールを形成するエッチング工程と, 次いで,四臭化炭素(CBr4)あるいは三塩化硼素(BCl3)あ
るいは四塩化炭素(CCl4)あるいは三臭化硼素(BBr3)を含
むガスのプラズマを用いて該被処理基板のドライエッチ
ングを行う後処理工程とを有することを特徴とする半導
体装置の製造方法。1. An etching process for forming a contact hole in an insulating film deposited on a substrate to be processed, and then carbon tetrabromide (CBr 4 ) or boron trichloride (BCl 3 ) or carbon tetrachloride (CCl 4). 4 ) or a post-treatment step of dry etching the substrate to be treated using plasma of a gas containing boron tribromide (BBr 3 ).
ガスの混合ガスを用いることを特徴とする請求項1記載
の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein a mixed gas of the gas and a fluorine-based gas is used in the post-treatment step.
ライエッチングを行い,次いでフッ素系ガスを用いてド
ライエッチングを行うことを特徴とする請求項1記載の
半導体装置の製造方法。3. The method of manufacturing a semiconductor device according to claim 1, wherein in the post-processing step, dry etching is performed using the gas, and then dry etching is performed using a fluorine-based gas.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32720691A JPH05160084A (en) | 1991-12-11 | 1991-12-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP32720691A JPH05160084A (en) | 1991-12-11 | 1991-12-11 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH05160084A true JPH05160084A (en) | 1993-06-25 |
Family
ID=18196503
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP32720691A Withdrawn JPH05160084A (en) | 1991-12-11 | 1991-12-11 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH05160084A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07230993A (en) * | 1994-02-15 | 1995-08-29 | Nec Corp | Wiring forming method of semiconductor device |
JP2005026687A (en) * | 2003-07-01 | 2005-01-27 | Ips Ltd | Vapor disposition method for thin film |
KR100748477B1 (en) * | 2005-07-26 | 2007-08-10 | 가부시키가이샤 히다치 하이테크놀로지즈 | Semiconductor device manufacturing method |
-
1991
- 1991-12-11 JP JP32720691A patent/JPH05160084A/en not_active Withdrawn
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07230993A (en) * | 1994-02-15 | 1995-08-29 | Nec Corp | Wiring forming method of semiconductor device |
JP2005026687A (en) * | 2003-07-01 | 2005-01-27 | Ips Ltd | Vapor disposition method for thin film |
KR100748477B1 (en) * | 2005-07-26 | 2007-08-10 | 가부시키가이샤 히다치 하이테크놀로지즈 | Semiconductor device manufacturing method |
US7364956B2 (en) | 2005-07-26 | 2008-04-29 | Hitachi High-Technologies Corporation | Method for manufacturing semiconductor devices |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 19990311 |